CN110828420A - 用于在垂直功率器件中减小接触注入物向外扩散的氧插入的Si层 - Google Patents

用于在垂直功率器件中减小接触注入物向外扩散的氧插入的Si层 Download PDF

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CN110828420A
CN110828420A CN201910729101.5A CN201910729101A CN110828420A CN 110828420 A CN110828420 A CN 110828420A CN 201910729101 A CN201910729101 A CN 201910729101A CN 110828420 A CN110828420 A CN 110828420A
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contact trench
contact
trench
doped
diffusion barrier
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M.波茨尔
O.布兰克
T.菲尔
B.格勒
R.哈瑟
S.里奥曼
A.梅瑟
M.罗施
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

用于在垂直功率器件中减小接触注入物向外扩散的氧插入的Si层。一种半导体器件包括：延伸到Si衬底中的栅沟槽；在Si衬底中的本体区，该本体区包括沿栅沟槽的侧壁延伸的沟道区；在本体区上方、在Si衬底中的源区；延伸到Si衬底中并且通过源区的一部分和本体区的一部分与栅沟槽分离的接触沟槽，该接触沟槽填充有导电材料，该导电材料接触在接触沟槽的侧壁处的源区和在接触沟槽的底部处的高掺杂本体接触区；以及沿接触沟槽的侧壁形成并且被设置在高掺杂本体接触区和沟道区之间的扩散阻挡结构，该扩散阻挡结构包括Si和氧掺杂Si的交替层。

Description

用于在垂直功率器件中减小接触注入物向外扩散的氧插入的 Si层
背景技术
随着基于沟槽的晶体管的尺寸缩小，高掺杂的源/本体接触对在沟道区附近掺杂的净本体的影响变得更加重要。对于与本体掺杂相比具有高2-3个数量级的掺杂水平的源/本体接触扩散的更宽横向分布，器件的Vth（阈值电压）和RonA（导通状态电阻）增加。增加源/本体接触与沟道区之间的距离引起在高漏极电压下耗尽本体，这可能导致高DIBL（漏致引发的阻挡降低）。此外，沟槽宽度和接触宽度两者的工艺窗口变化以及接触不对准必须变得更小以避免这些不利影响（更高的Vth、更高的RonA和更高的DIBL）。
因此，更好地控制源/本体接触掺杂的横向外扩散是合期望的。
发明内容
根据半导体器件的实施例，该半导体器件包括：延伸到Si衬底中的栅沟槽；在Si衬底中的本体区，该本体区包括沿栅沟槽的侧壁延伸的沟道区；在本体区上方、在Si衬底中的源区；延伸到Si衬底中并且通过源区的一部分和本体区的一部分与栅沟槽分离的接触沟槽，该接触沟槽填充有导电材料，该导电材料接触在接触沟槽的侧壁处的源区和在接触沟槽的底部处的高掺杂本体接触区；以及沿接触沟槽的侧壁形成并且被设置在高掺杂本体接触区与沟道区之间的扩散阻挡结构，该扩散阻挡结构包括Si和氧掺杂Si的交替层。
在实施例中，扩散阻挡结构可以沿接触沟槽的底部延伸。
单独地或以组合的形式，高掺杂本体接触区可以仅由扩散阻挡结构横向限制，该扩散阻挡结构不在接触沟槽的底部。
单独地或以组合的形式，填充接触沟槽的导电材料可以延伸到Si衬底的前主表面上超出扩散阻挡结构并且在朝向栅沟槽的方向上延伸。
单独地或以组合的形式，扩散阻挡结构可以包括在Si和氧掺杂Si的交替层上外延生长的Si覆盖层。
单独地或以组合的形式，Si衬底可以包括在基底Si衬底上生长的一个或多个Si外延层。
根据制造半导体器件的方法的实施例，该方法包括：形成延伸到Si衬底中的栅沟槽；形成接触沟槽，该接触沟槽延伸到Si衬底中并且与栅沟槽分离；在接触沟槽的底部处、在Si衬底中形成高掺杂本体接触区；沿接触沟槽的侧壁形成扩散阻挡结构，该扩散阻挡结构包括Si和氧掺杂Si的交替层；在Si衬底中形成本体区，该本体区包括沿栅沟槽的侧壁延伸的沟道区；在本体区上方、在Si衬底中形成源区；以及利用导电材料填充接触沟槽，该导电材料接触在接触沟槽侧壁处的源区和在接触沟槽的底部处的高掺杂本体接触区。
在实施例中，形成扩散阻挡结构可以包括，在利用导电材料填充接触沟槽之前，在接触沟槽的侧壁和底部上外延生长Si和氧掺杂Si的交替层。
单独地或以组合的形式，该方法可以进一步包括在Si和氧掺杂Si的交替层上外延生长Si覆盖层。
单独地或以组合的形式，形成高掺杂本体接触区可以包括将掺杂剂物质注入到在接触沟槽的底部处的Si和氧掺杂Si的交替层中，以及使Si衬底退火以激活注入的掺杂剂物质。
单独地或以组合的形式，该方法可以进一步包括从接触沟槽的底部的至少一部分去除Si和氧掺杂Si的交替层。
单独地或以组合的形式，从接触沟槽的底部的至少一部分去除Si和氧掺杂Si的交替层可以包括：在Si和氧掺杂Si的交替层上外延生长Si覆盖层；在Si覆盖层上沉积共形间隔体氧化物；各向异性地蚀刻共形间隔体氧化物，以暴露在接触沟槽的底部处的扩散阻挡结构；蚀刻掉在接触沟槽的底部处的暴露的扩散阻挡结构；以及在蚀刻掉在接触沟槽的底部处的暴露的扩散阻挡结构之后，去除共形间隔体氧化物。
单独地或以组合的形式，形成扩散阻挡结构可以包括，在利用导电材料填充接触沟槽之前，仅在接触沟槽的侧壁上而不是底部上外延生长Si和氧掺杂Si的交替层。
单独地或以组合的形式，该方法可以进一步包括在Si和氧掺杂Si的交替层上外延生长Si覆盖层。
单独地或以组合的形式，形成高掺杂本体接触区可以包括：将掺杂剂物质注入到接触沟槽的底部的区中，该接触沟槽的底部的区没有Si和氧掺杂Si的交替层，以及使Si衬底退火以激活注入的掺杂剂物质。
单独地或以组合的形式，该方法可以进一步包括，在利用导电材料填充接触沟槽之前，往回蚀刻形成在Si衬底的前主表面上的绝缘层，使得绝缘层具有开口，该开口与接触沟槽对准并且比接触沟槽和扩散阻挡结构的组合宽度更宽。
单独地或以组合的形式，利用导电材料填充接触沟槽可以包括：将导电材料沉积在接触沟槽中以及沉积在绝缘层中形成的开口中，使得导电材料延伸到Si衬底的前主表面上超出扩散阻挡结构并且在朝向栅沟槽的方向上延伸。
单独地或以组合的形式，形成扩散阻挡结构可以包括，在形成本体区和源区之前，在接触沟槽的侧壁和底部上外延生长Si和氧掺杂Si的交替层。
单独地或以组合的形式，该方法可以进一步包括，在形成本体区和源区之前，在Si和氧掺杂Si的交替层上外延生长Si覆盖层。
单独地或以组合的形式，该方法可以进一步包括从接触沟槽的底部的至少一部分去除Si和氧掺杂Si的交替层。
单独地或以组合的形式，从接触沟槽的底部的至少一部分去除Si和氧掺杂Si的交替层可以包括：在Si和氧掺杂Si的交替层上外延生长Si覆盖层；在Si覆盖层上沉积共形间隔体氧化物；各向异性地蚀刻共形间隔体氧化物，以暴露在接触沟槽的底部处的扩散阻挡结构；蚀刻掉在接触沟槽的底部处的暴露的扩散阻挡结构；以及在蚀刻掉在接触沟槽的底部处的暴露的扩散阻挡结构之后，去除共形间隔体氧化物。
单独地或以组合的形式，形成扩散阻挡结构可以包括：在形成本体区和源区之前，在接触沟槽的底部处形成牺牲绝缘层；在形成牺牲绝缘层之后，在接触沟槽的侧壁上外延生长Si和氧掺杂Si的交替层；在外延生长Si和氧掺杂Si的交替层之后，从接触沟槽的底部去除牺牲绝缘层。
单独地或以组合的形式，该方法可以进一步包括：在形成扩散阻挡结构之后并且在形成源区和本体区之前，利用牺牲塞材料填充接触沟槽；在利用牺牲塞材料填充接触沟槽之后，在Si衬底中形成源区和本体区；在形成源区和本体区之后，去除牺牲塞材料；在去除牺牲塞材料之后并且在用导电材料填充接触沟槽之前，将掺杂剂物质注入到接触沟槽的底部；以及使Si衬底退火以激活注入的掺杂剂物质，从而形成高掺杂本体接触区。
在阅读以下详细描述并且在查看附图时，本领域技术人员将意识到附加的特征和优点。
附图说明
附图的要素不一定相对于彼此是按比例的。同样的附图标记标明对应的类似部分。可以组合各种图示实施例的特征，除非它们彼此排斥。在附图中描绘实施例，并且在以下描述中详述实施例。
图1图示了具有扩散阻挡结构的基于沟槽的半导体器件的实施例的部分横截面视图。
图2A至2F图示了在制造过程的不同阶段期间图1中所示的基于沟槽的半导体器件的相应横截面视图。
图3图示了具有扩散阻挡结构的基于沟槽的半导体器件的另一实施例的部分横截面视图。
图4图示了具有扩散阻挡结构的基于沟槽的半导体器件的另一实施例的部分横截面视图。
图5A至图5D图示了从接触沟槽的底部的至少一部分省略扩散阻挡结构的实施例的相应横截面视图。
图6A至图6L图示了在制造过程的不同阶段期间基于沟槽的半导体器件的相应部分横截面视图，其中在器件的本体区和源区之前形成扩散阻挡结构。
具体实施方式
本文中描述的实施例控制基于沟槽的晶体管的源/本体接触掺杂的横向外扩散，从而对于高掺杂的源/本体接触和栅沟槽的给定几何变化允许更窄的Vth、RonA和DIBL分布，和/或对于给定的Vth、RonA和DIBL窗口允许器件的源/本体接触与沟道区之间的横向间距减小。通过插入扩散阻挡结构来更好地控制源/本体接触掺杂的横向外扩散，该扩散阻挡结构包括在高掺杂源/本体接触与器件的沟道区之间的Si和氧掺杂Si的交替层。扩散阻挡结构的氧掺杂Si层限制源/本体接触掺杂的横向外扩散，从而控制源/本体接触掺杂在朝向沟道区的方向上的横向外扩散。扩散阻挡结构使得能够实现例如窄沟槽MOSFET的更窄Vth分布，或者对于预定的Vth分布宽度，使得能够实现接触沟槽与栅沟槽之间的更小距离。接下来更详细地描述具有这样的扩散阻挡结构的半导体器件的实施例，以及对应的制造方法。
图1图示了基于沟槽的半导体器件100的实施例的部分横截面视图。半导体器件100包括：延伸到Si衬底104中的一个或多个栅沟槽102。Si衬底104可以包括在基底Si衬底上生长的一个或多个Si外延层。设置在每个栅沟槽102中的栅电极106通过栅电介质108与周围的半导体材料绝缘。场电极110可以设置在对应的栅电极106下方、在每个栅沟槽102中，并且通过场电介质112与周围的半导体材料和栅电极106绝缘。栅电介质108和场电介质112可以包括相同或不同的材料，并且可以具有相同或不同的厚度。代替地，场电极110可以形成在与栅沟槽102分离的不同沟槽中或被完全省略，这取决于半导体器件的类型。基于沟槽的半导体器件100可以是功率半导体器件，诸如功率MOSFET（金属氧化物半导体场效应晶体管）、IGBT（绝缘栅双极晶体管）等。
基于沟槽的半导体器件100进一步包括：形成在Si衬底104中的本体区114。本体区114包括沟道区116，该沟道区116沿对应的栅沟槽102的侧壁118垂直延伸。半导体器件100还包括在本体区114上方、在Si衬底104中形成的源区120。通过向栅电极106施加栅电势来控制流过沟道区116的垂直电流。在漂移区122的下方形成漏区或集电区（未示出）。取决于器件的类型，可以在漂移区域122中和/或漂移区域122与漏极/集电区之间形成附加结构。例如，在IGBT型器件的情况下，可以在漂移区域122中形成电荷补偿结构和/或可以在漂移区域122与漏极/集电区之间形成场停止层。再一次，具有沟槽栅的任何类型的半导体器件都可以利用本文中描述的扩散阻挡教导。
基于沟槽的半导体器件100进一步包括：延伸到Si衬底104中的接触沟槽124。接触沟槽124通过源区120的一部分和本体区114的一部分与每个相邻的栅沟槽102分离。接触沟槽124填充有导电材料126（诸如掺杂多晶硅、金属等），该导电材料126接触在接触沟槽124的侧壁处的源区120，和在接触沟槽124的底部处的高掺杂本体接触区128。填充接触沟槽124的导电材料126可以延伸到Si衬底104的前主表面130上超出扩散阻挡结构132并且在朝向栅沟槽102的方向上延伸，使得导电材料126接触沿着栅沟槽102与扩散阻挡结构132之间的Si衬底104的前主表面130的源区120。
在接触沟槽124的底部处的高掺杂本体接触区128具有与本体区114相同的掺杂类型，但是处于更高的浓度，以提供与填充了接触沟槽124的导电材料126的良好欧姆接触。例如，在n沟道器件的情况下，源区120和漂移区域122是n型掺杂的，并且本体区114、沟道区116和高掺杂本体接触区128是p型掺杂的。相反地，在p沟道器件的情况下，源区120和漂移区122是p型掺杂的，并且本体区114、沟道区116和高掺杂本体接触区128是n型掺杂的。
在任一种情况下，至少沿着接触沟槽124的侧壁形成扩散阻挡结构132，并且将其设置在高掺杂本体接触区126与沟道区116之间。扩散阻挡结构132还可以沿着接触沟槽124的底部延伸（如图1所示）、仅仅沿着侧壁延伸，或者沿着侧壁和底部的仅一部分延伸，如本文中之后更详细描述的。
扩散阻挡结构132包括Si 134和氧掺杂Si 136的交替层。Si 134和氧掺杂Si 136的交替层形成了通过外延而生长的氧掺杂硅区。在实施例中，每个氧掺杂Si层136的氧浓度低于5e14cm-3。每个氧掺杂Si层136可以具有在原子范围内的厚度（例如，一个或若干个原子厚度）或在纳米范围内的厚度，以确保用于在氧掺杂Si层136上生长Si的足够晶体信息。Si 134和氧掺杂Si 136的交替层可以通过与分别吸附在Si层表面上的氧层相间地外延生长Si层来实现，例如，具有对于氧掺杂Si层136的特定有限的厚度以确保充足的Si生长。
图1提供了扩散阻挡结构132的分解视图，该扩散阻挡结构132还可以包括在Si衬底104与Si 134和氧掺杂Si 136的交替层之间的Si缓冲层138，和/或在Si 134和氧掺杂Si136的交替层上外延生长的覆盖层140。Si缓冲层138可以相对较薄，例如，在2-5 nm厚的范围内。可以在注入或蚀刻步骤之后生长Si缓冲层138。覆盖层140在器件100的该区中提供高载流子迁移率。可以省略缓冲层138和覆盖层140中的一个或两个。扩散阻挡结构132的氧掺杂Si层136限制源/本体接触掺杂的横向外扩散，从而控制源/本体接触掺杂在朝向沟道区116的方向上的横向外扩散。扩散阻挡结构132的氧掺杂Si层136还可以改进器件100的垂直沟道区116内的载流子迁移率。
可以通过向Si晶格引入氧部分单层来形成扩散阻挡结构132的氧掺杂Si层136。间隙地放置氧原子以最小化对Si晶格的破坏。Si原子层134使相邻的氧部分单层136分离。Si134和氧掺杂Si 136的交替层可以通过在不同步骤处具有氧吸收的Si外延来形成。例如，可以在外延过程期间控制温度和气体条件以形成部分氧单层136。可以例如通过控制氧前体到外延室中的引入而在Si的外延层134之间引入/结合氧。所得到的扩散阻挡结构132包括与没有氧的标准Si外延层134相间的单层136，该单层136主要包括Si但具有一定掺杂水平或浓度水平的氧。扩散阻挡结构132还可以包括在Si 134和氧掺杂Si 136的交替层上外延生长的Si覆盖层140，或者可以省略Si覆盖层140。
图2A至图2F图示了在制造过程的不同阶段期间图1中所示的基于沟槽的半导体器件100的相应横截面视图。
图2A示出了在形成栅沟槽102、本体区114和源区120之后的器件100。可以使用用于形成栅沟槽、本体区和源区的任何常见半导体制造过程，例如，诸如沟槽掩模和蚀刻、沟槽填充、掺杂剂注入和激活（退火）等。
图2B示出了在将接触沟槽124蚀刻到相邻栅沟槽102之间的半导体台面中的Si衬底104中之后的器件100。可以使用任何常见的沟槽蚀刻过程。例如，可以在Si衬底104的前主表面130上形成诸如氧化硅之类的硬掩模/绝缘层200，并且使其图案化以形成开口202。然后可以各向同性地蚀刻Si衬底104的暴露部分以形成接触沟槽124，该接触沟槽124的宽度（W1）大于硬掩模200中的开口202的宽度（W2）。
图2C示出了在接触沟槽124的侧壁和底部上外延生长扩散阻挡结构132之后的器件100。扩散阻挡结构132包括Si 134和氧掺杂Si 136的交替层。可以在Si 134和氧掺杂Si136的交替层上外延生长Si覆盖层140。可以省略Si覆盖层140。扩散阻挡结构132可以原位或之后被掺杂有与源区120相同的导电类型，以提供源区120与随后沉积在接触沟槽124中的导电材料126之间的良好欧姆接触。
图2D示出了在将扩散阻挡结构132注入接触沟槽124的下部期间的器件100，该接触沟槽124的下部具有与本体区114相同的导电类型的掺杂剂204，以提供本体区114与随后沉积在接触沟槽124中的导电材料126之间的良好欧姆接触。通过退火激活注入的掺杂剂204在接触沟槽124的底部处形成高掺杂本体接触区128，其具有与本体区114相同的掺杂类型，但是处于更高的浓度以提供与随后沉积在接触沟槽124中的导电材料126的良好欧姆接触。扩散阻挡结构132的氧掺杂Si层136限制源/本体接触掺杂的横向外扩散，从而控制源/本体接触掺杂在朝向沟道区116的方向上的横向外扩散。在一个实施例中，扩散阻挡结构132存在于接触沟槽124的底部处，如图2D所示。根据该实施例，扩散阻挡结构132的氧掺杂Si层136还限制源/本体接触掺杂在朝向漂移区域122的方向上的垂直外扩散。在本文中之后更详细描述的实施例中，扩散阻挡结构132部分或完全地从接触沟槽124的底部省略，并且因此不限制源/本体接触掺杂的垂直外扩散。
图2E示出了在往回蚀刻硬掩模200以加宽（W2’）掩模200中的开口202之后的器件100。可以使用任何标准的电介质回蚀刻过程。硬掩模200中的加宽开口202与接触沟槽124对准，并且比接触沟槽124和扩散阻挡结构132的组合宽度（W3）更宽。
图2F示出了在利用导电材料126填充接触沟槽124之后的器件。导电材料126接触在接触沟槽124的侧壁处的源区120和在接触沟槽124的底部处的高掺杂本体接触区128。导电材料126可以延伸到Si衬底104的前主表面130上超出扩散阻挡结构132并且在朝向栅沟槽102的方向上延伸，例如，如果硬掩模200中的开口202先前被加宽的话，如图2E中所示。
图3图示了基于沟槽的半导体器件300的另一实施例的部分横截面视图。图3中所示的实施例类似于图1中所示的实施例。然而，不同的是，在扩散阻挡结构132的覆盖层140中注入和激活的体接触掺杂剂延伸到器件300的源区120中。
图4图示了基于沟槽的半导体器件400的另一实施例的部分横截面视图。图4中所示的实施例类似于图1和图3中所示的实施例。然而，不同的是，从接触沟槽124的底部省略扩散阻挡结构132，并且因此不限制源/本体接触掺杂的垂直外扩散。根据该实施例，从高掺杂本体接触区128向外扩散的掺杂剂被垂直地引到漂移区域/Si衬底122/104的更深处。通过仅在接触沟槽124的侧壁上而不是底部上外延生长Si 134和氧掺杂Si 136的交替层，可以从接触沟槽132的底部省略扩散阻挡结构132。例如，可以在接触沟槽124的底部处形成电介质间隔体（未示出），以防止在沟槽底部处外延生长扩散阻挡结构132。
图5A至图5D图示了从接触沟槽124的底部的至少一部分省略扩散阻挡结构132的另一实施例的相应横截面视图。
图5A示出了在接触沟槽124的侧壁和底部上形成扩散阻挡结构132之后的半导体器件500，例如，如在本文中先前结合图2C所描述的。共形间隔体氧化物502也沉积在扩散阻挡结构132的Si覆盖层140上。如果省略覆盖层140，则将共形间隔体氧化物502直接沉积在扩散阻挡结构132的Si 134和氧掺杂Si 136的交替层中的最上面的一个上。在任一种情况下，可以使用任何标准的共形间隔体氧化物，诸如氧化硅。
图5B示出了在从顶部各向异性蚀刻共形间隔体氧化物502期间的半导体器件500，以在接触沟槽124的底部处暴露扩散阻挡结构132。各向异性蚀刻由图5B中的向下箭头表示。如果提供Si覆盖层140，则覆盖层140将在接触沟槽124的底部处暴露。否则，将暴露Si134和氧掺杂Si 136的交替层中的最上面一层。可以使用任何标准的电介质各向异性蚀刻过程从接触沟槽124的底部去除共形间隔体氧化物502。
图5C示出了在蚀刻掉接触沟槽124的底部处暴露的扩散阻挡结构132期间的半导体器件500。Si蚀刻由图5C中的向下箭头表示。可以使用任何标准的Si蚀刻过程。
图5D示出了在蚀刻掉接触沟槽124的底部处的暴露的扩散阻挡结构132之后并且在去除了共形间隔体氧化物502之后的半导体器件500。在蚀刻掉接触沟槽124的底部处的暴露的扩散阻挡结构132之后，可以使用任何标准的电介质去除过程（例如，各向同性蚀刻）来去除共形氧化物间隔体502。然后，继续处理器件500以在接触沟槽124的底部处形成高掺杂本体接触区，填充接触沟槽124等，例如，如图2D至图2F所图示的。
图6A至图6L图示了在制造过程的不同阶段期间基于沟槽的半导体器件600的相应部分横截面视图，其中在本体区114和源区120之前形成扩散阻挡结构132。
图6A示出了在Si衬底104中形成栅沟槽102之后并且在Si衬底104的前主表面130上形成诸如例如氧化硅之类的硬掩模/绝缘层200之后的半导体器件500。可以使用用于形成栅沟槽和硬掩模的任何常见半导体制造过程，例如，诸如沟槽掩模和蚀刻、电介质沉积和/或热氧化等。
图6B示出了在将接触沟槽124蚀刻到相邻栅沟槽102之间的Si衬底104中之后的半导体器件600。可以使用任何常见的沟槽蚀刻过程来形成接触沟槽124。例如，可以在Si衬底104的前主表面130上、在硬掩模200中形成开口202，并且可以各向同性地蚀刻Si衬底104的暴露部分以形成比硬掩模200中的开口202更宽的接触沟槽124。
图6C示出了在接触沟槽124的侧壁和底部上外延生长扩散阻挡结构132之后的半导体器件600，例如，如本文中先前结合图2C所描述的。可以在Si 134和氧掺杂Si 136的交替层上外延生长Si覆盖层140。替换地，可以省略Si覆盖层140。
图6D示出了替换实施例，其中从接触沟槽124的底部省略了扩散阻挡结构132。可以部分地或完全地从接触沟槽124的底部省略扩散阻挡结构132。例如，通过仅在接触沟槽124的侧壁上而不是底部上外延生长Si 134和氧掺杂Si 136的交替层，可以从接触沟槽124的底部省略扩散阻挡结构132。可以在接触沟槽124的底部处形成电介质间隔体，以防止扩散阻挡结构132在沟槽底部处外延生长。
在一个实施例中，在接触沟槽124的底部处形成牺牲绝缘层602。在形成牺牲绝缘层602之后，仅在接触沟槽132的侧壁上外延生长Si 134和氧掺杂Si 136的交替层。在外延生长Si 134和氧掺杂Si 136的交替层之后，从接触沟槽124的底部去除牺牲绝缘层602。
在另一实施例中，Si 134和氧掺杂Si 136的交替层可以生长在接触沟槽124的侧壁和底部上，并且然后被从沟槽底部的部分或全部沟槽底部中去除，例如，如本文中先前结合图5A至图5D所描述的。
图6E至图6L图示了沿着接触沟槽124的底部设置的扩散阻挡结构132的部分，其中利用虚线来指示在接触沟槽124的底部处可以存在或可以不存在扩散阻挡结构132。
图6E示出了利用牺牲塞材料604（例如诸如碳或另一材料）填充接触沟槽124之后的半导体器件600，该牺牲塞材料604可选择性地蚀刻到形成在Si衬底104的前主表面130上的硬掩模200的材料。
图6F示出了在往回蚀刻硬掩模200接着形成屏蔽氧化物606之后的半导体器件600。
图6G示出了在例如通过掺杂剂注入以及由退火进行掺杂剂激活而在Si衬底104中形成本体区114和源区120之后的半导体器件600。使用具有相反导电类型的掺杂剂来形成本体区114和源区120。注入掺杂剂然后通过退火对掺杂剂进行激活以形成本体区114和源区120。掺杂剂注入由图6G中的向下箭头表示。如果从接触沟槽124的底部省略扩散阻挡结构132，则可以将掺杂剂物质直接注入到接触沟槽124的底部处的Si衬底104中，该Si衬底没有Si 134和氧掺杂Si 136的交替层。
图6H示出了在Si衬底104之上沉积台面保护氧化物608之后的半导体器件600。
图6I示出了在台面保护氧化物608被平坦化并且暴露了接触沟槽124中的牺牲塞材料604的顶表面610之后的半导体器件600。可以使用任何标准的平坦化过程，例如诸如CMP（化学机械抛光）。
图6J示出了在从接触沟槽124去除牺牲塞材料604之后的半导体器件600。被用来从接触沟槽124去除牺牲塞材料604的过程取决于塞材料的类型。例如，该过程可以涉及湿法和/或干法化学蚀刻。
图6K示出了在将掺杂剂物质612注入到接触沟槽124的底部中期间的半导体器件600。掺杂剂类型（p型或n型）与本体区114的掺杂剂类型相同，但是处于更高的浓度以形成欧姆接触。使Si衬底104退火以激活注入的掺杂剂物质612，从而在接触沟槽124的底部处形成高掺杂本体接触区128。扩散阻挡结构132的氧掺杂Si层136至少限制源/本体接触掺杂在朝向垂直沟道区116的方向上的横向外扩散。如果扩散阻挡结构132存在于接触沟槽124的底部处，则扩散阻挡结构132的氧掺杂Si层136还限制源/本体接触掺杂在朝向漂移区域122的方向上的垂直外扩散。
图6L示出了在利用导电材料126填充接触沟槽124之后的半导体器件600。导电材料126接触在接触沟槽124的侧壁处的源区120和在接触沟槽124的底部处的高掺杂本体接触区128。导电材料126可以延伸到Si衬底104的前主表面130上超出扩散阻挡结构132并且在朝向栅沟槽102的方向上延伸，如果台面保护氧化物608中的开口在沉积导电材料126之前被加宽的话，例如，如图2E中所示。
为了易于描述，使用诸如“之下”、“下方”、“下”、“之上”、“上”等等的空间相对术语来解释一个元件相对于第二元件的定位。除了与图中描绘的取向不同的取向之外，这些术语意图涵盖器件的不同取向。此外，诸如“第一”、“第二”等等的术语也被用来描述各种元件、区、区段等，并且也不意图是限制性的。同样的术语遍及说明书指代同样的元件。
如本文中使用的，术语“具有”、“含有”、“包括”、“包含”等等是开放式术语，其指示所陈述的元件或特征的存在，但并不排除附加的元件或特征。除非上下文另行明确指示的，冠词“一”、“一个”和“该”意图包括复数以及单数。
考虑到上面的变型和应用的范围，应该理解的是，本发明不受前述描述的限制，也不受附图的限制。代替地，本发明仅受所附权利要求及其合法等同物的限制。

Claims (22)

1.一种半导体器件，其包括：
延伸到Si衬底中的栅沟槽；
在所述Si衬底中的本体区，所述本体区包括沿所述栅沟槽的侧壁延伸的沟道区；
在所述本体区上方、在所述Si衬底中的源区；
延伸到所述Si衬底中并且通过所述源区的一部分和所述本体区的一部分与所述栅沟槽分离的接触沟槽，所述接触沟槽填充有导电材料，所述导电材料接触在所述接触沟槽的侧壁处的源区和在所述接触沟槽的底部处的高掺杂本体接触区；以及
沿所述接触沟槽的侧壁形成并且被设置在所述高掺杂本体接触区与所述沟道区之间的扩散阻挡结构，所述扩散阻挡结构包括Si和氧掺杂Si的交替层。
2.根据权利要求1所述的半导体器件，其中所述扩散阻挡结构沿所述接触沟槽的底部延伸。
3.根据权利要求1所述的半导体器件，其中所述高掺杂本体接触区仅由所述扩散阻挡结构横向限制，所述扩散阻挡结构不在所述接触沟槽的底部。
4.根据权利要求1所述的半导体器件，其中填充所述接触沟槽的导电材料可以延伸到所述Si衬底的前主表面上超出所述扩散阻挡结构并且在朝向所述栅沟槽的方向上延伸。
5.根据权利要求1所述的半导体器件，其中所述扩散阻挡结构包括在所述Si和氧掺杂Si的交替层上外延生长的Si覆盖层。
6.一种制造半导体器件的方法，所述方法包括：
形成延伸到Si衬底中的栅沟槽；
形成接触沟槽，所述接触沟槽延伸到所述Si衬底中并且与所述栅沟槽分离；
在所述接触沟槽的底部处、在所述Si衬底中形成高掺杂本体接触区；
沿所述接触沟槽的侧壁形成扩散阻挡结构，所述扩散阻挡结构包括Si和氧掺杂Si的交替层；
在所述Si衬底中形成本体区，所述本体区包括沿所述栅沟槽的侧壁延伸的沟道区；
在所述本体区上方、在所述Si衬底中形成源区；以及
利用导电材料填充所述接触沟槽，所述导电材料接触在所述接触沟槽的侧壁处的源区和在所述接触沟槽的底部处的高掺杂本体接触区。
7.根据权利要求6所述的方法，其中形成所述扩散阻挡结构包括：
在利用所述导电材料填充所述接触沟槽之前，在所述接触沟槽的侧壁和底部上外延生长所述Si和氧掺杂Si的交替层。
8.根据权利要求7所述的方法，进一步包括：
在所述Si和氧掺杂Si的交替层上外延生长Si覆盖层。
9.根据权利要求7所述的方法，其中形成所述高掺杂本体接触区包括：
将掺杂剂物质注入到在所述接触沟槽的底部处的Si和氧掺杂Si的交替层中；以及
使所述Si衬底退火以激活注入的掺杂剂物质。
10.根据权利要求7所述的方法，进一步包括：
从所述接触沟槽的底部的至少一部分去除所述Si和氧掺杂Si的交替层。
11.根据权利要求10所述的方法，其中从所述接触沟槽的底部的至少一部分去除所述Si和氧掺杂Si的交替层包括：
在所述Si和氧掺杂Si的交替层上外延生长Si覆盖层；
在所述Si覆盖层上沉积共形间隔体氧化物；
各向异性地蚀刻所述共形间隔体氧化物，以暴露在所述接触沟槽的底部处的扩散阻挡结构；
蚀刻掉在所述接触沟槽的底部处的暴露的扩散阻挡结构；以及
在蚀刻掉在所述接触沟槽的底部处的暴露的扩散阻挡结构之后，去除所述共形间隔体氧化物。
12.根据权利要求6所述的方法，其中形成所述扩散阻挡结构包括：
在利用所述导电材料填充所述接触沟槽之前，仅在所述接触沟槽的侧壁上而不是底部上外延生长所述Si和氧掺杂Si的交替层。
13.根据权利要求12所述的方法，进一步包括：
在所述Si和氧掺杂Si的交替层上外延生长Si覆盖层。
14.根据权利要求12所述的方法，其中形成所述高掺杂本体接触区包括：
将掺杂剂物质注入到所述接触沟槽的底部中，所述接触沟槽的底部没有所述Si和氧掺杂Si的交替层；以及
使所述Si衬底退火以激活注入的掺杂剂物质。
15.根据权利要求6所述的方法，进一步包括：
在利用所述导电材料填充所述接触沟槽之前，往回蚀刻形成在所述Si衬底的前主表面上的绝缘层，使得所述绝缘层具有开口，所述开口与所述接触沟槽对准并且比所述接触沟槽和所述扩散阻挡结构的组合宽度更宽。
16.根据权利要求15所述的方法，其中利用所述导电材料填充所述接触沟槽包括：
将所述导电材料沉积在所述接触沟槽中以及沉积在所述绝缘层中形成的开口中，使得所述导电材料延伸到所述Si衬底的前主表面上超出所述扩散阻挡结构并且在朝向所述栅沟槽的方向上延伸。
17.根据权利要求6所述的方法，其中形成所述扩散阻挡结构包括：
在形成所述本体区和所述源区之前，在所述接触沟槽的侧壁和底部上外延生长所述Si和氧掺杂Si的交替层。
18.根据权利要求17所述的方法，进一步包括：
在形成所述本体区和所述源区之前，在所述Si和氧掺杂Si的交替层上外延生长Si覆盖层。
19.根据权利要求17所述的方法，进一步包括：
从所述接触沟槽的底部的至少一部分去除所述Si和氧掺杂Si的交替层。
20.根据权利要求19所述的方法，其中从所述接触沟槽的底部的至少一部分去除所述Si和氧掺杂Si的交替层包括：
在所述Si和氧掺杂Si的交替层上外延生长Si覆盖层；
在所述Si覆盖层上沉积共形间隔体氧化物；
各向异性地蚀刻所述共形间隔体氧化物，以暴露在所述接触沟槽的底部处的扩散阻挡结构；
蚀刻掉在所述接触沟槽的底部处的暴露的扩散阻挡结构；以及
在蚀刻掉在所述接触沟槽的底部处的暴露的扩散阻挡结构之后，去除所述共形间隔体氧化物。
21.根据权利要求6所述的方法，其中形成所述扩散阻挡结构包括：
在形成所述本体区和所述源区之前，在所述接触沟槽的底部处形成牺牲绝缘层；
在形成所述牺牲绝缘层之后，在所述接触沟槽的侧壁上外延生长所述Si和氧掺杂Si的交替层；
在外延生长所述Si和氧掺杂Si的交替层之后，从所述接触沟槽的底部去除所述牺牲绝缘层。
22.根据权利要求6所述的方法，进一步包括：
在形成所述扩散阻挡结构之后并且在形成所述源区和所述本体区之前，利用牺牲塞材料填充所述接触沟槽；
在利用所述牺牲塞材料填充所述接触沟槽之后，在所述Si衬底中形成所述源区和所述本体区；
在形成所述源区和所述本体区之后，去除所述牺牲塞材料；
在去除所述牺牲塞材料之后并且在利用所述导电材料填充所述接触沟槽之前，将掺杂剂物质注入到所述接触沟槽的底部中；以及
使所述Si衬底退火以激活注入的掺杂剂物质，从而形成所述高掺杂本体接触区。
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