CN110827912A

CN110827912A - Memory controller, operating method of memory controller, and memory system

Info

Publication number: CN110827912A
Application number: CN201910724921.5A
Authority: CN
Inventors: 金玟昱; 全甫晥; 孙弘乐; 申东旻; 李起准
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2018-08-07
Filing date: 2019-08-06
Publication date: 2020-02-21
Also published as: US11037646B2; US20210265005A1; US20200050513A1; DE102019111130A1; KR20200016606A

Abstract

The operating method of a memory controller that individually controls a plurality of memory cells includes: reading respective segments from a plurality of memory cells based on a plurality of control signals; generating an output codeword based on the segmentation; performing error correction decoding on the output codeword; updating at least one of a plurality of accumulated error pattern information respectively corresponding to the plurality of memory cells based on a result of the error correction decoding when the result of the error correction decoding indicates success; and adjusting at least one of the plurality of control signals based on at least one of the plurality of accumulated error pattern information when the result of the error correction decoding indicates a failure.

Description

Memory controller, operating method of memory controller, and memory system

Cross Reference to Related Applications

The present disclosure claims priority from korean patent application No. 10-2018-.

Technical Field

The present disclosure relates to a semiconductor memory system, and more particularly, to a memory system that performs an error correction operation based on an Error Correction Code (ECC).

Background

Semiconductor memory devices can be classified into volatile memory devices, in which data stored in the volatile memory devices disappears when power is turned off, and non-volatile memory devices, in which data stored in the non-volatile memory devices is retained even when power is turned off.

During a process of writing data to or reading data from the semiconductor memory device, errors may occur in the data. Generally, an error correction code may be added to data by the semiconductor memory device before writing the data. In the case where an error is detected in data during a read operation, the semiconductor memory device may restore the original data by correcting the detected error using an error correction code.

However, in the case where the data includes many erroneous bits, the probability of successfully correcting the data may be low. Further, in the case of re-reading data for the purpose of performing decoding and/or error correction again, power consumption increases.

Disclosure of Invention

Embodiments of the inventive concept provide a memory controller and a memory system, which can improve the probability of successfully performing error correction on data and can reduce power consumption according to error correction.

Embodiments of the inventive concept provide a method of operating a memory controller that individually controls a plurality of memory cells. The method comprises the following steps: reading, by a memory controller, respective segments from a plurality of memory cells based on a plurality of control signals; generating, by the memory controller, an output codeword based on the segmentation; performing, by the memory controller, error correction decoding on the output codeword; updating, by the memory controller, at least one of a plurality of accumulated error pattern information respectively corresponding to the plurality of memory cells based on a result of the error correction decoding when the result of the error correction decoding indicates success; and adjusting, by the memory controller, at least one of the plurality of control signals based on at least one of the plurality of accumulated error pattern information when the result of the error correction decoding indicates a failure.

Embodiments of the inventive concept also provide a memory controller including: a codeword circuit generating an output codeword based on a first segment read from a first memory cell according to a first control signal and a second segment read from a second memory cell according to a second control signal; an Error Correction Code (ECC) circuit that performs error correction decoding on the output codeword; and a control circuit that operates according to a result of the error correction decoding. The control circuit adjusts at least one of the first control signal and the second control signal based on at least one of first accumulated error pattern information corresponding to the first memory cell and second accumulated error pattern information corresponding to the second memory cell.

Embodiments of the inventive concept also provide a memory system, including: a first memory cell operating in response to a first control signal; a second memory cell operating in response to a second control signal; and a memory controller that reads the first segment from the first memory unit based on the first control signal and reads the second segment from the second memory unit based on the second control signal. The memory controller includes: a codeword circuit that generates an output codeword based on the first segment and the second segment; an Error Correction Code (ECC) circuit that performs error correction decoding on the output codeword; and a control circuit that operates according to a result of the error correction decoding. The control circuit adjusts at least one of the first control signal and the second control signal based on at least one of first accumulated error pattern information corresponding to the first memory cell and second accumulated error pattern information corresponding to the second memory cell.

Embodiments of the inventive concept also provide a memory controller including: a codeword circuit configured to generate an output codeword based on a first segment read from a first memory cell according to a first control signal and a second segment read from a second memory cell according to a second control signal; an Error Correction Code (ECC) circuit configured to perform error correction decoding on the output codeword; and a control circuit configured to: updating at least one of first accumulated error pattern information corresponding to the first memory cell and second accumulated error pattern information corresponding to the second memory cell when the result of the error correction decoding indicates success; and adjusting at least one of the first control signal and the second control signal based on at least one of the first accumulated error pattern information and the second accumulated error pattern information when a result of the error correction decoding indicates a failure.

Drawings

The above and other objects and features of the present inventive concept will become apparent in view of the following description of exemplary embodiments of the present inventive concept with reference to the accompanying drawings.

Fig. 1 illustrates a block diagram of a memory system according to an embodiment of the inventive concept.

FIG. 2 shows a block diagram of the memory controller of FIG. 1.

FIG. 3 illustrates a schematic diagram of one example of the memory system throttling control signal of FIG. 1.

FIG. 4 shows a block diagram of the memory controller of FIG. 3 operating according to decoding success.

FIG. 5 is a diagram illustrating an example of the memory controller of FIG. 4 updating an error pattern information table based on decoding success.

FIG. 6 shows a schematic diagram of an example of the memory controller of FIG. 4 adjusting a control signal according to decoding success.

Fig. 7A, 7B, and 7C are schematic diagrams illustrating an example in which a control circuit determines a read voltage level according to an embodiment of the inventive concept.

FIG. 8 shows a schematic diagram of an example of data successfully refreshing memory cells according to decoding by the memory controller of FIG. 4.

FIG. 9 illustrates a block diagram of the operation of the memory controller of FIG. 3 according to a decoding failure.

FIG. 10 is a diagram illustrating an example of the memory controller of FIG. 9 re-reading a segment based on a decoding failure.

Fig. 11 is a diagram illustrating an example in which the memory controller of fig. 9 performs decoding again according to a decoding failure.

Fig. 12 illustrates a flowchart of an operation of a memory controller according to an embodiment of the inventive concept.

Fig. 13 illustrates a flowchart of an operation corresponding to a case where the memory controller is decoded successfully, according to an embodiment of the inventive concept.

Fig. 14 illustrates a flowchart of an operation corresponding to a case where a memory controller fails to decode according to an embodiment of the inventive concept.

Fig. 15 illustrates a block diagram of an application of a memory system according to an embodiment of the inventive concept.

Detailed Description

Embodiments of the inventive concept will be described in detail and clearly below to the extent that they can be carried into effect by a person skilled in the art.

As is common in the field of the inventive concept, embodiments may be described and illustrated in terms of blocks performing the described functions. These blocks, which may be referred to herein as units or modules, are physically implemented by analog and/or digital circuitry, such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuitry, and the like, and may optionally be driven by firmware and/or software. For example, the circuitry may be embodied in one or more semiconductor chips, or on a substrate support such as a printed circuit board. The circuitry making up the block may be implemented by dedicated hardware or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware for performing some of the functions of the block and a processor for performing other functions of the block. Each block of an embodiment may be physically separated into two or more interactive and discrete blocks without departing from the scope of the inventive concept. Similarly, the blocks of an embodiment may be physically combined into more complex blocks without departing from the scope of the inventive concept.

The memory cell according to the embodiments of the inventive concept described below may mean any memory cell that can operate in response to a separate control signal. In embodiments of the inventive concept, the memory cells may include, for example, a memory device, a memory chip, a memory die, a memory group, a memory block, or a memory cell connected to one word line. For example, the memory cell according to an embodiment of the inventive concept may indicate a memory device in which a read voltage may be individually adjusted.

Accordingly, each memory cell according to embodiments of the inventive concept may be implemented with or as: a separate memory package, a separate memory device, a separate memory chip, or a separate memory die. Alternatively, the set of memory cells may be implemented with or as: a memory package, a memory device, a memory chip, or a memory die.

A memory cell or a set of memory cells according to embodiments of the inventive concept may be implemented with at least one of: volatile memory (e.g., static ram (sram), dynamic ram (dram), synchronous dram (sdram), etc.) and non-volatile memory (e.g., Read Only Memory (ROM), programmable ROM (prom), electrically programmable ROM (eprom), electrically erasable programmable ROM (eeprom), phase change ram (pram), magnetic ram (mram), resistive ram (rram), ferroelectric ram (fram), flash memory, etc.).

Fig. 1 illustrates a block diagram of a memory system according to an embodiment of the inventive concept. Referring to fig. 1, a memory system 1000 includes a memory controller 100 and a memory 200. Memory 200 may include a plurality of memory units MU11, MU12 through MU1 n; MU21, MU22 to MU2 n; and MUn1, MUn2 through MUnn (which may be referred to hereinafter as a plurality of memory units MU11 through MUnn).

The memory controller 100 may provide the plurality of control signals CTRL11 to CTRL1n, CTRL21 to CTRL2n, and CTRLn1 to CTRLn (hereinafter, may be referred to as a plurality of control signals CTRL11 to CTRLn) and the plurality of DATA11 to DATA1n, DATA21 to DATA2n, and DATAn1 to DATAnn (hereinafter, may be referred to as a plurality of DATA11 to DATAnn) to the memory 200 through the plurality of channels CH1, CH2 to CHn. For example, the memory controller 100 may provide control signals CTRL11 to CTRL1n and DATA11 to DATA1n through the first channel CH1, and may provide control signals CTRL21 to CTRL2n and DATA21 to DATA2n through the second channel CH 2.

Memory controller 100 may control each of memory units MU11 through MUnn based on control signals corresponding to memory units MU11 through MUnn, respectively. For example, memory controller 100 may control memory unit MU11 based on control signal CTRL11 corresponding to memory unit MU11 and may control memory unit MU12 based on control signal CTRL12 corresponding to memory unit MU 12. Memory controller 100 may control memory unit MU21 based on control signal CTRL21 corresponding to memory unit MU21 and may control memory unit MU22 based on control signal CTRL22 corresponding to memory unit MU 22.

In an embodiment, memory controller 100 may transmit a select signal for the purpose of individually controlling memory units MU11 through MUnn. The selection signal may be a signal indicating one of the memory cells connected to one channel. For example, memory controller 100 may control memory unit MU11 based on control signal CTRL11 and a select signal indicating memory unit MU 11.

The memory controller 100 may store data in the respective memory units MU11 through MUnn, and may read the stored data from the respective memory units MU11 through MUnn. For example, the memory controller 100 may provide the control signal CTRL11 and the DATA11 to the first channel CH1 to store the DATA11 in the memory unit MU 11. The memory controller 100 may provide a control signal CTRL21 to the second channel CH2 to store the DATA21 in the memory unit MU 21.

As described above, the memory system 1000 may include a plurality of memory cells, which may operate in response to various control signals. The memory controller 100 may manage control signals for the respective memory cells individually. That is, the memory controller 100 may control the respective memory cells based on different control signals. The memory controller 100 may control the respective memory cells by transmitting different control signals to different channels. In addition, the memory controller 100 may control the respective memory cells by transmitting different control signals to one channel.

As shown in fig. 1, memory controller 100 includes an Error Correction Code (ECC) circuit 110, a codeword circuit 120, and a control circuit 130. The ECC circuit 110 may generate an input codeword CW by performing encoding on DATA "provided from a host. The input codeword CW may be a data code to which an error correction code ECC is added.

The codeword circuit 120 may divide the input codeword CW' provided from the ECC circuit 110 into a plurality of segments SEG1 through SEGn. The codeword circuit 120 may divide the input codeword CW according to a predetermined division rule.

The control circuit 130 may control the respective memory units MU11 through MUnn based on control signals corresponding to the memory units MU11 through MUnn, respectively. For example, control circuitry 130 may store first segment SEG1 in memory unit MU11 based on control signal CTRL11 and may store second segment SEG2 in memory unit MU12 based on control signal CTRL 12.

Control circuit 130 may distribute and store segments SEG 1-SEGn in memory units MU 11-MUnn. In an embodiment, control circuitry 130 may distribute and store segments SEG1 through SEGn in memory cells connected to the same channel. For example, control circuit 130 may store segments SEG 1-SEGn in memory units MU 11-MU 1n, respectively. In another embodiment, control circuitry 130 may distribute and store segments SEG1 through SEGn in memory cells coupled to different channels. For example, control circuit 130 may store segments SEG1 through SEGn in memory units MU11 through MUn1, respectively. In another embodiment, control circuitry 130 may store segments SEG 1-SEGn in memory units MU 11-MUnn in any order.

The control circuit 130 may read the segments SEG1 through SEGn distributed and stored in the memory units MU11 through MUnn based on the control signals respectively corresponding to the memory units MU11 through MUnn.

Codeword circuit 120 may generate an output codeword CW based on the segments SEG 1-SEGn read from memory units MU 11-MUnn. The codeword circuit 120 may generate an output codeword CW according to a predetermined division rule. In an embodiment, the generated output codeword CW may comprise error bits generated during writing of segments SEG 1-SEGn to memory units MU 11-MUnn or reading of segments SEG 1-SEGn from memory units MU 11-MUnn. In this way, the bits of the input codeword CW' may be different from the bits of the corresponding output codeword CW.

The ECC circuit 110 may perform error correction decoding (hereinafter, referred to as "decoding") for correcting errors of the generated output codeword CW. For example, the ECC circuit 110 may perform hard decision decoding. The DATA "output from the ECC circuit 110 may be provided to the host according to the decoded result. For example, the ECC circuit 110 may provide the decoded codeword (i.e., the error-corrected codeword) to the host in the event that the decoding result indicates that the decoding operation was successful. The ECC circuit 110 may provide the decoding result to the control circuit 130.

Control circuit 130 may adjust the control signals corresponding to each of memory units MU11 through MUnn based on the decoding results from ECC circuit 110. In an embodiment, control circuitry 130 may adjust the control signals based on the accumulated error pattern information corresponding to each of memory units MU11 through MUnn. The accumulated error pattern information may be accumulated information generated based on error bits of data output from the memory cells.

Control circuit 130 may adjust the control signal such that the number of segmented error bits read from the memory cells is reduced. For example, since erroneous bits may occur during writing or reading of a segment, the control circuit 130 may adjust the control signal such that the write voltage level or the read voltage level to be supplied to the memory cell changes. However, the inventive concept is not limited to adjusting the control signal to change the write and/or read voltage levels. For example, control circuit 130 may adjust the control signal according to various conditions associated with the erroneous bits.

Depending on the adjusted control signals, control circuitry 130 may store data in memory units MU11 through MUnn or may read data from memory units MU11 through MUnn. Since the control signal is adjusted in such a way that the number of erroneous bits of the segment read from the memory cell is reduced, the number of erroneous bits of the output codeword CW generated on the basis of the adjusted control signal is reduced.

As described above, memory system 1000 may adjust the control signals corresponding to each of memory units MU11 through MUnn such that the number of erroneous bits of data read from each of memory units MU11 through MUnn is reduced. Thus, the Raw Bit Error Rate (RBER) of the memory system 1000 may be reduced.

The circuits 110 to 130 included in the memory controller 100 of fig. 1 may be implemented in the form of software, hardware, or a combination thereof. In embodiments, the software may be machine code, firmware, embedded code, and application software. For example, the hardware may include electrical circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, micro-electro-mechanical systems (MEMS), passive components, or a combination thereof.

Fig. 2 illustrates a block diagram of the memory controller of fig. 1 according to an embodiment of the inventive concept. Referring to fig. 2, the memory controller 100 includes an ECC circuit 110, a codeword circuit 120, a control circuit 130, a bus 140, a processor 150, a Random Access Memory (RAM)160, a Read Only Memory (ROM)170, a host interface 180, and a memory interface 190.

The operations of the ECC circuit 110, the codeword circuit 120 and the control circuit 130 are described with reference to fig. 1, and thus additional description will be omitted to avoid redundancy.

Bus 140 is configured to provide a channel between the components of memory controller 100. The processor 150 may control the overall operation of the memory controller 100. For example, ECC circuit 110, codeword circuit 120, and control circuit 130 may be driven by processor 150.

The RAM 160 may be used as a buffer memory, a cache memory, or a working memory of the memory controller 100. The RAM 160 may store codes and commands executed by the processor 150, and may store data processed by the processor 150. RAM 160 may include a Flash Translation Layer (FTL) 161. FTL 161 may be software or firmware that performs various management operations between a host and a memory unit such that the memory unit may be efficiently used. In an embodiment, FTL 161 stored in RAM 160 may be driven by processor 150.

In an embodiment, FTL 161 can assign one of the memory units to each of the segments. In this way, FTL 161 can manage information about memory units corresponding to a segment. Control circuitry 130 may store the segments in the assigned memory cells or may read the segments from the assigned memory cells.

The ROM170 may store various information required for the memory controller 100 to operate in the form of firmware. In the embodiment shown in fig. 2, FTL 161 is included in RAM 160. However, in other embodiments, the inventive concept is not so limited, and FTL 161 may be included in ROM 170.

Memory controller 100 may communicate with a host through host interface 180. Memory controller 100 may communicate with memory units through memory interface 190.

The operation of the memory controller 100 of fig. 1 will be described more fully with reference to fig. 3-11. For convenience of description, it is assumed that each of the plurality of channels corresponds to one memory cell. That is, the operation of the memory controller 100 will be described based on an example in which the memory controller 100 controls one memory cell through one channel, but the inventive concept is not limited thereto. Further, for convenience of description, the operation of the memory controller 100 will be described based on an example in which the control circuit 130 adjusts the control signal so that the read voltage level to be supplied to the memory cell is changed, but the inventive concept is not limited thereto.

FIG. 3 illustrates a schematic diagram of one example of the memory system throttling control signal of FIG. 1. Referring to fig. 3, a memory system 1000 includes a memory controller 100 and a plurality of

memory cells

210, 220 to 2nO (hereinafter may be referred to as memory cells 210 to 2 nO). The memory controller 100 may control the memory cells 210 to 2nO based on a plurality of control signals CTRL1, CTRL2 to CTRLn (which may be referred to as control signals (CTRL1 to CTRLn) hereinafter). Each of the memory cells 210 to 2nO may be individually operated based on a corresponding control signal.

Each of the memory cells 210 to 2nO may store a corresponding segment of a plurality of segments SEG1, SEG2 to SEG (hereinafter may be referred to as segments SEG1 to SEG). For example, first memory unit 210 may store first segment SEG1, second memory unit 220 may store second segment SEG2, and nth memory unit 2nO may store nth segment SEG.

Control circuit 130 may read stored segments SEG1 through SEGn from memory cells 210 through 2 nO. Control circuit 130 may read segments SEG1 through SEGn based on a control signal corresponding to the read voltage level of each of memory cells 210 through 2 nO. For example, the memory controller 100 may read the first segment SEG1 from the first memory cell 210 based on the control signal CTRL1 corresponding to the read voltage level L1, and may read the second segment SEG2 from the second memory cell 220 based on the control signal CTRL2 corresponding to the read voltage level L2. That is, the first memory cell 210 may output the first segment SEG1 by using the read voltage of the read voltage level L1 in response to the control signal CTRL1, and the second memory cell 220 may output the second segment SEG2 by using the read voltage of the read voltage level L2 in response to the control signal CTRL 2. The read voltage level L1 may be different from the read voltage level L2.

Codeword circuit 120 may generate an output codeword CW based on the first through nth segments SEG1 through SEGn thus read.

The ECC circuit 110 may perform decoding on the output codeword CW. The ECC circuit 110 may determine success or failure as a result of decoding the output codeword CW. In an embodiment, where the decoded codeword is generated by decoding the output codeword CW, the ECC circuit 110 may determine that the decoding is successful (i.e., the decoding is successful). In the case where a decoded codeword is not generated by decoding the output codeword CW, the ECC circuit 110 may determine that the decoding failed (i.e., the decoding failed).

In the case of outputting the decoding result, the control circuit 130 may adjust the control signals CTRL1 through CTRLn based on the accumulated error pattern information AEPI of the error pattern information table 101. The control circuit 130 may adjust the control signals associated with a particular memory cell based on the accumulated error pattern information AEPI corresponding to the particular memory cell. For example, the error pattern information table 101 may be stored in the RAM 160 or the ROM170 of fig. 2. For example, the error pattern information table 101 may store the accumulated error pattern information AEPI1, AEPI2, to AEPIn for

memory cells

1, 2, to n (i.e.,

memory cells

210, 220, to 2nO), respectively. As shown in fig. 3, the control circuit 130 may adjust the control signal CTRL2, e.g., based on the accumulated error pattern information AEPI2 corresponding to the second memory cell 220. The control circuit 130 may adjust the control signal CTRL2 such that the read voltage level L2 of the second memory cell 220 changes to the read voltage level L2'. As such, control circuit 130 may control second memory cell 220 based on the adjusted control signal CTRL 2' instead of CTRL 2. In the case where the adjusted control signal CTRL2 'is transferred or transmitted to second memory cell 220, second memory cell 220 may output stored data by using read voltage level L2'.

The control circuit 130 may manage the control signals CTRL1 through CTRLn corresponding to the memory cells 210 through 2nO based on the control signal management table 102. The control signal management table 102 may store a control signal corresponding to each of the memory cells 210 to 2 nO. The control circuit 130 may adjust the control signal based on the accumulated error pattern information AEPI, and may update the control signal stored in the control signal management table 102 based on the adjusted control signal. Thereafter, the control circuit 130 may control the memory cells 210 to 2nO based on the adjusted control signals stored in the control signal management table 102. For example, the control signal management table 102 may be stored in the RAM 160 or the ROM170 of fig. 2. For example, the control signal management table 102 shown in fig. 3 may store the control signal CTRL1, the adjusted control signals CTRL 2' to CTRLn for the

memory cells

1, 2 to n (i.e., the

memory cells

210, 220 to 2nO), respectively.

As shown in fig. 3, the control circuit 130 may adjust the control signal CTRL2 based on the accumulated error mode information AEPI2, and may update the control signal CTRL2 corresponding to the second memory cell 220 in the control signal management table 102 based on the adjusted control signal CTRL 2'. Thereafter, the control circuit 130 may control the second memory unit 220 based on the adjusted control signal CTRL 2' stored in the control signal management table 102.

In an embodiment, the control circuit 130 may adjust all or a portion of the control signals CTRL1 through CTRLn according to the accumulated error pattern information AEPI. Thus, the control circuit 130 may update all or a part of the control signals CTRL1 through CTRLn of the control signal management table 102.

Hereinafter, the operation of the memory controller according to an embodiment of the inventive concept will be more fully described with reference to fig. 4 to 11. Specifically, an operation of the memory controller 100 according to a decoding success will be described with reference to fig. 4 to 8, and an operation of the memory controller 100 according to a decoding failure will be described with reference to fig. 9 to 11.

FIG. 4 shows a block diagram of the memory controller of FIG. 3 operating according to decoding success. Referring to fig. 4, a memory controller 100 is shown to include an ECC circuit 110, a codeword circuit 120, a control circuit 130, an error pattern information table 101, and a control signal management table 102.

In case the decoding result indicates success, the ECC circuit 110 may provide the control circuit 130 with a decoding result "success", which includes the decoded codeword DCW (① of fig. 4).

Control circuit 130 may receive the decoding result "successful" from ECC circuit 110, including decoded codeword DCW, and may receive output codeword CW. from codeword circuit 120 control circuit 130 may detect erroneous bits by comparing output codeword CW with decoded codeword DCW (② of fig. 4).

The control circuit 130 may update the accumulated error pattern information AEPI (③ of fig. 4) in the error pattern information table 101 corresponding to the determined memory cell based on the detected error bit the operation of the control circuit 130 to detect the error bit and update the error pattern information table 101 will be described more fully with reference to fig. 5.

The control circuit 130 may adjust the control signal CTRL based on the updated accumulated error mode information AEPI in the error mode information table 101 (④ -1 of fig. 4), in an embodiment, the control circuit 130 may adjust the control signal CTRL of the memory cell corresponding to the updated accumulated error mode information AEPI, the control circuit 130 may update the control signal CTRL in the control signal management table 102 according to the adjusted control signal (⑤ -1 of fig. 4), the operation of the control circuit 130 to adjust the control signal CTRL based on the accumulated error mode information AEPI will be more fully described with reference to fig. 6 and 7A through 7C.

The control circuit 130 may refresh the memory cells (④ -2 of FIG. 4) by transmitting a control signal CTRL including a refresh command REF to the memory cells, the control circuit 130 may initialize the accumulated error mode information AEPI (⑤ -2 of FIG. 4) in the error mode information table 101 corresponding to the refreshed memory cells, the operation of the control circuit 130 to refresh the memory cells and initialize the accumulated error mode information AEPI will be more fully described with reference to FIG. 8.

FIG. 5 is a diagram illustrating an example of the memory controller of FIG. 4 updating an error pattern information table based on decoding success. Referring to fig. 5, the control circuit 130 may receive a decoding result "success" including the decoded codeword DCW therein from the ECC circuit 110 based on the decoding success, and may receive the output codeword CW from the codeword circuit 120. The control circuit 130 may detect erroneous bits by comparing the output codeword CW with the decoded codeword DCW. The control circuit 130 may compare the bits of the output codeword CW with the bits of the decoded codeword DCW, respectively, and may detect bits of the output codeword CW that are different in value from the bits of the decoded codeword DCW as error bits.

As shown in fig. 5, control circuit 130 may detect erroneous bits by comparing bits of each of segments SEG1 through SEGn of output codeword CW with bits of each of segments DSEG1 through DSEGn of decoded codeword DCW. Control circuit 130 may detect second bit "0" and third bit "0" of bits "0001" included in second segment SEG2 of output codeword CW as error bits (i.e., as error bits). Control circuitry 130 may determine that the detected error bit is included in segment SEG 2. In this way, control circuit 130 may determine that an error bit occurred at second memory cell 220 (see FIG. 3).

For example, control circuitry 130 may determine whether erroneous bits are included in any of the segments based on predetermined partitioning rules used at codeword circuitry 120. Alternatively, the control circuit 130 may divide the output codeword CW and the decoded codeword DCW based on a predetermined division rule, and the control circuit 130 may compare a specific segment of the output codeword CW with a specific segment of the decoded codeword DCW to determine error bits included in the specific segment. Here, the specific segment of the output codeword CW and the specific segment of the decoded codeword DCW may correspond to each other.

Control circuitry 130 may calculate the number of error bits and bit error pattern information for each memory cell based on the determined error bits. In case that the bits of the output codeword CW are decoded into different bit values, the bit error pattern information may be information on the number of errors corresponding to each of the bit error types. In an embodiment, the bit error types may include a first flipping error FE1 in which a bit value "0" is flipped to a different bit value "1" and a second flipping error FE2 in which a bit value "1" is flipped to a different bit value "0". That is, when the first toggle error FE1 is generated, an erroneous bit "0" in the output codeword CW can be detected. Further, when the second toggle error FE2 is generated, an erroneous bit "1" in the output codeword CW can be detected.

As shown in fig. 5, in case that the second bit value "0" of the second segment SEG2 is decoded to a different bit value "1" (i.e., the second toggle error FE2 occurs) and the third bit value "0" of the second segment SEG2 is decoded to a different bit value "1" (i.e., the second toggle error FE2 occurs), the control circuit 130 may calculate the number of error bits of the second memory cell 220 as "2". In addition, the control circuit 130 may calculate the number of second toggle errors FE2 as bit error pattern information. In the example of fig. 5, the number of second rollover errors FE2 may be "2".

The control circuit 130 may update the error pattern information table 101 based on the number of error bits thus calculated and the bit error pattern information thus calculated. As shown in fig. 5, the error pattern information table 101 may include an accumulated error bit count and bit error pattern information. That is, the accumulated error pattern information AEPI may include an accumulated error bit count and bit error pattern information.

As shown in fig. 5, before updating the error pattern information table 101, the accumulated error bit count corresponding to the second memory cell 220 may be "3", the number of first toggle errors FE1 may be "1", and the number of second toggle errors FE2 may be "2". Accordingly, the control circuit 130 may update the accumulated error bit count corresponding to the second memory cell 220 from "3" to "5" based on the calculated number of error bits. The control circuit 130 may also update the number of second rollover errors FE2 from "2" to "4" based on the calculation result.

The embodiment of fig. 5 shows the error pattern information table 101 as including the accumulated error bit count and the bit error pattern information as accumulated error pattern information AEPI. However, other embodiments of the inventive concept are not limited thereto, and the error pattern information table 101 may include various information associated with error bits, for example.

FIG. 6 shows a schematic diagram of an example of the memory controller of FIG. 4 adjusting the control signal according to decoding success. Referring to fig. 6, the control circuit 130 may receive the decoding result "successful" from the ECC circuit 110 and may update the error pattern information table 101 (e.g., as described with respect to fig. 5). As shown in fig. 6, control circuit 130 may update the accumulated error bit count corresponding to second memory cell 220 from "3" to "5" and may update the number of second rollover errors FE2 from "2" to "4".

Control circuitry 130 may determine whether the updated accumulated error bit count is not less than the first threshold and is less than the second threshold. In the event that the updated accumulated error bit count is not less than the first threshold and is less than the second threshold, control circuit 130 may adjust the control signal for the associated memory cell. For example, control circuit 130 may adjust the control signals to adjust the read voltage level of the associated memory cell. In this case, the first threshold may be a reference value for adjusting the read voltage level. The second threshold may be a reference value for performing any other operation (e.g., a refresh operation) while the control circuit 130 is not regulating the control signal.

As shown in fig. 6, in the case where the updated accumulated error bit count is "5", the first threshold value is "4", and the second threshold value is "9", the updated accumulated error bit count may not be less than the first threshold value and may be less than the second threshold value. In this case, control circuit 130 may adjust control signal CTRL2 to adjust the read voltage level of second memory cell 220. Thus, the control signal CTRL2 corresponding to the second memory cell 220 in the control signal management table 102 may be updated to the adjusted control signal CTRL 2'. In an embodiment, in a read operation associated with second memory cell 220, control circuitry 130 may read data from second memory cell 220 by using adjusted control signal CTRL 2'.

Control circuit 130 may determine the direction and magnitude to adjust the read voltage level based on the updated accumulated error bit count or the updated bit error pattern information. For example, the control circuit 130 may increase the magnitude of the read voltage level in a preset direction in proportion to the updated accumulated error bit count.

Hereinafter, an operation of the control circuit 130 to determine to adjust the direction and magnitude of the read voltage level based on the bit error pattern information will be more fully described with reference to fig. 7A to 7C.

Fig. 7A, 7B, and 7C are schematic diagrams illustrating an example in which a control circuit determines a read voltage level according to an embodiment of the inventive concept. Specifically, fig. 7A shows an example in which the control circuit 130 performs a read operation by using the first voltage V1. Fig. 7B shows an example in which the control circuit 130 performs a read operation by using the second voltage V2. Fig. 7C shows an example in which the control circuit 130 performs a read operation by using the third voltage V3. Referring to fig. 7A to 7C, threshold voltage distributions of memory cells included in the memory cell are shown. In fig. 7A to 7C, the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells. In fig. 7A to 7C, a memory cell of the state "0" included in the first region a1 may be determined as a memory cell of the state "1". The memory cell of the state "1" included in the second area a2 may be determined as the memory cell of the state "0". That is, the first region a1 may be a region where the first rollover error FE1 occurs, and the second region a2 may be a region where the second rollover error FE2 occurs.

Referring to fig. 7A, in the case of performing a read operation based on the first voltage V1, since the size of the first region a1 is the same as the size of the second region a2, the number of first toggle errors FE1 may be the same as the number of second toggle errors FE 2. In this case, the control circuit 130 may maintain the read voltage level. Accordingly, the control circuit 130 may maintain the control signal corresponding to the memory cell.

Referring to fig. 7B, in the case of performing a read operation based on the second voltage V2, since the size of the first region a1 is smaller than the size of the second region a2, the number of first toggle errors FE1 to be occurred in the first region a1 may be smaller than the number of second toggle errors FE2 to be occurred in the second region a 2. In this case, the control circuit 130 may increase the read voltage level. That is, in the case where the number of the first flipping errors FE1 is less than the number of the second flipping errors FE2, the control circuit 130 may determine that the direction of adjusting the read voltage level is a forward direction. The control circuit 130 may determine the magnitude of the adjusted read voltage level based on the difference between the number of first toggle errors FE1 and the number of second toggle errors FE 2. Accordingly, the control circuit 130 may adjust the control signal such that the read voltage level is increased according to the determined adjustment magnitude.

Referring to fig. 7C, in the case of performing a read operation based on the third voltage V3, since the size of the first region a1 is greater than the size of the second region a2, the number of first toggle errors FE1 to be occurred in the first region a1 may be greater than the number of second toggle errors FE2 to be occurred in the second region a 2. In this case, the control circuit 130 may lower the read voltage level. That is, in the case where the number of the first flipping errors FE1 is greater than the number of the second flipping errors FE2, the control circuit 130 may determine that the direction of adjusting the read voltage level is negative. The control circuit 130 may determine the magnitude of the adjusted read voltage level based on the difference between the number of first toggle errors FE1 and the number of second toggle errors FE 2. Accordingly, the control circuit 130 may adjust the control signal such that the read voltage level is reduced according to the determined adjustment magnitude.

In the embodiments of fig. 7A to 7C, a Single Level Cell (SLC) storing one bit in a memory cell is illustrated. However, other embodiments of the inventive concept are not limited thereto. For example, the inventive concept may be applied to a multi-level cell (MLC) that stores a plurality of bits in a memory cell. In this case, the control circuit 130 may adjust the control signal to adjust the plurality of read voltage levels.

As described above, the control circuit 130 may determine the read voltage level based on the bit error pattern information as described with reference to fig. 7A to 7C, and may adjust the control signal according to the determined read voltage level. However, the inventive concept is not limited thereto, and for example, the control circuit 130 may obtain the read voltage level from the bit error pattern information through machine learning, and may adjust the control signal according to the obtained read voltage level.

FIG. 8 is a diagram illustrating an example of the memory controller of FIG. 4 refreshing data of memory cells according to decoding success. Referring to fig. 8, the control circuit 130 may receive the decoding result "success" from the ECC circuit 110, and may update the error pattern information table 101. As shown in fig. 8, the control circuit 130 may update the accumulated error bit count corresponding to the second memory cell 220 from "3" to "10".

Control circuitry 130 may determine whether the updated accumulated error bit count is not less than the second threshold. In the case where the updated accumulated error bit count is not less than the second threshold value, the control circuit 130 may refresh the data stored in the relevant memory cell. As shown in fig. 8, in the event that the updated accumulated error bit count (e.g., 10) is not less than the second threshold (e.g., 9), control circuitry 130 may provide control signal CTRL2, including refresh command REF, to second memory cell 220. The second memory cell 220 may perform a refresh operation in response to the refresh command REF. In this way, all data stored in the second memory unit 220 can be rewritten.

In the case of overwriting the data of the second memory cell 220, the existing accumulated error pattern information AEPI associated with the second memory cell 220 may not be associated with the second memory cell 220. Accordingly, the control circuit 130 may initialize the accumulated error pattern information AEPI corresponding to the second memory unit 220 in the error pattern information table 101. As shown in fig. 8, the control circuit 130 may initialize the accumulated error bit count corresponding to the second memory cell 220 to "0".

As described above, in the case where the decoding result indicates success, the memory controller 100 may adjust the control signal corresponding to the memory cell based on the accumulated error pattern information AEPI. The memory controller 100 may adjust the control signal based on the decoding result of the memory cell, thereby adjusting the read voltage level of the memory cell. Therefore, the number of erroneous bits of data output from the memory cell may be reduced, and the probability of occurrence of decoding failure may be reduced. That is, the Raw Bit Error Rate (RBER) of the memory system 1000 may be reduced.

In addition, in the case where the accumulated error bit count is not less than the preset value, the memory controller 100 may refresh data of the relevant memory cell. Thus, the reliability of data stored in the memory cells after refresh is improved.

FIG. 9 illustrates a block diagram of the operation of the memory controller of FIG. 3 according to a decoding failure. Referring to fig. 9, the memory controller 120 is shown to include an ECC circuit 110, a codeword circuit 120, a control circuit 130, an error pattern information table 101, and a control signal management table 102.

In the event that the decoding result associated with the output codeword CW indicates a failure (i.e., a decoding failure), the control circuit 130 may receive the decoding result "failure" from the ECC circuit 110 (① of fig. 9), the control circuit 130 may adjust the control signal CTRL (③ of fig. 9) based on the accumulated error mode information AEPI (② of fig. 9) in the error mode information table 101, in an embodiment, the control circuit 130 may adjust the control signal CTRL of the memory cell corresponding to the accumulated error mode information AEPI satisfying a preset condition, the control circuit 130 may update the control signal management table 102(④ of fig. 9) according to the adjusted control signal, the operation of the control circuit 130 based on the decoding failure adjustment control signal CTRL will be more fully described with reference to fig. 10.

Control circuit 130 may re-read segment SEG stored in memory cells based on adjusted control signal CTRL ⑤ of fig. 9 hi an embodiment, control circuit 130 may re-read only segments SEG stored in memory cells corresponding to the adjusted control signal among segments SEG1 through SEGn stored in memory cells 210 through 2n0, that is, may re-read only segments stored in some of memory cells 210 through 2n0, the operation of control circuit 130 re-reading segments SEG stored in memory cells based on the adjusted control signal will be described more fully with reference to fig. 10.

Codeword circuit 120 may generate a new output codeword NCW based on the re-read segment SEG (⑥ of fig. 9.) in an embodiment, where only segments stored in some memory cells are re-read, codeword circuit 120 may generate a new output codeword NCW based on the re-read segments and previously read segments-ECC circuit 110 may perform decoding on the new output codeword NCW (⑦ of fig. 9) — the operations of codeword circuit 120 to generate the new output codeword NCW and ECC circuit 110 to perform decoding on the new output codeword NCW will be described more fully with reference to fig. 11.

FIG. 10 is a diagram illustrating an example of the memory controller of FIG. 9 re-reading a segment according to a decoding failure. Referring to fig. 10, the control circuit 130 may receive a decoding result "fail" from the ECC circuit 110 based on the decoding failure. In response to the decoding result "fail," the control circuit 130 may determine whether the accumulated error bit count corresponding to each of the memory cells 210 to 2nO is less than a first threshold. In the case where the accumulated error bit count is not less than the first threshold (as described with reference to fig. 6), the control signal of the associated memory cell may be a pre-adjusted control signal. In this way, control circuit 130 may adjust the control signal for the associated memory cell in the event that the accumulated error bit count is less than the first threshold. For example, the first threshold may be the same as the first threshold of fig. 6. The control circuit 130 may update the control signal management table 102 according to the adjusted control signal.

As shown in fig. 10, in the error pattern information table 101, the accumulated error bit count corresponding to the first memory cell 210 may be "3", the accumulated error bit count corresponding to the second memory cell 220 may be "6", and the accumulated error bit count corresponding to the n-th memory cell 2nO may be "5" (see the

memory cells

210, 220, and 2nO in fig. 3). Control circuit 130 may determine whether the accumulated error bit count corresponding to each of memory cells 210 through 2nO is less than a first threshold. In the case where the accumulated error bit count corresponding to the first memory cell 210 is "3" and the first threshold value is "4", the accumulated error bit count corresponding to the first memory cell 210 is less than the first threshold value. In this case, control circuit 130 may adjust control signal CTRL1 of first memory cell 210. As shown in FIG. 10, control circuit 130 may adjust control signal CTRL1 such that first memory cell 210 performs a read operation based on the adjusted read voltage level L1'. The control circuit 130 may update the control signal management table 102 according to the adjusted control signal CTRL 1'.

In an embodiment, control circuitry 130 may determine read voltage level L1' corresponding to first memory cell 210 based on the accumulated error bit count or bit error pattern information. As shown in fig. 10, with respect to the first memory cell 210, the number of first toggle errors FE1 may be "3", and the number of second toggle errors FE2 may be "0". The control circuit 130 may determine the read voltage level L1' based on the number of first toggle errors FE1 and the number of second toggle errors FE2 associated with the first memory cell 210. As shown in fig. 7A to 7C, since the number of the first flipping errors FE1 is greater than the number of the second flipping errors FE2, the control circuit 130 may determine the read voltage level L1 ', or in other words, adjust the read voltage level L1 ' in one direction such that the magnitude of the read voltage level L1 ' is reduced. The control circuit 130 may determine the decrement based on a difference between the number of first rollover errors FE1 and the number of second rollover errors FE 2.

Control circuit 130 may re-read the segment from the memory cell based on the adjusted control signal. In an embodiment, control circuit 130 may re-read only the segment associated with the memory cell corresponding to the adjusted control signal among segments SEG1 through SEGn stored in memory cells 210 through 2n 0. As shown in fig. 10, control circuit 130 may re-read first segment SEG1 from first memory cell 210 based on adjusted control signal CTRL 1'. In response to the adjusted control signal CTRL1 ', the first memory cell 210 may output the first segment SEG1 by using the read voltage of the read voltage level L1'.

Fig. 11 is a diagram illustrating an example in which the memory controller of fig. 9 performs decoding again according to a decoding failure. Referring to fig. 11, codeword circuit 120 may generate a new output codeword NCW based on first segment SEG1 read again from first memory cell 210. Codeword circuit 120 may generate a new output codeword NCW based on the re-read first segment SEG1 and the previously read second segment SEG2 through nth segment SEGn.

ECC circuit 110 may perform decoding on the new output codeword NCW and may output the decoding result. In case the decoding result indicates success, the control circuit 130 may operate as described with reference to fig. 4 to 8. In an embodiment, control circuit 130 may detect erroneous bits by comparing decoded codeword DCW with new output codeword NCW. The control circuit 130 may update the accumulated error pattern information AEPI in the error pattern information table 101 based on the detected error bit. The control circuit 130 may adjust the control signal based on the accumulated error pattern information AEPI, and may update the control signal management table 102 based on the adjusted control signal. Alternatively, control circuit 130 may refresh segments SEG1 through SEGn stored in memory cells 210 through 2n0 based on decoded codeword DCW. That is, the control circuit 130 may rewrite the segments SEG1 through SEGn according to the decoded codeword DCW in which the error bits are corrected.

In the event that the decoding result indicates a failure, the control circuit 130 may determine that the read operation has failed.

As described above, in the case where the decoding result indicates a failure, the control circuit 130 may adjust the control signal and may re-read the segment based on the adjusted control signal. In this case, the number of erroneous bits of the re-read segment may be reduced. Therefore, the probability of successful decoding of the new output codeword NCW generated based on the re-read segment increases. Further, the control circuit 130 may not re-read all the segments SEG1 through SEGn stored in the memory cells 210 through 2nO, but the control circuit 130 may re-read only the segments stored in the memory cells corresponding to the adjusted control signals. Therefore, an increase in read delay can be minimized, and power consumption can be reduced.

Fig. 12 illustrates a flowchart of an operation of a memory controller according to an embodiment of the inventive concept. Referring to fig. 3 and 12, the memory controller 100 receives (i.e., reads) a plurality of segments SEG1 through SEGn from a plurality of memory cells 210 through 2nO based on a plurality of control signals CTRL1 through CTRLn in operation S101. In operation S102, the memory controller 100 generates an output codeword CW based on the plurality of segments SEG1 through SEGn. In operation S103, the memory controller 100 performs error correction decoding on the output codeword CW and generates a decoding result.

In operation S104, the memory controller 100 adjusts the plurality of control signals CTRL1 through CTRLn based on the accumulated error pattern information AEPI corresponding to each of the plurality of memory cells 210 through 2nO according to the decoding result. In an embodiment, the memory controller 100 may adjust at least one of the plurality of control signals CTRL1 through CTRLn based on at least one of the plurality of accumulated error pattern information AEPI corresponding to the plurality of memory cells 210 through 2 nO.

Fig. 13 illustrates a flowchart of an operation corresponding to a case where the memory controller is decoded successfully, according to an embodiment of the inventive concept. Referring to fig. 4 and 13, the memory controller 100 detects an error bit by comparing the output codeword CW with the decoded codeword DCW in operation S111. In operation S112, the memory controller 100 updates the accumulated error pattern information AEPI in the error pattern information table 101 based on the detected error bit.

In operation S113, the memory controller 100 determines whether the updated accumulated error bit count of the updated accumulated error pattern information AEPI is not less than a first threshold. In the case where the updated accumulated error bit count is not less than the first threshold value (yes in S113), the memory controller 100 determines whether the updated accumulated error bit count is not less than the second threshold value in operation S114. In the case where the updated accumulated error bit count is less than the second threshold value (no in S114), the memory controller 100 adjusts the control signals associated with the memory cells corresponding to the updated accumulated error pattern information AEPI in operation S115.

In the case where the updated accumulated error bit count is not less than the second threshold value (yes in S114), the memory controller 100 refreshes data stored in the memory cell corresponding to the updated accumulated error pattern information AEPI in operation S116. That is, all data stored in the corresponding memory cell can be rewritten. In operation S117, the memory controller 100 initializes the accumulated error pattern information AEPI corresponding to the refreshed memory cells. For example, an accumulated error bit count corresponding to a refreshed memory cell may be initialized. In the case where the updated accumulated error bit count is smaller than the first threshold value (no in S113), the operation ends.

Fig. 14 illustrates a flowchart of an operation corresponding to a case where a memory controller fails to decode according to an embodiment of the inventive concept. Referring to fig. 9 and 14, in operation S121, the memory controller 100 determines whether an accumulated error bit count in the accumulated error pattern information AEPI corresponding to each of the memory cells 210 to 2nO is less than a first threshold. In the case where the accumulated error bit count of the corresponding memory cell is less than the first threshold value (yes in S121), the memory controller 100 adjusts a control signal associated with the memory cell corresponding to the accumulated error pattern information AEPI in operation S122. In operation S123, the memory controller 100 re-reads the segment from the relevant (i.e., corresponding) memory cell based on the adjusted control signal. In operation S124, the memory controller 100 generates a new output codeword NCW based on the re-read segment. In operation S125, the memory controller 100 performs error correction decoding on the new output codeword NCW. In the case where the accumulated error bit count corresponding to each memory cell is not less than the first threshold value (no in S121), the operation ends.

Fig. 15 illustrates a block diagram of an application of a memory system according to an embodiment of the inventive concept. Referring to fig. 15, the computer system 2000 includes a host 2100, a user interface 2200, a storage module 2300, a network module 2400, a memory module 2500, and a system bus 2600.

The host 2100 may drive components and an operating system included in the computer system 2000. In an embodiment, the host 2100 may include, for example, a controller, interface, graphics engine, etc. to control the components of the computer system 2000. For example, host 2100 may be implemented using a system on a chip (SoC).

The user interface 2200 may include an interface for inputting data or instructions to the host 2100 or outputting data to an external device. In an embodiment, the user interface 2200 may comprise a user input interface, such as a keyboard, keypad, button, touchpad, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, piezoelectric sensor, and the like. The user interface 2200 may also include interfaces such as: liquid Crystal Displays (LCDs), Organic Light Emitting Diode (OLED) display devices, active matrix OLED (amoled) display devices, Light Emitting Diodes (LEDs), speakers, and motors.

The storage module 2300 may store data. For example, the storage module 2300 may store data received from the host 2100. Alternatively, the storage module 2300 may transfer the data stored therein to the host 2100. In an embodiment, memory module 2300 may be implemented with a non-volatile memory system such as Electrically Programmable Read Only Memory (EPROM), electrically Erasable Programmable Read Only Memory (EPROM), NAND flash memory, NOR flash memory, phase change ram (pram), resistive ram (reram), ferroelectric ram (feram), magnetic ram (mram), or thyristor ram (tram), among others. The memory module 2300 may include the memory system according to an embodiment of the inventive concept described with reference to fig. 1 to 14.

The network module 2400 may communicate with an external device. In an embodiment, the network module 2400 may support wireless communication such as Code Division Multiple Access (CDMA), global system for mobile communications (GSM), wideband CDMA (wcdma), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE)^TM) Worldwide interoperability for microwave access (Wimax), wireless lan (wlan), Ultra Wideband (UWB), bluetooth and wireless display (WI-DI).

The memory module 2500 may operate as a main memory, a working memory, a buffer memory, or a cache memory of the computer system 2000. Memory module 2500 may include a volatile memory system (e.g., DRAM or SRAM), or a non-volatile memory system (e.g., NAND flash, NOR flash, PRAM, RoRAM, FeRAM, MRAM, or TRAM). The memory module 2500 may include the memory system according to an embodiment of the inventive concept described with reference to fig. 1 to 14.

The system bus 2600 may electrically connect the host 2100, the user interface 2200, the memory module 2300, the network module 2400, and the memory module 2500 to each other.

According to the inventive concept, a memory controller and a memory system that can prevent failure of error correction performed on data can be provided.

Further, a memory controller and a memory system can be provided which can increase the probability of success of error correction and can minimize power consumption in the case where error correction is performed again after error correction fails.

Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A method of operating a memory controller that individually controls a plurality of memory cells, the method comprising:

reading, by the memory controller, respective segments from the plurality of memory cells based on a plurality of control signals;

generating, by the memory controller, an output codeword based on the segment;

performing, by the memory controller, error correction decoding on the output codeword;

updating, by the memory controller, at least one of a plurality of accumulated error pattern information respectively corresponding to the plurality of memory cells based on a result of the error correction decoding when the result of the error correction decoding indicates success; and

adjusting, by the memory controller, at least one of the plurality of control signals based on at least one of the plurality of accumulated error pattern information when the result of the error correction decoding indicates a failure.

2. The method of claim 1, wherein updating at least one of the plurality of accumulated error pattern information comprises:

comparing the output codeword with a decoded codeword produced from the error correction decoding to detect an erroneous bit corresponding to a first memory cell of the plurality of memory cells; and

updating first accumulated error pattern information corresponding to the first memory cell among the plurality of accumulated error pattern information based on the detected error bit.

3. The method of claim 2, further comprising: adjusting, by the memory controller, a control signal corresponding to the first memory cell among the plurality of control signals when an updated first accumulated error bit count of the updated first accumulated error pattern information is not less than a first threshold value and is less than a second threshold value.

4. The method of claim 3, further comprising:

refreshing, by the memory controller, data stored in the first memory cell when the updated first accumulated error bit count is not less than the second threshold; and

initializing the updated first accumulated error pattern information.

5. The method of claim 3, wherein a second control signal of the plurality of control signals corresponding to a second memory cell of the plurality of memory cells is adjusted by the memory controller when the result of the error correction decoding indicates a failure and a second accumulated error bit count of a second accumulated error pattern information of the plurality of accumulated error pattern information corresponding to the second memory cell is less than the first threshold.

6. The method of claim 5, further comprising:

re-reading, by the memory controller, one of the segments from the second memory unit based on an adjusted second control signal corresponding to the second memory unit;

generating a new output codeword based on the re-read segments; and

performing the error correction decoding on the new output codeword.

7. The method of claim 1, wherein each of the plurality of memory cells comprises at least one of: memory devices, memory chips, memory dies, memory banks, memory blocks, and memory cells connected to one word line.

8. The method of claim 1, further comprising:

performing, by the memory controller, error correction encoding on data supplied from a host to generate an input codeword to which an error correction code is added;

dividing, by the memory controller, the input codeword to produce the segment; and

storing, by the memory controller, the segment in the plurality of memory cells based on the plurality of control signals.

9. A memory controller, comprising:

a codeword circuit configured to generate an output codeword based on a first segment read from a first memory cell according to a first control signal and a second segment read from a second memory cell according to a second control signal;

an Error Correction Code (ECC) circuit configured to perform error correction decoding on the output codeword; and

a control circuit configured to operate according to a result of the error correction decoding,

wherein the control circuit is configured to adjust at least one of the first control signal and the second control signal based on at least one of first accumulated error pattern information corresponding to the first memory cell and second accumulated error pattern information corresponding to the second memory cell.

10. The memory controller of claim 9, wherein, when the result of the error correction decoding indicates success,

the ECC circuit is configured to generate a decoded codeword, an

The control circuit is further configured to:

comparing said output codeword with said decoded codeword, an

Updating the first accumulated error pattern information based on at least one erroneous bit when the at least one erroneous bit is detected from bits corresponding to the first segment based on a result of the comparison.

11. The memory controller of claim 10, wherein the control circuitry is configured to adjust the first control signal when the updated first accumulated error bit count of the updated first accumulated error pattern information is not less than a first threshold and is less than a second threshold.

12. The memory controller of claim 11, wherein when the updated first accumulated error bit count is not less than the second threshold, the control circuitry is configured to refresh data stored in the first memory cell and initialize the updated first accumulated error pattern information.

13. The memory controller of claim 11, wherein the control circuitry is configured to adjust the first control signal when the result of the error correction decoding indicates a failure and a first accumulated error bit count of the first accumulated error pattern information is less than the first threshold.

14. The memory controller of claim 13, wherein, when the result of the error correction decoding indicates a failure,

the control circuit is further configured to re-read the first segment from the first memory cell based on the adjusted first control signal,

the codeword circuit is further configured to generate a new output codeword based on the re-read first segment and the second segment, an

The ECC circuit is further configured to perform the error correction decoding on the new output codeword.

15. The memory controller of claim 9, wherein the control circuitry is configured to:

adjusting at least one of a first read voltage level of the first memory cell and a second read voltage level of the second memory cell based on at least one of the first accumulated error pattern information and the second accumulated error pattern information; and

adjusting at least one of the first control signal and the second control signal based on the adjusted at least one of the first read voltage level and the second read voltage level.

16. The memory controller of claim 15, wherein the first accumulated error pattern information includes first bit error pattern information indicating a pattern information of a first bit error in which a first bit value read from the first memory cell is decoded to a bit value different from the first bit value,

wherein the second accumulated error pattern information includes second bit error pattern information indicating a pattern information of a second bit error in which a second bit value read from the second memory cell is decoded to a bit value different from the second bit value, and

wherein the control circuit is configured to adjust at least one of the first read voltage level and the second read voltage level based on at least one of the first bit error pattern information and the second bit error pattern information.

17. A memory system, comprising:

a first memory cell configured to operate in response to a first control signal;

a second memory cell configured to operate in response to a second control signal; and

a memory controller configured to read a first segment from the first memory cell based on the first control signal and read a second segment from the second memory cell based on the second control signal,

wherein the memory controller comprises:

a codeword circuit configured to generate an output codeword based on the first segment and the second segment,

an Error Correction Code (ECC) circuit configured to perform error correction decoding on the output codeword, an

18. The memory system according to claim 17, wherein when the result of the error correction decoding indicates success,

the ECC circuit is configured to generate a decoded codeword, an

The control circuit is further configured to:

comparing said output codeword with said decoded codeword, an

19. The memory system of claim 18, wherein the control circuitry is configured to adjust the first control signal when the updated first accumulated error bit count of the updated first accumulated error pattern information is not less than a first threshold and is less than a second threshold.

20. The memory system of claim 19, wherein the control circuitry is configured to adjust the first control signal when the result of the error correction decoding indicates a failure and a first accumulated error bit count of the first accumulated error pattern information is less than the first threshold.