CN110825662A - Data updating method, system and related device - Google Patents
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Abstract
The application provides a data updating method, which comprises the following steps: determining a physical block where all valid data corresponding to the target logical block are located; updating the valid data in the physical block to the SLC mode cache block; after receiving a data writing instruction every time, judging whether an SLC mode cache block is in an updating mode; if yes, updating the valid data with the length corresponding to the data writing instruction into the TLC & QLC mode physical block corresponding to the logic block, and recording the data position of the data which is not updated in the SLC mode cache block during each updating until all valid data are updated to the TLC & QLC mode physical block. According to the method, the effective data are updated to the TLC & QLC mode physical block in batches, so that the overtime problem of most equipment can be effectively solved, and the method has high economic and social benefits. The application also provides a data updating system, a computer readable storage medium and a storage device, which have the beneficial effects.
Description
Technical Field
The present application relates to the field of storage devices, and in particular, to a data updating method, system and related apparatus.
Background
With the rapid development of storage technology and the popularization and application of large data, large-capacity NandFlash is more and more popular, and particularly, TLC and QLC NandFlash are most widely applied. Generally, large-capacity U disks, EMMC and SSD use TLC & QLC NandFlash as storage media, so that higher requirements are made on the compatibility of storage devices of the Flash.
At present, data updating algorithms for TLC & QLC NandFlash are performed by updating valid data corresponding to a logical block to a physical block of a TLC & QLC mode corresponding to the logical block at one time, and because the programming time of the TLC & QLC mode is too long, the method may have a situation of no response to a system for a long time in the process of data updating, thereby causing system response timeout, having a great influence on compatibility of a usb disk, an EMMC, and an SSD, and possibly causing the valid data to be unusable in a severe case.
In summary, the existing TLC & QLC NandFlash data updating algorithm has obvious disadvantages in practical application, and needs to be improved.
Disclosure of Invention
An object of the present application is to provide a data updating method, system, a computer-readable storage medium, and a storage device, which can reduce the influence of storage device updating.
In order to solve the technical problems, the application provides a data updating method which is applied to a TLC & QLC NandFlash physical block, and the specific technical scheme is as follows:
determining a physical block where all valid data corresponding to the target logical block are located;
updating the valid data in the physical block to an SLC mode cache block corresponding to the logical block according to the logical address sequence;
after receiving a data writing instruction every time, judging whether the SLC mode cache block is in an updating mode;
if yes, updating the valid data with the length corresponding to the data writing instruction to the TLC & QLC mode physical block corresponding to the logic block, and recording the data position of the data which is not updated in the SLC mode cache block; until all the valid data are updated to the TLC & QLC mode physical block.
Wherein determining whether the SLC mode cache block is in an update mode comprises:
and judging whether the valid data exists in the SLC mode cache block or not.
Wherein, before updating the valid data in the physical block to the SLC mode cache block corresponding to the logical block according to the logical address sequence, the method further includes:
and setting an initial updating address and the number of pages to be updated each time.
Wherein, after all the valid data are updated to the TLC & QLC mode physical block, the method further comprises:
setting the SLC mode cache block to a non-update state to cause the SLC mode cache block to stop updating data.
The application also provides a data updating system, which is applied to TLC & QLC NandFlash physical blocks and comprises the following steps:
the data determining module is used for determining the physical block where all valid data corresponding to the target logic block are located;
the data integration module is used for updating the valid data in the physical block to an SLC mode cache block corresponding to the logical block according to the logical address sequence;
the judging module is used for judging whether the SLC mode cache block is in an updating mode after receiving a data writing instruction every time;
a data updating module, configured to update valid data with a length corresponding to the data writing instruction to a TLC & QLC mode physical block corresponding to the logical block and record a data position of non-updated data in the SLC mode cache block if the determination result of the determining module is yes; until all the valid data are updated to the TLC & QLC mode physical block.
Wherein, the judging module comprises:
and the judging unit is used for judging whether the valid data exists in the SLC mode cache block or not.
Wherein, still include:
and the setting module is used for setting an initial updating address and the number of pages to be updated each time.
Wherein, still include:
a setting module, configured to set the SLC mode cache block to a non-update state after all the valid data is updated to the TLC & QLC mode physical block, so that the SLC mode cache block stops updating data.
The present application also provides a computer-readable storage medium having stored thereon a computer program which, when being executed by a processor, carries out the steps of the method as set forth above.
The present application also provides a storage device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method described above when calling the computer program in the memory.
The application provides a data updating method, which is applied to a TLC & QLC NandFlash physical block and comprises the following steps: determining a physical block where all valid data corresponding to the target logical block are located; updating the valid data in the physical block to an SLC mode cache block corresponding to the logical block according to the logical address sequence; after receiving a data writing instruction every time, judging whether the SLC mode cache block is in an updating mode; if yes, updating the valid data with the length corresponding to the data writing instruction to the TLC & QLC mode physical block corresponding to the logic block, and recording the data position of the data which is not updated in the SLC mode cache block; until all the valid data are updated to the TLC & QLC mode physical block.
According to the method and the device, the effective data are updated to the TLC & QLC mode physical block in batches, the time for updating the TLC & QLC mode physical block once is divided into a plurality of times of system command processing, the problem that the system has no response for a long time caused by one-time updating is avoided, the problem of timeout on most devices can be effectively solved, and the method and the device have high economic and social benefits. The present application further provides a data updating system, a computer-readable storage medium, and a storage device, which have the above beneficial effects and are not described herein again.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a data updating method provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of a data updating system according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a flowchart of a data updating method according to an embodiment of the present application, where the data updating method includes:
s101: determining a physical block where all valid data corresponding to the target logical block are located;
s102: updating the valid data in the physical block to an SLC mode cache block corresponding to the logical block according to the logical address sequence;
s103: after receiving a data writing instruction every time, judging whether the SLC mode cache block is in an updating mode;
s104: if yes, updating the valid data with the length corresponding to the data writing instruction to the TLC & QLC mode physical block corresponding to the logic block, and recording the data position of the data which is not updated in the SLC mode cache block; until all the valid data are updated to the TLC & QLC mode physical block.
First, all valid data corresponding to the logical block are determined. Usually, the valid data is distributed in several physical blocks, then step S101 needs to determine all physical blocks containing valid data. And after the physical blocks are determined, updating the valid data in each physical block to the SLC mode cache block corresponding to the logical block according to the logical address sequence. SLC mode refers to Single-level cell, Single-level cell flash, which is a type of NAND flash. Each logic block corresponds to three or four SLC mode cache blocks (general TLC NandFlash corresponds to 3, QLC NandFlash corresponds to 4), and this step requires that all valid data be updated to the SLC mode cache blocks. The logical address order used is not limited, and is usually the order of logical addresses of data in the NAND.
Since the current data updating algorithm for TLC & QLC NandFlash is performed by updating valid data corresponding to a logical block to a physical block of a TLC & QLC mode corresponding to the logical block at one time, since the programming time of the TLC & QLC mode is too long, there is a situation that the system does not respond to the system for a long time in the process of data updating in the manner, which results in system response timeout. For this reason, the present application performs data updating divided into several times.
The data write command refers to a data write command, which marks each update of valid data. Once receiving the data writing command, firstly, judging whether the SLC mode cache block is in an updating mode. The update mode means that the SLC mode cache block needs to perform an update, i.e. it is determined whether valid data still exists in the SLC mode cache block. If there is valid data, it indicates that the SLC mode cache block is still in the update mode. Of course, valid data that has been updated to the TLC & QLC mode physical block will be removed from the SLC mode cache block.
Specifically, before step S102, an initial update address and the number of pages to be updated each time may also be set. The initial update address is used for counting, and is typically set to 0. Each time the page number is updated, the number of pages of valid data which needs to be updated from the SLC mode cache block to the TLC & QLC mode physical block after each data write instruction is received, may also be understood as the data length.
It should be noted that the core of the present application is to update valid data to the TLC & QLC mode physical block in batches, and the data length of the valid data updated in each update process is not limited, and it should be valid data of the corresponding length of the data write instruction. In other words, the effective data length of each update depends on the data write command, i.e. the data length of each update may be the same or different, and the specific data length is not limited herein. However, it should be noted that, each time the data is updated, the effective data length of the current update may be obtained from the parameter in the data writing instruction, or may be a preset length corresponding to the data writing instruction. The updated effective data length can be written into the data writing instruction every time, the length corresponding to the data writing instruction can also be set as a preset value, and when the data writing instruction is received, the preset value is directly called to obtain the effective data length required to be updated at this time. If the step S103 is executed to set the number of pages to be updated each time or other parameters capable of playing the same role, the preset value may directly correspond to the number of pages to be updated each time according to the data writing instruction. Whether the preset value is the preset value or the number of pages to be updated each time, the data size of the valid data to be updated is usually set by a person skilled in the art accordingly. It is easy to understand that the data volume of the valid data updated each time is not too large, and the influence on the system operation needs to be ensured to be minimum, so as to avoid the long-time no response of the system caused by the large data volume of the update.
Further, whether valid data is updated in the logical address order is not limited. Whether the data is updated according to a certain data or not, the address of the currently updated effective data can be recorded in each updating process, and the recorded address is avoided for updating in the subsequent updating process. Or recording the position of the data which is not updated in the SLC mode cache block during each updating, and updating according to the recorded position in the subsequent updating process.
In addition, the valid data is updated to the SLC mode cache block from each physical block, and then is updated to the TLC & QLC mode physical block from the SLC mode cache block, namely, the valid data is updated by using the cache, so that the updating speed of the valid data to the TLC & QLC mode physical block is greatly improved.
And during each update, the data position of the un-updated data in the SLC mode cache block can be recorded, so that after a data writing instruction is received next time, the valid data needing to be updated next time can be directly determined according to the data position of the un-updated data.
There is no limitation on how to determine whether all valid data is updated to the TLC & QLC mode physical block. Preferably, the initial update address M is set to 0, the number of pages updated each time, that is, the data length is n, and the number of pages updated each time is M + n until the final M equals to the total number of pages M of valid data in each physical block, that is, it is determined that all valid data have been updated to the TLC & QLC mode physical block. At this time, valid data does not already exist in the SLC mode cache block, and it may be set to a non-update state.
According to the embodiment of the application, the effective data is updated to the TLC & QLC mode physical block in batches, and the time for updating the TLC & QLC mode physical block once is divided into a plurality of times of system command processing, so that the problem of no response of a system for a long time caused by one-time updating is avoided, the problem of timeout on most devices can be effectively solved, and the economic benefit and the social benefit are high.
On the basis of the above embodiment, after all valid data is updated to the TLC & QLC mode physical block, the SLC mode cache block may also be set to a non-update state, so that the SLC mode cache block stops updating data.
When the SLC mode cache block is in a non-updating state, all valid data in the SLC mode cache block are updated to TLC & QLC mode physical blocks at the moment, and the end of data updating of NAND Flash is marked.
Then, the specific implementation process corresponding to this embodiment is as follows:
s201: determining a physical block where all valid data corresponding to the target logical block are located;
s202: updating effective data in the physical block to an SLC mode cache block corresponding to the logical block according to the logical address sequence;
s203: after receiving a data writing instruction every time, judging whether an SLC mode cache block is in an updating mode;
s204: if yes, updating the effective data with the length corresponding to the data writing instruction to the TLC & QLC mode physical block corresponding to the logic block, and recording the data position of the un-updated data in the SLC mode cache block; until all valid data is updated to the TLC & QLC mode physical block.
S205: when all valid data is updated to the TLC & QLC mode physical block, the SLC mode cache block is set to a non-updated state.
In the following, a data updating system provided by an embodiment of the present application is introduced, and the data updating system described below and the data updating method described above may be referred to correspondingly.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a data updating system provided in an embodiment of the present application, and the present application further provides a data updating system applied to a TLC & QLC NandFlash physical block, including:
a data determining module 100, configured to determine a physical block where all valid data corresponding to the target logical block are located;
a data integration module 200, configured to update valid data in the physical block to an SLC mode cache block corresponding to the logical block according to a logical address sequence;
a determining module 300, configured to determine whether the SLC mode cache block is in an update mode after receiving a data write instruction each time;
a data updating module 400, configured to update valid data with a length corresponding to the data writing instruction to a TLC & QLC mode physical block corresponding to the logical block and record a data position of the un-updated data in the SLC mode cache block if the determination result of the determining module 300 is yes; until all the valid data are updated to the TLC & QLC mode physical block.
Based on the above embodiment, as a preferred embodiment, the determining module 300 includes:
and the judging unit is used for judging whether the valid data exists in the SLC mode cache block or not.
Based on the above embodiment, as a preferred embodiment, the data update system may further include:
and the setting module is used for setting an initial updating address and the number of pages to be updated each time.
Based on the above embodiment, as a preferred embodiment, the data updating system may further include:
a setting module, configured to set the SLC mode cache block to a non-update state after all the valid data is updated to the TLC & QLC mode physical block, so that the SLC mode cache block stops updating data.
The present application also provides a computer readable storage medium having stored thereon a computer program which, when executed, may implement the steps provided by the above-described embodiments. The storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The present application further provides a storage device, which may include a memory and a processor, where the memory stores a computer program, and the processor may implement the steps provided in the foregoing embodiments when calling the computer program in the memory. Of course, the storage device may also include various network interfaces, power supplies, and the like.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system provided by the embodiment, the description is relatively simple because the system corresponds to the method provided by the embodiment, and the relevant points can be referred to the method part for description.
The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A data updating method is characterized by being applied to a TLC & QLC NandFlash physical block and comprising the following steps:
determining a physical block where all valid data corresponding to the target logical block are located;
updating the valid data in the physical block to an SLC mode cache block corresponding to the logical block according to the logical address sequence;
after receiving a data writing instruction every time, judging whether the SLC mode cache block is in an updating mode;
if yes, updating the valid data with the length corresponding to the data writing instruction to the TLC & QLC mode physical block corresponding to the logic block, and recording the data position of the data which is not updated in the SLC mode cache block; until all the valid data are updated to the TLC & QLC mode physical block.
2. The data update method of claim 1, wherein determining whether the SLC mode cache block is in update mode comprises:
and judging whether the valid data exists in the SLC mode cache block or not.
3. The data updating method of claim 1, wherein before the valid data in the physical block is updated to the SLC mode cache block corresponding to the logical block according to the logical address order, the method further comprises:
and setting an initial updating address and the number of pages to be updated each time.
4. The data updating method of claim 1, wherein after all the valid data are updated to the TLC & QLC mode physical block, further comprising:
setting the SLC mode cache block to a non-update state to cause the SLC mode cache block to stop updating data.
5. A data updating system is characterized by being applied to a TLC & QLC NandFlash physical block and comprising:
the data determining module is used for determining the physical block where all valid data corresponding to the target logic block are located;
the data integration module is used for updating the valid data in the physical block to an SLC mode cache block corresponding to the logical block according to the logical address sequence;
the judging module is used for judging whether the SLC mode cache block is in an updating mode after receiving a data writing instruction every time;
a data updating module, configured to update valid data with a length corresponding to the data writing instruction to a TLC & QLC mode physical block corresponding to the logical block and record a data position of non-updated data in the SLC mode cache block if the determination result of the determining module is yes; until all the valid data are updated to the TLC & QLC mode physical block.
6. The data update system of claim 5, wherein the determining module comprises:
and the judging unit is used for judging whether the valid data exists in the SLC mode cache block or not.
7. The data update system of claim 5, further comprising:
and the setting module is used for setting an initial updating address and the number of pages to be updated each time.
8. The data update system of claim 5, further comprising:
a setting module, configured to set the SLC mode cache block to a non-update state after all the valid data is updated to the TLC & QLC mode physical block, so that the SLC mode cache block stops updating data.
9. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the data updating method according to any one of claims 1 to 4.
10. A storage device comprising a memory in which a computer program is stored and a processor which, when called upon by the computer program in the memory, carries out the steps of the data update method according to any one of claims 1 to 4.
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Application publication date: 20200221 |