CN1108039C - System structure for receiving split phase code and making optimum detection and its method - Google Patents
System structure for receiving split phase code and making optimum detection and its method Download PDFInfo
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- CN1108039C CN1108039C CN 99111133 CN99111133A CN1108039C CN 1108039 C CN1108039 C CN 1108039C CN 99111133 CN99111133 CN 99111133 CN 99111133 A CN99111133 A CN 99111133A CN 1108039 C CN1108039 C CN 1108039C
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Abstract
The present invention relates to a system structure for receiving the optimum detection by split phase codes and a method. In the system structure, a computer is arranged, an integrating circuit is connected with the computer, and the computer is connected with baseband signals through a resistor. The method includes the following steps that an integrating result is subtracted from a medial level to determine the sampling polarity and the deviation size; the polarity of a calculation result for the sampling of a previous time is compared with the polarity of a calculation result for the sampling of a current time to determine whether phase lead or phase lag is realized for the sampling; the calculation result for the sampling is accumulated into a filtering result buffer so as to carry out addition for the lag and subtraction for the lead; a filtering result is compared with a filtering regulation value N; when the filtering result is greater then N, a timing time constant is regulated, and the sampling phase is moved forwards; when the filtering result is smaller than-N, the timing time constant is regulated, and the sampling phase is moved backwards; the current code 0/1 is determined and stored; a filtering result unit is cleared.
Description
The invention provides a kind of system configuration and method that receives optimal detection, be meant a kind of system results and method of utilizing diphase code to receive optimal detection especially.
In digital communication system, transmitting terminal transmits out by certain bit rate with digital signal one by one, and receiving terminal also must be by identical speed to the code element judgement of sampling one by one, otherwise can't correctly recover original digital signal.In order to reduce the influence of noise and intersymbol interference, reach the purpose that reduces the error rate, must select the best time that symbol sample is adjudicated.Just require sampling instant and the transmission sequence of symhols of being received to have identical speed and correct time relation.General method be receiving terminal by hardware circuit produce one with the transmitting terminal sequence of symhols with homophase frequently synchronously or the commutator pulse sequence, i.e. bit synchronization signal is for sampling and the needs of other aspect.
The objective of the invention is to, provide a kind of diphase code to receive the system configuration of optimal detection, it has advantage of simple structure.
Another object of the present invention is to, the method that provides a kind of diphase code to receive optimal detection, it is to utilize software approach to select optimum sampling constantly, so there is not the bit synchronization item of a pulse train form in practice.
A kind of diphase code of the present invention receives the system configuration of optimal detection, it is characterized in that, comprising a computer, linking to each other with this computer is connected to an integrating circuit, and this integrating circuit connects baseband signal by a resistance respectively; The two ends that this integrating circuit is connected with computer are respectively removes end and integration end.
A kind of diphase code of the present invention receives the method for optimal detection, it is characterized in that it is to utilize the computer intelligence arbitration functions, and the result is kept in the input buffer by the analog to digital converter input integral; Integral result and middle bit level are subtracted each other definite sampling polarity and deviation size; More last time determined with the polarity of current sampling result of calculation that sampling phase still lagged behind in advance; The result of calculation of will sampling is added to filtering result cache device, and the hysteresis addition is subtracted each other in advance; Filtering result and filtering adjusted value N relatively, when＞N adjusts the reach of timing constant sampling phase, when＜-N moves after adjusting timing constant sampling phase; Judge current sign indicating number 0 or 1 and preservation; Remove filtering unit as a result.
Below in conjunction with drawings and Examples structure of the present invention, method and the effect that can reach are done a detailed description, wherein:
Fig. 1 is an orthogonal integration principle of phase lock loop block diagram in the prior art;
Fig. 2 is the optimum receiving system structure chart of optimizable computer digit base band;
Fig. 3 is the optimum receiving system structure chart of diphase code computer digit base band of the present invention;
Fig. 4 is noise-free signal oscillogram when synchronous for adopting;
Fig. 5 is sampling phase noise-free signal oscillogram when leading;
Noise-free signal oscillogram when Fig. 6 lags behind for sampling phase;
Fig. 7 receives the flow chart of optimum detection methodology for diphase code.
See also shown in Figure 3ly, be the optimum receiving system structure chart of diphase code computer digit base band of the present invention.Wherein in the optimum receiving system of diphase code computer digit base band, comprise: a computer, linking to each other with this computer is connected to an integrating circuit, and this integrating circuit connects baseband signal by a resistance; The two ends that this integrating circuit is connected with computer are respectively removes end and integration end.
Please in conjunction with consulting Fig. 7, diphase code receives the method for optimal detection, and it is to utilize the computer intelligence arbitration functions, and the result is kept in the input buffer by the analog to digital converter input integral; Integral result and middle bit level are subtracted each other definite sampling polarity and deviation size; More last time determined with the polarity of current sampling result of calculation that sampling phase still lagged behind in advance; The result of calculation of will sampling is added to filtering result cache device, and the hysteresis addition is subtracted each other in advance; Filtering result and filtering adjusted value N relatively, when＞N adjusts the reach of timing constant sampling phase, when＜-N moves after adjusting timing constant sampling phase; Judge current sign indicating number 0 or 1 and preservation; Remove filtering unit as a result.
In the signals transmission, may suffer various distortion and sneak into random noise, also just exist uncertainty or randomness at receiving terminal.But do not mean that signal can't reliable reception.From the viewpoint of probability theory, any enchancement factor is always followed certain statistical law, so only GPRS receives the statistics of waveform, just can obtain the reception of being satisfied with the method for statistical decision.For example: a signal is by comparator and differential circuit, and what obtain only is signal on the point, and when noise was more intense, it just can not represent transmission signals reliably.If this signal is by an integrator, then the integration of noise is at random, and overall average be " 0 " (referring to here has+,-output is to the integration at zero point, attention integration of noise on a code-element period may not be " 0 ").And the integration of signal is deferred to the rule of transmitting terminal symbol signal, gets the integrator output valve in the moment of determining, to bit decision, defers to the judgement of statistical law exactly.Fig. 1 follows the tracks of the principle of phase lock loop block diagram by the typical orthogonal integration that hardware circuit constitutes.Voltage controlled oscillator output T1 (t) is the bit synchronization signal of tracking.Principle and use can be consulted " phase-locked loop principle and application) " Chen Shiwei work.Do not do further discussion herein.
Part after the orthogonal integration phase-locked loop integrator is moved into computer just formed computer optimal detection system (as Fig. 2).Be subjected to the influence of A/D converter conversion speed in low-cost system, the computer sampling speed ratio is lower.Will bigger deviation be arranged with analog integration if do the sampling integration with computer.Therefore with integral part by hardware handles, other parts are finished with computer software.
Computer by the homophase of analog switch control active integrator remove, in remove mutually.Its clearance rate, sampling rate are identical with bit rate.Sample homophase removing immediately after the sampling finish time in each code element with phase integral.Middle phase integral is in the code element intermediate samples, and sampling is removed in the back mutually.In the loop judgement, conversion is adjudicated, is postponed, multiplies each other and loop filtering is all finished by computer.At this moment loop filter is not that voltage of output is controlled voltage controlled oscillator, but adjusts sampling and remove constantly according to the calculated value of loop filter.Homophase with middle mutually sampling and removing be move forward simultaneously or after move, in system, in fact do not have voltage controlled oscillator.The polarity that can notice homophase integration sampling value is exactly the code element content through optimum decision.Because this group sampled value and bit rate be the frequency homophase together, and all exists in the computer, so there is no need the carry-out bit synchronizing signal as standard for manual sampling again.Homophase with middle mutually sampling and the phase shifts Minimum Increment value of removing on 80186 computers, can reach 0.5 μ s, compare quantization error with synchronizing cycle and can ignore, therefore in the phase place adjustment, can have than higher precision.
Diphase code has a saltus step " ↑ " expression " 0 " in the centre of code element, " ↓ " expression " 1 ".Can find that its duty ratio is symmetrical in each code element.Each code element homophase integral voltage equals 0, and the middle phase integral result in the middle of two code elements is positive maximum or negative maximum.According to this feature, phase integral circuit in can cancelling in the design is only used the homophase integrating circuit, once sampling of (sampling instant of phase integral in former) increase on the code element centre position.Homophase (it is initial that code element finishes next code element) sampled value removes to adjust sampling phase through loop filter, can reach the purpose of following the tracks of phase place.
When phase place was accurate, the in-phase sampling value was always 0, and this moment, the loop filter calculated value was 0, did not do phase place adjustment (Fig. 4).
When sampling phase is leading (Fig. 5), if the phase sampler value is for just in this moment code element, then the in-phase sampling value is also for just.When middle phase sampler value was negative, the in-phase sampling value was for negative.Just in-phase sampling depends on current middle phase sampler value polarity.
As can be seen from Figure 6, when sampling phase lagged behind, in-phase sampling can fall into next code element integrated area, and its polarity depends on phase integral polarity in the next code element.
| A k-1 a k | In advance | Lag behind |
| 0 0 0 1 1 0 1 1 | - - + + | - + - + |
Table 1 conversion decision rule
If with a
K-1With a
kRepresent adjacent two code element contents respectively, can from table 1, find out the leading polarity of exporting with phase integral with hysteresis.Work as a
K-1With a
kWhen polarity was identical, the conversion judgement was output as 0.Work as a
K-1≠ a
kThe time, if sampled value and a
K-1The identical expression of polarity is leading, and this moment, sampled value took absolute value, and obtained a series of positive homophase integrated values.If sampled value and a
kThe identical expression of polarity lags behind, and adds negative sign after sampled value takes absolute value, and can draw the negative homophase integrated value of row.Identical with in-phase sampling value phase place for the ease of understanding the phase place of changing the judgement pulse in the lead and lag oscillogram, the conversion judgement is to obtain a in practice
kAdjudicate after the polarity, lag behind the in-phase sampling value.After having obtained a series of conversion decision values, can remove to control sampling phase by a filter.
Whole base band receives decoded portion can see second-order PLL as, by the close-loop feedback control principle, selects damping coefficient ξ and loop natural frequency ω
n, under [S] territory, calculate filter parameter.At this moment loop bandwidth should be much smaller than bit rate.
In the experiment of system, also adopt another kind of filtering method, also obtained effect preferably.Be the digital filter principle that the reference number ring is adopted, the numerical value after the conversion judgement asked its algebraical sum, when itself and absolute value during greater than a certain numerical value, sampling phase does+or-adjustment.Different is that the addition here is quantitative addition, rather than the qualitative addition that digital rings adopted with digital rings.Thereby, can improve adjusting function greatly.
From the above as can be seen: as long as code element has conversion, the conversion judgement just has numerical value.If sampling phase is accurate, this numerical value is 0 when noiseless, if noise is arranged, sampled value is the statistical value of noise in one-period.Each periodic noise value is at random, but can remove noise effect by loop filter, reaches optimal detection.
This technology in, can replace the optimum detector that conventional phase locked loops is formed in the low rate system fully.
Claims (2)
1, a kind of diphase code receives the system configuration of optimal detection, it is characterized in that, comprising:
One computer, linking to each other with this computer is connected to an integrating circuit, and this integrating circuit connects baseband signal by a resistance; End and integration end are removed in being respectively that this integrating circuit is connected with computer.
2, a kind of diphase code receives the method for optimal detection, it is characterized in that,
It is to utilize the computer intelligence arbitration functions, and the result is kept in the input buffer by the analog to digital converter input integral;
Integral result and middle bit level are subtracted each other definite sampling polarity and deviation size;
More last time determined with the polarity of current sampling result of calculation that sampling phase still lagged behind in advance;
The result of calculation of will sampling is added to filtering result cache device, and the hysteresis addition is subtracted each other in advance;
Filtering result and filtering adjusted value N relatively, when＞N adjusts the reach of timing constant sampling phase, when＜-N moves after adjusting timing constant sampling phase;
Judge current sign indicating number 0 or 1 and preservation;
Remove filtering unit as a result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN 99111133 CN1108039C (en) | 1999-07-27 | 1999-07-27 | System structure for receiving split phase code and making optimum detection and its method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99111133 CN1108039C (en) | 1999-07-27 | 1999-07-27 | System structure for receiving split phase code and making optimum detection and its method |
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| Publication Number | Publication Date |
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| CN1282159A CN1282159A (en) | 2001-01-31 |
| CN1108039C true CN1108039C (en) | 2003-05-07 |
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| CN 99111133 Expired - Fee Related CN1108039C (en) | 1999-07-27 | 1999-07-27 | System structure for receiving split phase code and making optimum detection and its method |
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| CN116539956A (en) * | 2022-01-26 | 2023-08-04 | 深圳市紫光同创电子有限公司 | Phase detection method and device |
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