CN110798361B - Short-wave direct-sampling system configuration method - Google Patents
Short-wave direct-sampling system configuration method Download PDFInfo
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- CN110798361B CN110798361B CN201911120328.6A CN201911120328A CN110798361B CN 110798361 B CN110798361 B CN 110798361B CN 201911120328 A CN201911120328 A CN 201911120328A CN 110798361 B CN110798361 B CN 110798361B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0803—Configuration setting
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/02—Protocols based on web technology, e.g. hypertext transfer protocol [HTTP]
- H04L67/025—Protocols based on web technology, e.g. hypertext transfer protocol [HTTP] for remote control or remote monitoring of applications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/2866—Architectures; Arrangements
- H04L67/30—Profiles
- H04L67/303—Terminal profiles
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses a short wave direct acquisition system configuration method, which comprises the following configuration steps: configuration of the operating environment; configuration of radio frequency control; configuration of digital AGC control; configuration of local network and FPGA program loading; configuration of heartbeat packets; configuration of the AD overload function. The invention configures the short wave direct acquisition system, controls the short wave direct acquisition equipment, controls the front-end board card, transmits various parameters, issues data, returns and other functions, and realizes the function of multi-channel short wave direct acquisition.
Description
Technical Field
The invention belongs to the technical field of electronic communication, and particularly relates to a short wave direct acquisition system configuration method.
Background
Short-wave communication carries out signal transmission in a short-wave mode, belongs to one of radio communication technologies, and is applied to the communication field more and more at present. In the prior art, a short-wave direct-acquisition receiving system is needed to control a short-wave direct-acquisition device to realize multi-channel acquisition of short-wave signals, perform correction and high-linearity amplification on the signals, then perform sampling and DDC processing on the signals to obtain subband signals, and a configuration method of the short-wave direct-acquisition system is needed.
Disclosure of Invention
The invention provides a short wave direct acquisition system configuration method, which is used for configuring a short wave direct acquisition system, controlling short wave direct acquisition equipment, controlling a front-end board card, transmitting various parameters, issuing data, returning data and the like, and realizing a multichannel short wave direct acquisition function.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
a short wave direct sampling system configuration method mainly comprises the following steps: the system comprises a 20-channel short-wave direct acquisition receiver and a back-end application processing server; the 20-channel short-wave direct acquisition receiver comprises 5 acquisition boards, wherein the acquisition boards are short-wave signal acquisition processing cards, and the 5 acquisition boards respectively receive 5 sub-frequency bands of the short-wave frequency band; the 20-channel short wave direct acquisition receiver also comprises a transmission board main board and a slave board, wherein the transmission board is a ten-gigabit network transmission and control card and is used for connecting a rear-end application processing server; the 20-channel short-wave direct acquisition receiver is connected with a time system device to receive time signals; the core of the acquisition board and the transmission board is FPGA;
the configuration step comprises:
s1, configuring an operating environment;
s2, configuring radio frequency control;
s3, configuring digital AGC control;
s4, local network and FPGA program loading configuration;
s5, configuring a heartbeat packet;
and S6, configuring an AD overload function.
Further, the configuring of the digital AGC control in step S3 includes: and setting AGC parameters, starting AGC gain, and setting AGC gain query.
Further, the configuration loaded by the local network and the FPGA program in step S4 includes FPGA program loading configuration, local network configuration, and FPGA version number query function configuration.
Furthermore, the FPGA program loading configuration includes a loaded program path and a loading selection of a transmission board or an acquisition board.
Further, the method for local network configuration includes:
a) A source end IP and a destination end IP of the current equipment are determined by capturing a temperature packet and a trillion network state packet which are uploaded to a PC by the equipment through wireshark;
b) Adding high level IP of a local PC end, and adding a local gigabit network IP to be changed;
c) Opening a test program configuration file, changing a local IP in the gigabit network setting into the destination IP obtained in the step a), and changing a device IP into the source IP obtained in the step a);
d) Opening a test program, and displaying temperature information;
e) Opening the local gigabit network IP and FPGA program settings in the test program, and changing the device gigabit network IP;
f) The method comprises the steps that temperature packets uploaded to a PC through a wireshark grabbing device are used for observing whether a source end IP is changed;
g) Closing the test program, opening a configuration file Config-NetConfig.xml of the test program, changing the local IP in the gigabit network setting into the local IP added in the step b), and changing the equipment IP into the IP set in the step e);
h) Opening the local gigabit network IP and FPGA program settings in the test program, and changing the local IP into the IP in the step b);
i) And restarting the test program, displaying temperature information, and observing whether the IP of the temperature packet grabbed by the wireshark is corrected or not.
Furthermore, the format of the FPGA version number query function configuration is as follows: v _ device model _ vendor _ module type _ version number.
Further, the configuration of the heartbeat packet in step S5 includes:
1) The starting state:
1 represents normal power-on when the computer is started, and 0 represents abnormal power-on of the board card;
2) The system clock state:
1 represents that an external clock is accessed, and 0 represents that no external clock is accessed;
3) A digital receiver temperature;
4) The state of the FPGA chip:
1 represents that the acquisition board V7 is normally started, and 0 represents that the acquisition board V7 is abnormal;
5) The state of the transmission plate is as follows:
1 represents that the transmission plate is normal, and 0 represents that the transmission plate is abnormal;
6) Radio frequency channel module state:
acquiring the state of a plate which reads back to radio frequency every minute, wherein 1 represents that the in-place state of a radio frequency channel module is normal, and 0 represents that the in-place state of the radio frequency channel module is abnormal;
7) Correcting the source switching state:
1 represents that the data source is in an antenna state, and 0 represents that the data source is in a calibration source state;
8) A correction source module:
1 represents that the correction source power supply is turned on and the correction switch is turned on, and 0 represents that the correction source power supply is turned off or the correction switch is turned off;
9) Temperature of the radio frequency case: the temperature state of the plate read back to radio frequency per minute is collected.
Further, the configuring of the AD overload function in step S6 includes: and configuring a display area, and respectively displaying the AD overload states of the 5 boards.
Compared with the prior art, the invention has the following beneficial effects:
the short-wave direct acquisition system is configured, short-wave direct acquisition equipment is controlled, a front-end board card is controlled, various parameters are transmitted, data are issued and returned, and the like, so that the multi-channel short-wave direct acquisition function is realized.
Drawings
Fig. 1 is a schematic diagram of a system hardware structure according to an embodiment of the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
1. Description of the system:
the hardware structure of the system to be configured in the invention is shown in fig. 1, and the antennas in the antenna array are divided into 5 frequency bands, and each frequency band is 20 channels. The 20 signals of each frequency band firstly pass through 5 independent 20-channel short-wave direct-sampling receivers (analog parts), and the parts carry out high-linearity amplification processing on the signals. The short wave direct acquisition receiver (analog part) part also provides a correction signal output and a frequency source output. 20 paths of signals with the same frequency band after amplification processing enter an acquisition processing module with the same short wave direct acquisition receiver (digital part), are acquired at a sampling rate of 102.4Mfps, are subjected to DDC processing to be subband signals with a bandwidth of 500kHz, and are output to an exchanger through a ten-gigabit network port, and the exchanger outputs the subband signals to an application server for processing.
5 short wave signal acquisition processing cards of the 20-channel short wave digital direct acquisition receiver system respectively receive 5 sub-frequency bands of 1.5 MHz-30 MHz of short wave frequency band:
frequency band one: 1.5 MHz-5.5 MHz, and 4MHz bandwidth;
frequency band two: 5.5 MHz-9.5 MHz, 4MHz bandwidth;
frequency band three: 9.5 MHz-14.5 MHz, 5MHz bandwidth;
and a frequency band IV: 10.5 MHz-20.5 MHz, and 10MHz bandwidth;
and a fifth frequency band: 20.5 MHz-30.5 MHz, and 10MHz bandwidth;
meanwhile, the receiver system also controls five sets of 20-channel receiving and correcting equipment to receive the short wave signals output by the sharer and complete the radio frequency synchronous direct acquisition of the 20-channel signals of the corresponding sub-frequency band, thereby completing the seamless coverage of the whole short wave frequency band.
20 direct acquisition channels of the 20-channel short-wave digital direct acquisition receiver perform narrow-band digital down-conversion (DDC) of at most 20 500kHz per channel on short-wave radio frequency signal data directly acquired by corresponding sub-frequency bands, so that time code labeling of narrow-band IQ data is completed, and the final IQ narrow-band data is connected with a rear-end application processing server through 8 ten-gigabit network interfaces of 2 gigabit network transmission control cards for distribution. The network connection number and the corresponding connection parameters can be set by the back-end application processing server.
The 20-channel short-wave digital direct acquisition receiver can also control the corresponding 20-channel receiving correction equipment to complete the channel correction of the receiver.
The core of the acquisition board card and the transmission board card of the short wave direct acquisition receiver (digital part) is FPGA, and communication is carried out through udp network transmission. The system software mainly realizes data transmission and communication with the FPGA on the board card through udp network transmission, thereby realizing the functions of controlling the front-end board card, transmitting various parameters, issuing and returning data and the like required by projects.
The system software mainly designs a DLL program and an application layer program under a windows platform, and realizes various functions of instruction control, data return and the like according to project requirements.
The control command of the upper computer to the system is carried out through a gigabit network, and the method specifically comprises the following steps:
control command of short wave direct sampling receiver (digital part):
1. changing equipment kilomega network IP address through an upper computer;
2. the FPGA program can be loaded remotely;
3. carrying out self-checking query on the equipment;
4. sending configurable source end, destination end IP and port to the ten-gigabit network data;
5. the performance control can be carried out on the data sent by the ten-gigabit network;
6. the device temperature status may be returned.
(II) control command of short wave direct sampling receiver (radio frequency part):
1. controlling gain modes MGC and AGC;
2. controlling the attenuation value of the radio frequency preprocessing module;
3. controlling the working mode, the low noise mode and the conventional mode of the radio frequency preprocessing module;
4. controlling the working frequency band of the radio frequency preprocessing module;
5. controlling a power switch of the radio frequency preprocessing module;
6. controlling the attenuation value of the radio frequency correction source module;
7. controlling the working mode of the radio frequency correction source module, and outputting and closing the correction source;
8. controlling the working frequency band of the radio frequency correction source module;
9. controlling a power switch of the radio frequency correction source module;
10. controlling the working mode, the antenna state and the correction state of the radio frequency direction finding switch module;
11. controlling a power switch of the radio frequency direction-finding switch module;
12. performing state query and identity query on the preprocessing module;
13. performing state query and identity query on the correction source module;
14. and carrying out state query and identity query on the direction-finding switch module.
(III) New function
1. Digital AGC related functions:
(1) controlling radio frequency AGC parameters;
setting an upper limit and a lower limit of the radio frequency AGC, setting a discharge constant and setting a discharge step;
(2) controlling digital AGC parameters;
setting an upper limit, a lower limit, a discharge constant and a discharge step of the digital AGC;
(3) a digital gain mode configuration;
agc, mgc state switching function;
(4) digital MGC attenuation value control;
controlling the number of the sub-band (0-19) + the attenuation value (0-59);
2. some of the query functions:
(1) a starting-up state inquiry function;
(2) a system clock state query function;
(3) a radio frequency communication state query function;
(4) acquiring a board aurora state query function;
querying the version number of the FPGA;
4, inquiring an AGC gain value;
5. heartbeat packet function.
2. Based on the above system software and hardware architecture and functions, the configuration method of the present invention includes:
s1, configuring an operating environment;
s2, configuring radio frequency control;
s3, configuring digital AGC control; the method comprises the following steps: setting AGC parameters, starting AGC gain, and setting AGC gain query;
s4, configuration of local network and FPGA program loading; the method comprises the steps of FPGA program loading configuration, local network configuration and FPGA version number query function configuration;
the FPGA program loading configuration comprises a loaded program path and loading selection of a transmission board or a collection board.
The method for local network configuration comprises the following steps:
a) A source end IP and a destination end IP of the current equipment are determined by capturing a temperature packet and a trillion network state packet which are uploaded to a PC by the equipment through wireshark;
b) Adding high level IP of a local PC end, and adding a local gigabit network IP to be changed;
c) Opening a test program configuration file, changing a local IP in the gigabit network setting into the destination IP obtained in the step a), and changing a device IP into the source IP obtained in the step a);
d) Opening a test program, and displaying temperature information;
e) Opening the local gigabit network IP and FPGA program settings in the test program, and changing the gigabit network IP of the equipment;
f) The method comprises the steps that temperature packets uploaded to a PC through a wireshark grabbing device are used for observing whether a source end IP is changed;
g) Closing the test program, opening a configuration file Config-NetConfig.xml of the test program, changing the local IP in the gigabit network setting into the local IP added in the step b), and changing the equipment IP into the IP set in the step e);
h) Opening the local gigabit network IP and FPGA program settings in the test program, and changing the local IP into the IP in the step b);
i) And restarting the test program, displaying temperature information, and observing whether the IP of the temperature packet grabbed by the wireshark is corrected or not.
The format of the FPGA version number query function configuration is as follows: v _ device model _ vendor _ module type _ version number.
S5, configuration of heartbeat packets;
the method comprises the following steps:
1) The starting state:
1 represents normal power-on when the computer is started, and 0 represents abnormal power-on of the board card;
2) The system clock state:
1 represents that an external clock is accessed, and 0 represents that no external clock is accessed;
3) A digital receiver temperature;
4) The state of the FPGA chip:
1 represents that the acquisition board V7 is normally started, and 0 represents that the acquisition board V7 is abnormal;
5) The state of the transmission plate:
1 represents that the transmission plate is in a normal state, and 0 represents that the transmission plate is in an abnormal state;
6) Radio frequency channel module state:
acquiring the state of a plate which reads back to radio frequency every minute, wherein 1 represents that the in-place state of a radio frequency channel module is normal, and 0 represents that the in-place state of the radio frequency channel module is abnormal;
7) Correcting the source switching state:
1 represents that the data source is in an antenna state, and 0 represents that the data source is in a calibration source state;
8) A correction source module:
1 represents that the correction source power supply is turned on and the correction switch is turned on, and 0 represents that the correction source power supply is turned off or the correction switch is turned off;
9) Temperature of the radio frequency case: the temperature state of the plate read back to radio frequency per minute is collected.
S6, configuring an AD overload function; and configuring a display area, and respectively displaying the AD overload states of the 5 boards.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (3)
1. A short wave direct sampling system configuration method is characterized in that the system mainly comprises: the system comprises a 20-channel short-wave direct acquisition receiver and a back-end application processing server; the 20-channel short-wave direct acquisition receiver comprises 5 acquisition boards, wherein the acquisition boards are short-wave signal acquisition processing cards, and the 5 acquisition boards respectively receive 5 sub-frequency bands of the short-wave frequency band; the 20-channel short wave direct acquisition receiver also comprises a transmission board main board and a slave board, wherein the transmission board is a ten-gigabit network transmission and control card and is used for connecting a rear-end application processing server; the 20-channel short-wave direct acquisition receiver is connected with time system equipment to receive time signals; the core of the acquisition board and the transmission board is FPGA;
the configuration step comprises:
s1, configuring an operating environment;
s2, configuring radio frequency control;
s3, configuring digital AGC control;
s4, configuration of local network and FPGA program loading;
s5, configuring a heartbeat packet;
s6, configuring an AD overload function;
the system also comprises system software for realizing data transmission and communication with the FPGA on the board card through udp network transmission, and the specific configuration comprises the following steps:
control commands of a digital part of the short-wave direct acquisition receiver are as follows:
1.1, changing equipment kilomega network IP address through an upper computer;
1.2 remotely loading an FPGA program;
1.3, carrying out self-checking query on the equipment;
1.4 sending configurable source end, destination end IP and port to the ten-gigabit network data;
1.5, carrying out enabling control on the data sent by the trillion network;
1.6 returning to the temperature state of the equipment;
(II) control commands of the radio frequency part of the short wave direct acquisition receiver:
2.1 controlling gain modes MGC and AGC;
2.2 controlling the attenuation value of the radio frequency preprocessing module;
2.3 controlling the working mode, low noise mode and normal mode of the radio frequency preprocessing module;
2.4, controlling the working frequency range of the radio frequency pretreatment module;
2.5 controlling the power switch of the radio frequency preprocessing module;
2.6 controlling the attenuation value of the radio frequency correction source module;
2.7 controlling the working mode of the radio frequency correction source module, and outputting and closing the correction source;
2.8 controlling the working frequency range of the radio frequency correction source module;
2.9 controlling the power switch of the radio frequency correction source module;
2.10 controlling the working mode, the antenna state and the correction state of the radio frequency direction-finding switch module;
2.11 controlling the power switch of the radio frequency direction-finding switch module;
2.12, performing status query and identity query on the preprocessing module;
2.13, performing status query and identity query on the correction source module;
2.14, carrying out state query and identity query on the direction-finding switch module;
step S3, the configuration of the digital AGC control includes: setting AGC parameters, starting AGC gains, and setting AGC gain inquiry;
s4, the local network and the FPGA program loading configuration comprises an FPGA program loading configuration, a local network configuration and an FPGA version number inquiry function configuration;
the FPGA program loading configuration comprises a loaded program path and loading selection of a transmission plate or a collection plate;
the method for local network configuration comprises the following steps:
a) A temperature packet and a gigabit network state packet which are uploaded to a PC (personal computer) by the equipment are grabbed by a wireshark, and a source end IP and a destination end IP of the current equipment are determined;
b) Adding high level to IP of local PC end, and adding local kilomega network IP to be changed;
c) Opening a test program configuration file, changing a local IP in the gigabit network setting into the destination IP obtained in the step a), and changing a device IP into the source IP obtained in the step a);
d) Opening a test program, and displaying temperature information;
e) Opening the local gigabit network IP and FPGA program settings in the test program, and changing the device gigabit network IP;
f) The method comprises the steps that temperature packets uploaded to a PC through a wireshark grabbing device are used for observing whether a source end IP is changed;
g) Closing the test program, opening a configuration file Config-NetConfig.xml of the test program, changing a local IP in gigabit network setting into the local IP added in the step b), and changing a device IP into the IP set in the step e);
h) Opening the local gigabit network IP and FPGA program settings in the test program, and changing the local IP into the IP in the step b);
i) Restarting the test program, displaying temperature information, and observing whether the IP of the temperature packet grabbed by the wireshark is corrected or not;
step S5, the configuration of the heartbeat packet includes:
1) The starting state:
1 represents normal power-on when the computer is started, and 0 represents abnormal power-on of the board card;
2) The system clock state:
1 represents that an external clock is accessed, and 0 represents that no external clock is accessed;
3) A digital receiver temperature;
4) The state of the FPGA chip:
1 represents that the acquisition board V7 is normally started, and 0 represents that the acquisition board V7 is abnormal;
5) The state of the transmission plate:
1 represents that the transmission plate is normal, and 0 represents that the transmission plate is abnormal;
6) Radio frequency channel module state:
acquiring the state of a plate which reads back to radio frequency every minute, wherein 1 represents that the in-place state of a radio frequency channel module is normal, and 0 represents that the in-place state of the radio frequency channel module is abnormal;
7) Correcting the source switching state:
1 represents that the data source is in an antenna state, and 0 represents that the data source is in a calibration source state;
8) A correction source module:
1 represents that the correction source power supply is turned on and the correction switch is turned on, and 0 represents that the correction source power supply is turned off or the correction switch is turned off;
9) Temperature of the radio frequency case: and acquiring the temperature state of the plate read back to radio frequency every minute.
2. The short wave direct sampling system configuration method according to claim 1, wherein the format of the FPGA version number query function configuration is: v _ device model _ vendor _ module type _ version number.
3. The short wave direct acquisition system configuration method according to claim 1, wherein the step S6 of configuring the AD overload function includes: and configuring a display area, and respectively displaying the AD overload states of the 5 boards.
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