CN110797363A - Backside illuminated time delay integral image sensor and forming method thereof - Google Patents

Backside illuminated time delay integral image sensor and forming method thereof Download PDF

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Publication number
CN110797363A
CN110797363A CN201911071212.8A CN201911071212A CN110797363A CN 110797363 A CN110797363 A CN 110797363A CN 201911071212 A CN201911071212 A CN 201911071212A CN 110797363 A CN110797363 A CN 110797363A
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image sensor
layer
time delay
substrate
backside
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胡万景
王林
黄金德
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Brigates Microelectronic Co Ltd
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Brigates Microelectronic Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements

Abstract

A backside illuminated time delay integral image sensor and a forming method thereof, wherein the backside illuminated time delay integral image sensor comprises: the substrate comprises a first face and a second face which are opposite, the substrate comprises a plurality of photoelectric doping regions, and the surfaces of the photoelectric doping regions are exposed out of the first face; a circuit device layer on the first side; and the anti-reflection and anti-reflection layer is positioned on the second surface and covers a plurality of the photoelectric doped regions. The back-illuminated time delay integral image sensor has high performance.

Description

Backside illuminated time delay integral image sensor and forming method thereof
Technical Field
The invention relates to the field of semiconductors, in particular to a back-illuminated time delay integral image sensor and a forming method thereof.
Background
Time Delay Integration (TDI) image sensors are an evolution of linear image sensors. The imaging mechanism of the time delay integral image sensor is to expose the pixels passing through the object line by line and accumulate the exposure results, thereby solving the problem of weak imaging signals caused by insufficient exposure time of a high-speed moving object. The time delay integral image sensor can increase effective exposure time and improve the signal-to-noise ratio of the image.
The time delay integral image sensor is divided into a CCD and a CMOS. One method is to manufacture a TDI image sensor on a CCD process, and due to the particularity of the CCD process, other processing circuits cannot be integrated on the TDI image sensor, so that the universality and the flexibility are poor. Another type of TDI image sensor is a CMOS type, which is based on a general CMOS manufacturing process, and a device having a CCD-like function, i.e., eccd (embedded CCD), is embedded, thereby forming a TDI-CMOS image sensor.
However, the performance of the existing TDI-CMOS image sensor is still poor.
Disclosure of Invention
The invention provides a back-illuminated time delay integral image sensor and a forming method thereof, which are used for improving the performance of the back-illuminated time delay integral image sensor.
In order to solve the above technical problem, a technical solution of the present invention provides a backside illuminated time delay integral image sensor, including: the substrate comprises a first face and a second face which are opposite, the substrate comprises a plurality of photoelectric doping regions, and the surfaces of the photoelectric doping regions are exposed out of the first face; a circuit device layer on the first side; and the anti-reflection and anti-reflection layer is positioned on the second surface and covers a plurality of the photoelectric doped regions.
Optionally, the material of the anti-reflection layer includes: fluoride, oxide or nitride; the fluorinated compound comprises: magnesium fluoride or barium fluoride; the oxide includes: hafnium oxide, zirconium oxide, tantalum oxide, or aluminum oxide; the nitride includes: silicon nitride or silicon oxynitride.
Optionally, the thickness range of the anti-reflection layer is as follows: 200 to 1500 angstroms.
Optionally, the circuit device layer includes: a dielectric layer on the substrate; the gate structures are positioned in the dielectric layer, positioned on the surface of each photoelectric doping region and positioned on the first surface; an interconnect structure located within the dielectric layer.
Optionally, the plurality of gate structures are arranged in parallel along a first direction, the plurality of gate structures cross over one of the photoelectric doped regions along a second direction, and the second direction is perpendicular to the first direction.
Optionally, the interconnect structure includes: several overlapped conductive layers on the gate structure; and the conductive plugs are positioned between two adjacent conductive layers, between the conductive layers and the substrate or between the conductive layers and the grid electrode structure.
Optionally, the method further includes: and the first protective layer is positioned on the surface of the dielectric layer.
Optionally, the material of the first protective layer includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
Optionally, the method further includes: and the second protective layer is positioned on the surface of the second surface and positioned between the anti-reflection layer and the substrate.
Optionally, the material of the second protective layer includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
Optionally, the gate structure includes: the gate electrode layer is positioned on the surface of the gate dielectric layer.
Optionally, the substrate further comprises: the isolation regions are positioned between the adjacent photoelectric doping regions; the isolation region has an isolation structure therein.
Optionally, the substrate is doped with first ions; the photoelectric doping area is doped with second ions, and the conductivity types of the first ions and the second ions are opposite.
Correspondingly, the technical scheme of the invention also provides a forming method of any one of the back-illuminated time delay integral image sensors, which comprises the following steps: providing a substrate, wherein the substrate comprises a first face and a second face which are opposite, the substrate comprises a plurality of photoelectric doping regions, and the surface of each photoelectric doping region is exposed by the first face; forming a circuit device layer on the first face; and forming an anti-reflection and anti-reflection layer on the second surface, wherein the anti-reflection and anti-reflection layer covers a plurality of photoelectric doped regions.
Optionally, the formation process of the anti-reflection and anti-reflection layer includes: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Optionally, the circuit device layer includes: a dielectric layer on the substrate; the gate structures are positioned in the dielectric layer, positioned on the surface of each photoelectric doping region and positioned on the first surface; an interconnect structure located within the dielectric layer; the method for forming the back-illuminated time delay integral image sensor further comprises the following steps: and after the dielectric layer is formed and before the anti-reflection and anti-reflection layer is formed, forming a first protective layer on the surface of the dielectric layer.
Optionally, the method further includes: and after the first protective layer is formed and before the anti-reflection and anti-reflection layer is formed, a second protective layer is formed on the surface of the second surface.
Optionally, the method further includes: and thinning the substrate after the first protective layer is formed and before the second protective layer is formed.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the back-illuminated time delay integral image sensor provided by the technical scheme of the invention, the second surface is provided with an anti-reflection layer. When the back of the image sensor is illuminated, namely, light passing through the anti-reflection layer enters the substrate from the second surface, in this way, the light can directly enter the photoelectric doping region for photoelectric conversion, so that the blocking of devices in a circuit device layer is avoided, the improvement of the light incidence quantity is facilitated, the sensitivity, the signal-to-noise ratio and the quantum effect of the back-illuminated time delay integral image sensor are improved, and the performance of the back-illuminated time delay integral image sensor is better.
Further, the back-illuminated time delay integration image sensor further includes: the first protective layer is positioned on the surface of the interconnection structure, and can reduce the influence of a conductive layer and a conductive plug in the interconnection structure on subsequent processes, so that the interconnection structure is protected. Further, the back-illuminated time delay integration image sensor further includes: and the second protective layer is positioned on the surface of the second surface and positioned between the anti-reflection layer and the substrate. On one hand, the second protective layer can increase the bonding force between the anti-reflection layer and the substrate, and on the other hand, the second protective layer can passivate the silicon surface and reduce the damage and ion pollution to the silicon substrate.
Drawings
Fig. 1 to 3 are schematic structural views of a time delay integral image sensor;
fig. 4 to 11 are schematic structural diagrams of steps of a method for forming a backside illuminated time delay integration image sensor according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of the existing time delay integration image sensor is poor.
The reason why the performance of the conventional time delay integral image sensor is poor will be described in detail below with reference to the accompanying drawings, and fig. 1 to 3 are schematic structural diagrams of the time delay integral image sensor.
Referring to fig. 1 to fig. 3, fig. 2 is a schematic cross-sectional structure of fig. 1 along a-a1, fig. 3 is a schematic cross-sectional structure of fig. 1 along a B-B1, fig. 1 is a top view of fig. 2 along the X direction, it should be noted that fig. 1 is a schematic diagram of omitting a structure located on a gate structure, and an image sensor includes: the substrate 100 comprises a first surface 101 and a second surface 102 which are opposite, the substrate 100 comprises a plurality of pixel regions I, and an isolation region II is arranged between every two adjacent pixel regions I; a photoelectric doped region 110 located in the pixel region I; a plurality of gate structures 120 located on the first surface 101, and a plurality of the gate structures 120 cross over one of the photo-electrically doped regions; an interconnect structure 130 on the gate structure; an anti-reflective anti-reflection layer 140 on the interconnect structure 130.
In the time delay integral image sensor, the substrate 100 has first doped ions therein, the photo doping 110 has second doped ions therein, and the conductivity type of the first doped ions is opposite to that of the second doped ions, so that a photodiode can be formed. When light irradiates the substrate 100, the photodiode converts photons into electrons by a photovoltaic effect, thereby realizing generation of signal charges; by applying a voltage to the gate structure 120, a potential well is formed in the substrate 100 below the gate structure 120, and electrons generated by the photodiode are collected in the potential well, so that storage of signal charges is realized; by applying different voltages to different gate structures 120, the charges stored in the driving potential well can be transferred toward a certain direction.
However, when light irradiates the time delay integral image sensor from the front side, that is, when the light is incident from the anti-reflection layer 120 on the first side 101, the light is blocked by the stacked interconnection structures 130 and the gate structures 120 before entering into the substrate 100, resulting in low sensitivity, signal-to-noise ratio and quantum efficiency of the image sensor, so that the performance of the image sensor is poor.
In order to solve the above technical problem, an embodiment of the present invention provides a backside illuminated time delay integral image sensor, including: the substrate comprises a first surface and a second surface which are opposite, the substrate comprises a plurality of photoelectric doping regions, and the surfaces of the photoelectric doping regions are exposed from the first surface; a circuit device layer on the first side; and the anti-reflection and anti-reflection layer is positioned on the second surface and covers a plurality of the photoelectric doped regions. The performance of the graphic sensor is better.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 11 are schematic structural diagrams of steps of a method for forming a backside illuminated time delay integration image sensor according to an embodiment of the present invention.
Referring to fig. 4 and 5, fig. 5 is a schematic cross-sectional view of fig. 4 along a direction of a tangent M-N, fig. 4 is a top view of fig. 5 along a direction X, a substrate 200 is provided, the substrate 200 includes a first surface 201 and a second surface 202 opposite to the first surface 201, the substrate 200 includes a plurality of photoelectric doped regions 210, and the first surface 201 exposes a surface of the photoelectric doped regions 210.
The material of the substrate 200 is a semiconductor material. In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
In this embodiment, the substrate 200 further includes: a plurality of isolation regions (not shown) between adjacent photodoped regions 210; the isolation region has an isolation structure 211 therein.
In the present embodiment, the substrate 200 is doped with first ions; the photo-electric doping region 210 is doped with second ions, and the conductivity types of the first ions and the second ions are opposite.
Specifically, the base 200 includes a substrate (not shown in the figure) and a silicon epitaxial layer (not shown in the figure) on the surface of the substrate, the first side 201 is an exposed surface of the silicon epitaxial layer, and the second side 202 is an exposed surface of the substrate.
Since the second doping ions in the photo-electric doping region 210 have the opposite conductivity type to the first doping ions in the substrate 200, a photodiode is constructed. The photodiode is used for converting photons in incident light into electrons.
In this embodiment, the first ions are P-type ions, and include: boron ions, the second ions being N-type ions, comprising: phosphorus ions or arsenic ions.
In other embodiments, the first ions are N-type ions and the second ions are P-type ions.
Referring to fig. 6 and 7, fig. 6 is a schematic diagram based on fig. 4, fig. 7 is a schematic diagram based on fig. 5, and it should be noted that fig. 6 is a schematic diagram of omitting a structure on a gate structure, and a circuit device layer 220 is formed on the first surface 201.
The circuit device layer 220 is used to electrically connect the photodiode to peripheral circuitry.
The circuit device layer 220 includes: a dielectric layer (not shown) on the substrate 200; a plurality of gate structures 221 located in the dielectric layer, wherein the plurality of gate structures 221 are located on the surface of each of the photoelectric doped regions 210, and the plurality of gate structures 210 are located on the first surface 201; an interconnect structure 224 located within the dielectric layer.
The forming method of the circuit device layer 220 comprises the following steps: forming a plurality of gate structures 221 on the first surface 201; forming a first dielectric layer 222 on the first surface 201, wherein the first dielectric layer 222 covers top surfaces and sidewall surfaces of the gate structures 221; and forming a second dielectric layer 223 on the surface of the first dielectric layer 221, wherein the second dielectric layer 223 is internally provided with an interconnection structure 224.
In this embodiment, the dielectric layers include a first dielectric layer 222 on the first side 201 and a second dielectric layer 223 on a surface of the first dielectric layer 222.
In the present embodiment, a plurality of the gate structures 221 are arranged in parallel along a first direction Y1, and a plurality of the gate structures cross over one of the photo-electric doping regions 210 along a second direction Y2, wherein the second direction Y2 is perpendicular to the first direction Y1.
In this embodiment, the interconnect structure 224 includes: several overlapped conductive layers (not shown) on the gate structure 221; and a conductive plug (not shown) between two adjacent conductive layers, between the conductive layer and the substrate, or between the conductive layer and the gate structure.
Referring to fig. 8, a first protection layer 230 is formed on the surface of the circuit device layer 220.
In this embodiment, specifically, the first protection layer 230 is formed on the surface of the dielectric layer.
The first protective layer 230 is used to reduce the influence of the external environment on the devices in the circuit device layer 220.
The material of the first protective layer 230 includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
In this embodiment, the material of the first protection layer 230 is silicon oxide.
The forming process of the first protection layer 230 includes: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Referring to fig. 9, after the first passivation layer 230 is formed, the substrate 200 is thinned.
It should be noted that the substrate 200 after thinning is still the substrate 200, and the substrate 200 after thinning includes a first side 201 and a second side 202 opposite to each other.
The thinning treatment method comprises the following steps: providing a carrier substrate (not shown); bonding the surface of the carrier substrate to the surface of the first protective layer 230 on the substrate 200; after the bonding process, a thinning process is performed on the substrate 200 from the second surface 202 to form a final substrate 200.
The thinning process comprises the following steps: and (5) carrying out a chemical mechanical polishing process.
Referring to fig. 10, after the thinning process, a second protection layer 240 is formed on the surface of the second side 202.
The second protective layer 240 serves to increase the bonding force between the subsequently formed anti-reflection layer and the substrate 200, and to reduce damage and ion contamination to the silicon substrate.
The forming process of the second protection layer 240 includes: a thermal oxidation process, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The material of the second protective layer 240 includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
In this embodiment, the material of the second protection layer 240 is silicon oxide.
Referring to fig. 11, after the second passivation layer 240 is formed, an anti-reflection layer 250 is formed on the second surface 202, and the anti-reflection layer 250 covers a plurality of the electro-optically doped regions 210.
The antireflection layer 250 serves to reduce reflection of light, thereby contributing to an increase in the amount of light incident.
The materials of the anti-reflection layer 250 include: fluoride, oxide or nitride; the fluorinated compound comprises: magnesium fluoride or barium fluoride; the oxide includes: hafnium oxide, zirconium oxide, tantalum oxide, or aluminum oxide; the nitride includes: silicon nitride or silicon oxynitride. In this embodiment, the anti-reflection layer 250 is made of tantalum oxide, the thickness of the anti-reflection layer is 520 angstroms, and the anti-reflection layer 250 can effectively reduce the reflection of light, so as to increase the incident amount of light entering the substrate 200.
The process for forming the anti-reflection layer 250 includes: a chemical vapor deposition process, a physical vapor deposition process, or a spin-on process.
By forming the antireflective layer 250 on the second side 202. When light is irradiated from the back of the time delay integration image sensor, that is, light passing through the anti-reflection layer 250 enters the substrate 200 from the second surface 202, so that light can be incident and directly enter the photoelectric doped region 210 for photoelectric conversion, blocking of devices in the circuit device layer 220 is avoided, improvement of light incidence is facilitated, sensitivity, signal-to-noise ratio and quantum effect of the image sensor are improved, and performance of the image sensor is better.
Accordingly, an embodiment of the present invention further provides a backside illuminated time delay integral image sensor formed by the above method, please refer to fig. 11, including: the substrate 200, the substrate 200 includes a first side 201 and a second side 202 opposite to each other, the substrate 200 includes a plurality of photoelectric doped regions 210, and the surface of the photoelectric doped region 210 is exposed by the first side 201; a circuit device layer 220 on the first side 201; an anti-reflection layer 250 is disposed on the second surface 202, and the anti-reflection layer 250 covers a plurality of the electro-optically doped regions 210.
Since the second side 202 has an anti-reflection layer 250 thereon. When the image sensor is illuminated from the back side, that is, light passing through the anti-reflection layer 250 enters the substrate 200 from the second surface 202, in this way, the light can directly enter the photoelectric doped region 210 for photoelectric conversion, so that the light is prevented from being blocked by devices in the circuit device layer 220, the improvement of the incident amount of the light is facilitated, the sensitivity, the signal-to-noise ratio and the quantum effect of the image sensor are improved, and the performance of the image sensor is better.
The following detailed description is made with reference to the accompanying drawings.
The materials of the anti-reflection layer 250 include: fluoride, oxide or nitride; the fluorinated compound comprises: magnesium fluoride or barium fluoride; the oxide includes: hafnium oxide, zirconium oxide, tantalum oxide, or aluminum oxide; the nitride includes: silicon nitride or silicon oxynitride.
In this embodiment, the material of the anti-reflection layer 250 is tantalum oxide.
The thickness range of the anti-reflection and anti-reflection layer 250 is as follows: 200 to 1500 angstroms.
The significance of selecting said thickness range is: if the thickness is less than 200 angstroms, the reflection of light cannot be effectively reduced by the anti-reflection layer 250 with too thin thickness, so that the incident amount of light entering the substrate 200 is still low, and the performance of the formed image sensor is poor; if the thickness is greater than 1500 angstroms, forming the anti-reflection layer 250 with too thick thickness will increase the process cost and time, and is not good for improving the working efficiency.
The circuit device layer 220 includes: a dielectric layer (not shown) on the substrate 200; a plurality of gate structures 221 located in the dielectric layer, wherein the plurality of gate structures 221 are located on the surface of each of the photoelectric doped regions 210, and the plurality of gate structures 221 are located on the first surface 201; an interconnect structure 224 located within the dielectric layer.
In this embodiment, the dielectric layers include a first dielectric layer 222 on the first side 201 and a second dielectric layer 223 on a surface of the first dielectric layer 222.
In the present embodiment, a plurality of the gate structures 221 are arranged in parallel along a first direction Y1 (shown in fig. 7), a plurality of the gate structures 221 cross one of the photo-electric doping regions 210 along a second direction Y2 (shown in fig. 7), and the second direction Y2 is perpendicular to the first direction Y1.
The gate structure 221 includes: a gate dielectric layer (not shown) on the surface of the first side 201 and a gate electrode layer (not shown) on the surface of the gate dielectric layer.
In this embodiment, the gate dielectric layer is made of silicon oxide, and the gate electrode layer is made of polysilicon.
The interconnect structure 224 includes: several overlapping conductive layers (not shown) over the gate structure 221; and a conductive plug (not shown) between two adjacent conductive layers, between the conductive layer and the substrate, or between the conductive layer and the gate structure.
The back-illuminated time delay integral image sensor further includes: a first protective layer 230 on the surface of the dielectric layer.
The first protection layer 230 can reduce the influence of the conductive layer and the conductive plug in the interconnect structure 224 from the subsequent processes, and protect the interconnect structure 224, thereby improving the performance of the image sensor.
The material of the first protective layer 230 includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
In this embodiment, the first protection layer 230 is made of: silicon oxide.
The back-illuminated time delay integral image sensor further includes: and a second protective layer 240 on the surface of the second side 202, wherein the second protective layer 240 is located between the anti-reflection layer 250 and the substrate 200.
The second protective layer 240 functions to, on one hand, increase the bonding force between the anti-reflection layer 250 and the substrate 200, and on the other hand, passivate the silicon surface and reduce the damage and ion contamination to the silicon substrate.
The material of the second protective layer 240 includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
In this embodiment, the material of the second protection layer 240 is silicon oxide.
In this embodiment, the substrate 200 further includes: isolation regions (not shown) between adjacent photodoped regions 210; the isolation region has an isolation structure 211 therein.
In the present embodiment, the substrate 200 is doped with first ions; the photoelectric doping area is doped with second ions, and the conductivity types of the first ions and the second ions are opposite.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A backside-illuminated time delay integral image sensor, comprising:
the substrate comprises a first face and a second face which are opposite, the substrate comprises a plurality of photoelectric doping regions, and the surfaces of the photoelectric doping regions are exposed out of the first face;
a circuit device layer on the first side;
and the anti-reflection and anti-reflection layer is positioned on the second surface and covers a plurality of the photoelectric doped regions.
2. The backside-illuminated time delay integration image sensor of claim 1, wherein the material of the anti-reflection layer comprises: fluoride, oxide or nitride; the fluorinated compound comprises: magnesium fluoride or barium fluoride; the oxide includes: hafnium oxide, zirconium oxide, tantalum oxide, or aluminum oxide; the nitride includes: silicon nitride or silicon oxynitride.
3. The backside illuminated time delay integration image sensor of claim 1, wherein the anti-reflection layer has a thickness in the range of: 200 to 1500 angstroms.
4. The backside-illuminated time delay integrating image sensor of claim 1, wherein the circuit device layer comprises: a dielectric layer on the substrate; a plurality of gate structures located in the dielectric layer, the plurality of gate structures being located on the surface of each of the photoelectric doped regions, and the plurality of gate structures being located on the first surface; an interconnect structure located within the dielectric layer.
5. The backside illuminated time delay integrating image sensor of claim 4, wherein a plurality of the gate structures are arranged in parallel along a first direction, and a plurality of the gate structures cross one of the electro-optically doped regions along a second direction, the second direction being perpendicular to the first direction.
6. The backside-illuminated time delay integrating image sensor of claim 4, wherein the interconnect structure comprises: several overlapped conductive layers on the gate structure; and the conductive plugs are positioned between two adjacent conductive layers, between the conductive layers and the substrate or between the conductive layers and the grid electrode structure.
7. The backside illuminated time delay integrating image sensor of claim 4, further comprising: and the first protective layer is positioned on the surface of the dielectric layer.
8. The backside-illuminated time delay integration image sensor of claim 7, wherein the material of the first protective layer comprises: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
9. The backside-illuminated time delay integration image sensor of claim 1, further comprising: and the second protective layer is positioned on the surface of the second surface and positioned between the anti-reflection layer and the substrate.
10. The backside-illuminated time delay integration image sensor of claim 9, wherein the material of the second protective layer comprises: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.
11. The backside-illuminated time delay integrating image sensor of claim 4, wherein the gate structure comprises: the gate electrode layer is positioned on the surface of the gate dielectric layer.
12. The backside-illuminated time delay integration image sensor of claim 1, wherein the substrate further comprises: the isolation regions are positioned between the adjacent photoelectric doping regions; the isolation region has an isolation structure therein.
13. The backside-illuminated time delay integration image sensor of claim 1, wherein the substrate is doped with first ions; the photoelectric doping area is doped with second ions, and the conductivity types of the first ions and the second ions are opposite.
14. The method of forming a backside illuminated time delay integrating image sensor of any of claims 1 to 13, comprising:
providing a substrate, wherein the substrate comprises a first face and a second face which are opposite, the substrate comprises a plurality of photoelectric doping regions, and the surface of each photoelectric doping region is exposed by the first face;
forming a circuit device layer on the first face;
and forming an anti-reflection and anti-reflection layer on the second surface, wherein the anti-reflection and anti-reflection layer covers a plurality of photoelectric doped regions.
15. The method of claim 14, wherein the anti-reflection layer is formed by a process comprising: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
16. The method of forming a backside illuminated time delay integrating image sensor of claim 14, wherein the circuit device layer comprises: a dielectric layer on the substrate; the gate structures are positioned in the dielectric layer, positioned on the surface of each photoelectric doping region and positioned on the first surface; an interconnect structure located within the dielectric layer; the method for forming the image sensor further comprises the following steps: and after the dielectric layer is formed and before the anti-reflection and anti-reflection layer is formed, forming a first protective layer on the surface of the dielectric layer.
17. The method of forming a backside illuminated time delay integrating image sensor of claim 16, further comprising: and after the first protective layer is formed and before the anti-reflection and anti-reflection layer is formed, a second protective layer is formed on the surface of the second surface.
18. The method of forming a backside illuminated time delay integrating image sensor of claim 17, further comprising: and thinning the substrate after the first protective layer is formed and before the second protective layer is formed.
CN201911071212.8A 2019-11-05 2019-11-05 Backside illuminated time delay integral image sensor and forming method thereof Pending CN110797363A (en)

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