CN110797072A - DRAM chip repairing method - Google Patents
DRAM chip repairing method Download PDFInfo
- Publication number
- CN110797072A CN110797072A CN201911062917.3A CN201911062917A CN110797072A CN 110797072 A CN110797072 A CN 110797072A CN 201911062917 A CN201911062917 A CN 201911062917A CN 110797072 A CN110797072 A CN 110797072A
- Authority
- CN
- China
- Prior art keywords
- chip
- repair
- repairing
- priority
- repaired
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/838—Masking faults in memories by using spares or by reconfiguring using programmable devices with substitution of defective spares
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention discloses a DRAM chip repairing method, which comprises the following steps: sorting the priority of the repair scheme of the chip from high to low according to the repair limiting conditions; and repairing the chips in sequence according to the priority of the repairing scheme until the repairing result of the chips is obtained. The invention can support the coexistence of multiple repair schemes, greatly shortens the repair time of the DRAM and further reduces the test time; meanwhile, multiple repair schemes can coexist simultaneously, so that the quality of the chip is improved.
Description
Technical Field
The invention relates to the field of memory repair, in particular to a DRAM chip repair method.
Background
In the conventional repair process of the DRAM, only one repair method can be supported. However, with the complexity of DRAM manufacturing processes and the increasing demand of DRAM quality from the market, the DRAM repair methods provided by chip designers are becoming more and more diversified, and therefore, only one repair method can be supported during the DRAM test process, which greatly reduces the test efficiency.
As shown in fig. 1, the figure is a DRAM repair flow diagram with multiple repair schemes coexisting, which is implemented using the existing repair flow. Assuming that there are two repair methods for a DRAM product, since the existing repair process can only support one repair method, the repair process is as follows:
1) extracting the failure address of each DRAM chip on the wafer for the first time;
2) each chip is repaired by adopting a repairing method 1:
storing the repair result of each chip which can be repaired by the repair method 1;
3) extracting the failure address of each chip on the wafer for the second time;
4) repairing by adopting a repairing method 2, and storing the repairing result of each chip which can be repaired by the repairing method 2;
5) screening a DRAM chip repairing method:
and comparing the repair result files of the two repair methods, and screening the final repair result of the chip.
Assuming that the repair method 1 is a preferred repair scheme (the preferred repair scheme is a repair scheme with the most repair limiting conditions, and the possibility that the chip can be repaired under the repair scheme is the lowest), the chip can be repaired by the repair method 1, that is, the repair result of the repair method 1 is stored in a final repair file; if the file can only be repaired by the repairing method 2, storing the repairing result of the repairing method 2 in a final repairing file; if the two repairing methods can not repair the chip, the chip is subjected to bad chip treatment;
6) and generating a repairing scheme for each DRAM chip on the wafer.
By adopting the repairing method, the failure address of each DRAM chip on the wafer can be extracted twice, and meanwhile, each DRAM chip needs to be repaired by adopting two repairing methods, so that the consumption of testing time is overhigh and the testing efficiency is lower.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a DRAM chip repairing method, which can support the coexistence of multiple repairing schemes, greatly shortens the repairing time of the DRAM and further reduces the testing time; meanwhile, multiple repair schemes can coexist simultaneously, so that the quality of the chip is improved.
In order to achieve the purpose, the invention adopts the following technical means:
a DRAM chip repairing method comprises the following steps:
sorting the priority of the chip repair scheme from high to low according to the repair limiting conditions;
and repairing the chips in sequence according to the priority of the repairing scheme until the repairing result of the chips is obtained.
Preferably, the priority of the chip repair scheme is divided into a first priority repair scheme and a second priority repair scheme from high to low;
the first priority repair scheme is the repair scheme with the most limiting conditions.
Preferably, the method comprises the steps of:
step S1: extracting a failure address;
step S2: a first priority repair analysis;
step S3: judging whether the chip can be repaired for the first time;
the step S3 includes:
step S3.1 if the chip can be repaired, go to step S7;
step S3.2 if the chip is not repairable, step S4 is performed;
step S4: second priority repair analysis;
step S5: judging that the chip can be repaired for the second time;
the step S5 includes:
step S5.1 if the chip can be repaired, go to step S7;
step S5.2 if the chip is not repairable, step S6 is performed;
step S6: processing chips as waste chips;
-said step S6 is:
after the chip is subjected to repair analysis by the second priority repair scheme with less restriction conditions, if the chip still cannot be repaired, the chip is subjected to scrap processing, the test result does not record the information of the chip, and then the step S8 is skipped to;
step S7: generating a chip repair scheme;
step S8: and finishing the chip repair.
Preferably, the method further comprises the steps of:
step S9: circulating the chip;
step S10: and finishing the wafer repairing.
Preferably, the step S1 extracts the failing address as: and extracting the chip failure address on the wafer.
Preferably, the step S2 includes a first priority repair analysis: and carrying out repair analysis on the chip by adopting the first repair scheme with the most limiting conditions.
Preferably, the limiting conditions are: the failed address inside the smallest individual repair cell is replaced by a redundant word line or a redundant column selection line inside the individual repair cell.
Preferably, the failing address is preferably replaced with a redundant word line or a redundant column selection line having no failing point.
Preferably, the step S7 of generating the chip repair solution is: and generating a repair result through the chip subjected to the first priority repair analysis or the chip subjected to the second priority repair analysis, and storing the repair result through a file.
Preferably, the step S9 is a chip loop: and (4) performing repair analysis on the residual chips on the wafer according to the steps from S2 to S8.
Preferably, the wafer repairing in step S10 ends with: after all the chips on the wafer have performed the repairing analysis process from step S2 to step S8, the repairing of the wafer is completed.
As a further improvement of the invention, the chip is divided into a plurality of independent repair units according to the repair rules of the redundant word lines and the redundant column selection lines, and each independent repair unit is repaired according to the priority of the repair scheme.
Optionally, the method includes:
providing two configuration files, wherein the two configuration files respectively describe the dividing modes of two blocks in a chip and the allocation schemes of redundant word lines and redundant column selection lines;
scanning the configuration file according to a syntax analyzer to generate two code level descriptions for dividing the internal blocks of the chip;
generating two repair algorithms according to the two code level descriptions, and assigning the priority of the algorithms;
and respectively carrying out two repair algorithms on each chip or the independent repair unit in the chip according to the priority of the algorithms until the chip or the independent repair unit in the chip can be repaired or can not be repaired.
Optionally, the method comprises the following steps:
step M1: extracting a failure address;
step M2: grouping failed addresses;
step M3: a first priority repair analysis;
step M4: judging that the failure address in the group can be repaired for the first time; analyzing a group of failed addresses of the chip by adopting a first priority repair scheme to obtain a result of whether the group of failed addresses of the chip can be repaired;
the step M4 includes:
-step M4.1: if a set of failed addresses of the chip can be repaired, go to step M8;
-step M4.2: if the set of failed addresses of the chip is not repairable, performing step M5;
step M5: second priority repair analysis:
step M6: judging that the failed address in the group can be repaired for the second time;
the step M6 includes:
-step M6.1: if a set of failed addresses of the chip can be repaired, go to step M8;
-step M6.2: if the set of failed addresses of the chip is not repairable, performing step M7;
step M7: processing chips as waste chips;
the step M7 is
When the repair analysis of the chip is sequentially carried out in the independent repair units, the chip needs to be subjected to waste treatment when encountering the first irreparable independent repair unit; after the chip is processed into waste chips, the step M11 is skipped;
step M8: generating an intra-group repair scheme;
step M9: group circulation;
step M10: combining the in-group repairing plans;
step M11: and finishing the chip repair.
Optionally, the method further includes:
step M12: circulating the chip;
step M13: and finishing the wafer repairing.
Optionally, the step M1 extracts the failing address as: and extracting the chip failure address on the wafer.
Optionally, the failing address of step M2 is grouped as:
according to the distribution of the redundant word lines and the redundant column selection lines and the repair rule, the chip is divided into a plurality of independent repair units, the chip failure addresses in one independent repair unit are a group, and the number of groups of failure addresses is the same as the number of independent repair units.
Optionally, the step M6 may determine that the failed address in the group can be repaired as follows:
and analyzing the group of failed addresses of the chip by adopting a second priority repair scheme to obtain a result of whether the group of failed addresses of the chip can be repaired.
Optionally, in the step M7, in the chip invalidation process:
the chip can be modified as follows: the failure address in each independent repair unit can be repaired;
the chip is not repairable as: failed addresses within at least one of the individual repair units are not repairable.
Optionally, the step M9 is a process in which the chip sequentially loops the step M3 to the step M9 according to each group of failed addresses divided by the chip independent repair unit.
Optionally, the repair solutions in the group M10 are merged into each group of failed addresses divided according to the chip independent repair units, and then the repair solutions of the independent repair units are merged to serve as the repair solution of the chip.
Optionally, the step M12 cycles the chip as follows: and (4) sequentially carrying out repair analysis on all the chips on the wafer according to the steps M2 to M11.
Optionally, the wafer repairing in step M13 is ended: after all the chips on the wafer have performed the repairing analysis process from step M2 to step M11, the repairing of the wafer is completed.
Compared with the prior art, the invention has the following advantages:
the priority of the chip repair scheme is sorted from high to low according to the repair limiting conditions; and repairing the chips in sequence according to the priority of the repairing scheme until the repairing result of the chips is obtained. The chip is only required to be repaired and analyzed once in the whole repairing process, and the repairing and analyzing of the second repairing method are not required for the part of the chip, so that the testing time is effectively saved.
In the repairing process of the DRAM chip, the method realizes the conversion from a single repairing scheme to a multi-repairing scheme, and simultaneously, one DRAM chip can be repaired by adopting the multi-repairing scheme, thereby saving the testing time to the maximum extent and ensuring the quality of the DRAM chip; because multiple repair schemes can be stored in the same repair framework, the failure address of each DRAM chip on the wafer only needs to be extracted once, the test time is shortened, and the test cost is saved.
Preferably, the test architecture is compatible with multiple repair schemes, the repair schemes are ranked from high to low in priority, and meanwhile, independent repair units of the chip are sequentially performed according to the repair priority.
Preferably, the failure addresses of the chip are divided into groups according to the independent repair units, each independent repair unit corresponds to one group of failure addresses, and repair is performed according to the priority of the repair scheme in each independent repair unit, so that the test time can be saved, multiple repair schemes can coexist in a single chip, and the quality of the chip is greatly improved.
Drawings
Fig. 1 is a flow chart of DRAM repair with multiple concurrent repair schemes implemented using a conventional repair flow.
Fig. 2 is a repair flow diagram with multiple repair schemes in place.
Fig. 3 is a multi-repair scheme concurrent repair flow diagram for a chip independent repair unit.
FIG. 4 is a diagram of a DRAM chip structure and repair.
FIG. 5 is a schematic diagram of DRAM failure and repair.
FIG. 6 is a schematic diagram of DRAM failure and repair.
Detailed Description
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
As shown in fig. 1, the figure is a DRAM repair flow diagram with multiple repair schemes coexisting, which is implemented by using a conventional repair flow.
In the conventional repair process, only one DRAM repair scheme can be supported. It is assumed that a DRAM chip provided by a chip designer can be repaired by two repair methods. In the conventional repair process, each chip on the wafer must be repaired by aiming at the repair method 1 and the repair method 2, and then the repair results of the two repair methods are screened to finally generate the repair method of the wafer.
The specific implementation mode of the invention is as follows: and adjusting the repairing process of the DRAM, enabling multiple repairing schemes to be stored in a testing framework, and sequencing the repairing schemes from high to low in priority, so that each chip adopts the first priority repairing scheme to perform repairing analysis.
If the chip can pass the repair analysis, recording the repair result;
and if not, adopting a second priority repair scheme to perform repair analysis on the chip.
And repairing the chips in sequence according to the priority of the repairing scheme until the repairing result of the chips is obtained.
Assume that the chip has two repair schemes, a first repair scheme and a second repair scheme. The chip repair personnel will sort the priority of the repair scheme of the chip according to the repair limiting conditions. Generally, the more restrictive a repair scheme is, the higher its priority, the lower the probability that a chip will pass through the repair scheme (usually, a designer proposes a repair limiter, which is the more restrictive a chip is, the higher the quality of the chip after repair from the viewpoint of chip performance).
As shown in fig. 2, the figure is a repair flow diagram with multiple repair schemes. It can be seen from the figure that if the chip can be repaired by adopting the repairing method 1, the chip only needs to be subjected to repairing analysis once, and for the part of the chip, the repairing analysis of the repairing method 2 is not needed, so that the testing time is effectively saved; the repair flow with the coexistence of multiple repair schemes shown in fig. 2 is as follows:
step S1: extracting a failure address;
the method specifically comprises the following steps: and extracting the failure address of each DRAM chip on the wafer.
Step S2: a first priority repair analysis;
the method specifically comprises the following steps: adopting a first repairing scheme with the most limiting conditions to carry out repairing analysis on the chip;
the limiting conditions may be:
the failure address in the minimum independent repairing unit is replaced by the redundant word line or the redundant column selection line in the independent repairing unit, so that the advantages that: the address decoder has minimum transmission delay;
the failure address is preferably replaced by a redundant word line or a redundant column selection line without a failure point, and the following advantages are achieved: no special repair schemes need to be initiated to account for migration of failed addresses.
Step S3: judging whether the chip can be repaired for the first time
The method specifically comprises the following steps: and analyzing the failure address of the chip by adopting a first-priority repair scheme to obtain a result of whether the chip can be repaired.
Step S3 specifically includes:
step S3.1 if the chip can be repaired, go to step S7;
step S3.2 if the chip is not repairable, execute step S4;
step S4 second priority repair analysis:
the method specifically comprises the following steps: namely, a second repair scheme with less limiting conditions is adopted to carry out repair analysis on the chip.
Step S5 is performed to determine that the chip can be repaired for the second time;
the method specifically comprises the following steps: and analyzing the failure address of the chip by adopting a second priority repair scheme to obtain a result of whether the chip can be repaired.
Step S5 specifically includes:
step S5.1 if the chip can be repaired, go to step S7;
step S5.2 if the chip is not repairable, step S6 is performed.
Step S6, the chip is processed into waste chips;
the method specifically comprises the following steps: after the chip is subjected to repair analysis by the second priority repair scheme with less restriction conditions, if the chip still cannot be repaired, the chip is subjected to scrap processing, the test result does not record the information of the chip, and then the step S8 is skipped to;
step S7 generates a chip repair plan.
The method specifically comprises the following steps: the chip which is repaired and analyzed through the first priority or the chip which is repaired and analyzed through the second priority can generate a repairing result which is saved through a file.
Step S8, the chip repair is finished;
step S9, circulating the chip;
the method specifically comprises the following steps: the process of repairing and analyzing the residual chips on the wafer according to the steps from S2 to S8 in sequence;
step S10 ends the wafer repair.
The method specifically comprises the following steps: after all the chips on the wafer have performed the repairing analysis process from step S2 to step S8, the repairing of the wafer is completed.
As a further improvement of the invention, the chip is further divided into a plurality of independent repair units according to the repair rules of redundant word lines (RWLroundabout word Line) and redundant Column selection lines (SCSLSPase Column Select Line), and the repair is performed according to the priority of the repair scheme aiming at each independent repair unit.
The method comprises the following specific steps:
1) two configuration files are respectively provided to describe the dividing modes of two blocks in a chip and the distribution schemes of redundant word lines (RWLreduce word lines) and redundant Column selection lines (SCSL spark Column Select lines).
2) And scanning the two configuration files by a syntax analyzer to generate code level description of the internal block division of the chip.
3) And generating two repair algorithms according to the two code level descriptions, and assigning the priority of the algorithms.
4) And trying two repair algorithms for each chip or the independent repair unit in the chip according to the priority of the algorithms respectively until the chip or the independent repair unit in the chip can be repaired or not repaired.
The flowchart shown in fig. 2 is improved to obtain the flowchart shown in fig. 3. The difference between fig. 3 and fig. 2 is that the failed addresses of the chip are divided into groups according to the independent repair units, each independent repair unit corresponds to one group of failed addresses, and the repair is performed inside each independent repair unit according to the priority of the repair scheme. By adopting the repair flow chart of fig. 3, not only can the test time be saved, but also multiple repair schemes can be stored in a single chip, thereby greatly improving the quality of the chip. As shown in fig. 3, it is a flow chart of multi-repair scheme concurrent repair for chip independent repair units.
As can be seen from the figure, the repair priorities of the chips are sequentially performed in the repair order from high to low according to the repair scheme priority on the basis of the independent repair units. The DRAM chip repaired by the flow chart can enable multiple repairing modes to be stored in the same chip, so that the quality of the DRAM chip is greatly improved; the repair procedure shown in fig. 3 is as follows:
step M1: extracting a failure address;
the method specifically comprises the following steps: extracting the failure address of each DRAM chip on the wafer;
step M2: grouping failed addresses;
the method specifically comprises the following steps: according to the distribution of the redundant word lines and the redundant column selection lines and the repair rule, the chip is divided into a plurality of independent repair units, the chip failure addresses in one independent repair unit are a group, and the number of groups of failure addresses is the same as the number of independent repair units.
Step M3: a first priority repair analysis;
the method specifically comprises the following steps: namely, the first repair scheme with the most restrictive conditions is adopted to carry out repair analysis on a group of failed addresses of the chip.
Step M4 is the first time to determine that the failed address in the group can be repaired;
the method specifically comprises the following steps: and analyzing the group of failed addresses of the chip by adopting a first-priority repair scheme to obtain a result of whether the group of failed addresses of the chip can be repaired.
Step M4.1 if a set of failed addresses of the chip can be repaired, go to step M8;
step M4.2 if a set of failed addresses of the chip is not repairable, perform step M5;
step M5 second priority repair analysis:
the method specifically comprises the following steps: namely, a second repair scheme with less limitation is adopted to perform repair analysis on a group of failed addresses of the chip.
Step M6 is performed for the second time to determine that the failed address in the group can be repaired;
the method specifically comprises the following steps: and analyzing the group of failed addresses of the chip by adopting a second priority repair scheme to obtain a result of whether the group of failed addresses of the chip can be repaired.
Step M6.1 if a set of failed addresses of the chip can be repaired, go to step M8;
step M6.2 if a set of failed addresses of the chip is not repairable, perform step M7;
step M7, processing chips by waste chips;
the method specifically comprises the following steps: the chip can be repaired, namely the failed address in each independent repair unit can be repaired; the chip is not repairable, i.e. the failed address inside at least one independent repair unit is not repairable. Therefore, when the repair analysis of the chip is sequentially performed in the independent repair units, the chip needs to be processed for scrap when the first irreparable independent repair unit is encountered. After the chip is processed by scrap, the process goes to step M11.
Step M8 generating an intra-group repair solution;
step M9 group loop;
the method specifically comprises the following steps: and the chip sequentially circulates the processes from the step 3 to the step 9 according to each group of failure addresses divided by the chip independent repair unit.
Step 10, merging the internal repair plans;
the method specifically comprises the following steps: and each group of failure addresses divided according to the chip independent repair units can be repaired, and then the repair schemes of the independent repair units are combined to be used as the repair scheme of the chip.
Step 11, finishing the chip repair;
step 12, circulating the chip;
the method specifically comprises the following steps: and (3) performing repair analysis on all chips on the wafer according to the steps from 2 to 11 in sequence.
And step 13, finishing the wafer repairing.
The method specifically comprises the following steps: after all the chips on the wafer have performed the repairing analysis process from step M2 to step M11, the repairing of the wafer is completed.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following description of the embodiments of the present invention with reference to the accompanying drawings and examples is given by way of illustration and not limitation.
Example 1
As shown in the structure and repair diagram of the DRAM chip of fig. 4:
in this figure, two repair schemes are provided.
The first repair scheme: based on the control mode of a Column selection Line (CSL Column Select Line) decoder, the DRAM chip is divided into two independent repair units, a redundant Column selection Line 1(SCSL spare Column Select Line) and a redundant Column selection Line 2(SCSL2) can repair the failure address of the Column Selection Line (CSL) of the independent repair unit 1, and a redundant Column selection Line 3(SCSL3) and a redundant Column selection Line 4(SCSL4) can repair the failure address of the Column Selection Line (CSL) in the independent repair unit 2.
The second repair scheme is as follows: the redundancy column select lines 1-4(SCSL1, SCSL2, SCSL3, and SCSL4) can repair any CSL failure address within the DRAM chip;
the first repair scheme may increase the column decoding speed of the DRAM compared to the second repair scheme. Assuming that one Column Selection Line (CSL) in the independent repair unit 1 is failed, if the redundant column selection line 1(SCSL1) is used for repair, after repair replacement, when the repaired Column Selection Line (CSL) is activated, an externally input column address is passed through the Column Selection Line (CSL) decoder 1, and the Column Selection Line (CSL) is activated;
if the failed Column Select Line (CSL) in the individual repair cell 1 is repaired using the redundant column select line 3(SCSL3) in the individual repair cell 2, after repair replacement, when the repaired Column Select Line (CSL) in the individual repair cell 1 is activated, an externally input column address passes through the Column Select Line (CSL) decoder 1, and passes through the Column Select Line (CSL) decoder 2, and the Column Select Line (CSL) can be activated.
Therefore, the priority ranking is performed for the two repair schemes, the first repair scheme has a first repair priority due to more limiting conditions and the performance of the DRAM chip adopting the repair scheme is higher, and the second repair scheme is a second repair priority.
Example 2
As shown in the failure and repair diagram of the DRAM of fig. 5:
this figure is based on fig. 4 and shows one type of failure, as shown in the left diagram of fig. 5, i.e. a CSL1 failure in individual repair unit 1 and a CSL2 failure in individual repair unit 2. The right diagram in fig. 5 shows the repair scheme, namely, SCSL1 repairs failed CSL1 and SCSL3 repairs failed CSL 2.
If the traditional repair process shown in fig. 1 is adopted, the chip needs to be repaired twice, that is, the first repair scheme and the second repair scheme are adopted to perform repair respectively, corresponding repair results are generated, and then the repair results of the first repair scheme are retained and used for repairing the chip through merging and comparison.
If the repair process with multiple repair schemes coexisting in FIG. 2 is adopted, the chip only needs to perform repair calculation for 1 time, namely, the chip can be repaired by adopting the first repair scheme with higher priority, and the chip does not need to perform repair analysis by using the second repair scheme, so that the test time is halved, and the test efficiency is improved. The repair results are shown in the right panel of fig. 5, with SCSL1 repairing failed CSL1 and SCSL3 repairing failed CSL 2.
Example 3
As shown in the failure and repair diagram of the DRAM of fig. 6:
this figure shows one type of failure based on fig. 4, as shown in the left diagram of fig. 6, i.e. with CSL1 failure in individual repair unit 1 and CSL2, CSL3 and CSL4 failure in individual repair unit 2. The middle graph in fig. 6 is a possible repair mode based on fig. 2, namely, SCSL1 repairing failed CSL3, SCSL2 repairing failed CSL2, SCSL3 repairing failed CSL4, and SCSL4 repairing failed CSL 1. The right graph in fig. 6 is a repair mode based on fig. 3, namely, SCSL1 repairing failed CSL1, SCSL2 repairing failed CSL2, SCSL3 repairing failed CSL4, and SCSL4 repairing failed CSL 3.
When the repair flow with multiple repair schemes in fig. 2 is adopted, since the redundancy replacement of the DRAM is performed randomly, the middle diagram in fig. 6 shows a possible repair manner, that is, SCSL1 repairs failed CSL3, SCSL2 repairs failed CSL2, SCSL3 repairs failed CSL4, and SCSL4 repairs failed CSL 1. By adopting the repair method, the repaired CSL1, CSL2 and CSL3 are replaced by the SCSLs of the adjacent independent repair units, so that the problem of slow speed exists in the column address decoding process.
When the repair flow of fig. 3 with multiple repair schemes for the chip-independent repair units is adopted, a repair manner is obtained, as shown in the right diagram of fig. 6, that is, the SCSL1 repairs the failed CSL1, the SCSL2 repairs the failed CSL2, the SCSL3 repairs the failed CSL4, and the SCSL4 repairs the failed CSL 3. The chip repaired by the repair method has the problem that only the SCSL2 has slow column address decoding, and compared with the repair result obtained by adopting the flow chart 2, the performance of the chip is improved.
Although specific embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the specific embodiments described above, which are intended to be illustrative, instructive, and not restrictive. Those skilled in the art, having the benefit of this disclosure, may effect numerous modifications thereto without departing from the scope of the invention as defined by the appended claims.
Claims (10)
1. A DRAM chip repairing method is characterized by comprising the following steps:
sorting the priority of the chip repair scheme from high to low according to the repair limiting conditions;
and repairing the chips in sequence according to the priority of the repairing scheme until the repairing result of the chips is obtained.
2. The method for repairing a DRAM chip according to claim 1, wherein:
the priority of the chip repair scheme is divided into a first priority repair scheme and a second priority repair scheme from high to low;
the first priority repair scheme is the repair scheme with the most limiting conditions.
3. The method for repairing a DRAM chip according to claim 2, wherein:
the method comprises the following steps:
step S1: extracting a failure address;
step S2: a first priority repair analysis;
step S3: judging whether the chip can be repaired for the first time;
the step S3 includes:
step S3.1 if the chip can be repaired, go to step S7;
step S3.2 if the chip is not repairable, step S4 is performed;
step S4: second priority repair analysis;
step S5: judging that the chip can be repaired for the second time;
the step S5 includes:
step S5.1 if the chip can be repaired, go to step S7;
step S5.2 if the chip is not repairable, step S6 is performed;
step S6: processing chips as waste chips;
-said step S6 is:
after the chip is subjected to repair analysis by the second priority repair scheme with less restriction conditions, if the chip still cannot be repaired, the chip is subjected to scrap processing, the test result does not record the information of the chip, and then the step S8 is skipped to;
step S7: generating a chip repair scheme;
step S8: and finishing the chip repair.
4. A method for repairing a DRAM chip as claimed in claim 3, wherein:
the method further comprises the steps of:
step S9: circulating the chip;
step S10: and finishing the wafer repairing.
5. The method for repairing a DRAM chip according to claim 1, wherein:
the chip is divided into a plurality of independent repairing units according to the repairing rules of the redundant word lines and the redundant column selection lines, and each independent repairing unit is repaired according to the priority of the repairing scheme.
6. The method for repairing a DRAM chip according to claim 5, wherein:
the method comprises the following steps:
providing two configuration files, wherein the two configuration files respectively describe the dividing modes of two blocks in a chip and the allocation schemes of redundant word lines and redundant column selection lines;
scanning the configuration file according to a syntax analyzer to generate two code level descriptions for dividing the internal blocks of the chip;
generating two repair algorithms according to the two code level descriptions, and assigning the priority of the algorithms;
and respectively carrying out two repair algorithms on each chip or the independent repair unit in the chip according to the priority of the algorithms until the chip or the independent repair unit in the chip can be repaired or can not be repaired.
7. The method for repairing a DRAM chip according to claim 5, wherein:
the method comprises the following steps:
step M1: extracting a failure address;
step M2: grouping failed addresses;
step M3: a first priority repair analysis;
step M4: judging that the failure address in the group can be repaired for the first time; analyzing a group of failed addresses of the chip by adopting a first priority repair scheme to obtain a result of whether the group of failed addresses of the chip can be repaired;
the step M4 includes:
-step M4.1: if a set of failed addresses of the chip can be repaired, go to step M8;
-step M4.2: if the set of failed addresses of the chip is not repairable, performing step M5;
step M5: second priority repair analysis:
step M6: judging that the failed address in the group can be repaired for the second time;
the step M6 includes:
-step M6.1: if a set of failed addresses of the chip can be repaired, go to step M8;
-step M6.2: if the set of failed addresses of the chip is not repairable, performing step M7;
step M7: processing chips as waste chips;
the step M7 is
When the repair analysis of the chip is sequentially carried out in the independent repair units, the chip needs to be subjected to waste treatment when encountering the first irreparable independent repair unit; after the chip is processed into waste chips, the step M11 is skipped;
step M8: generating an intra-group repair scheme;
step M9: group circulation;
step M10: combining the in-group repairing plans;
step M11: and finishing the chip repair.
8. The method for repairing a DRAM chip according to claim 7, wherein:
the method further comprises the following steps:
step M12: circulating the chip;
step M13: and finishing the wafer repairing.
9. The method for repairing a DRAM chip according to claim 7, wherein:
the step M2 failure address is grouped as:
according to the distribution of the redundant word lines and the redundant column selection lines and the repair rule, the chip is divided into a plurality of independent repair units, the chip failure addresses in one independent repair unit are a group, and the number of groups of failure addresses is the same as the number of independent repair units.
10. The method for repairing a DRAM chip according to claim 7, wherein:
the step M6 determines for the second time that the failed address in the group can be repaired as:
and analyzing the group of failed addresses of the chip by adopting a second priority repair scheme to obtain a result of whether the group of failed addresses of the chip can be repaired.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911062917.3A CN110797072B (en) | 2019-10-31 | 2019-10-31 | DRAM chip repairing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911062917.3A CN110797072B (en) | 2019-10-31 | 2019-10-31 | DRAM chip repairing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110797072A true CN110797072A (en) | 2020-02-14 |
| CN110797072B CN110797072B (en) | 2021-09-21 |
Family
ID=69440848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911062917.3A Active CN110797072B (en) | 2019-10-31 | 2019-10-31 | DRAM chip repairing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110797072B (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111415700A (en) * | 2020-04-24 | 2020-07-14 | 西安紫光国芯半导体有限公司 | Repair method, repair device and computer storage medium |
| CN114078561A (en) * | 2020-08-18 | 2022-02-22 | 长鑫存储技术有限公司 | Method and device for determining failed bit repairing scheme |
| CN115881202A (en) * | 2023-02-09 | 2023-03-31 | 长鑫存储技术有限公司 | Repair circuit and method, memory and electronic equipment |
| US11791010B2 (en) | 2020-08-18 | 2023-10-17 | Changxin Memory Technologies, Inc. | Method and device for fail bit repairing |
| US11791012B2 (en) | 2021-03-31 | 2023-10-17 | Changxin Memory Technologies, Inc. | Standby circuit dispatch method, apparatus, device and medium |
| US11797371B2 (en) | 2020-08-18 | 2023-10-24 | Changxin Memory Technologies, Inc. | Method and device for determining fail bit repair scheme |
| US11853152B2 (en) | 2020-08-18 | 2023-12-26 | Changxin Memory Technologies, Inc. | Fail bit repair method and device |
| US11881278B2 (en) | 2021-03-31 | 2024-01-23 | Changxin Memory Technologies, Inc. | Redundant circuit assigning method and device, apparatus and medium |
| US11887685B2 (en) | 2020-08-18 | 2024-01-30 | Changxin Memory Technologies, Inc. | Fail Bit repair method and device |
| CN117762069A (en) * | 2023-12-14 | 2024-03-26 | 上海源斌电子科技有限公司 | Control chip automatic data processing system and method based on Internet of things |
| US11984179B2 (en) | 2021-03-26 | 2024-05-14 | Changxin Memory Technologies, Inc. | Redundant circuit assigning method and device, and medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1405886A (en) * | 2001-09-14 | 2003-03-26 | 富士通株式会社 | Semiconductor device |
| CN1819062A (en) * | 2005-02-08 | 2006-08-16 | 国际商业机器公司 | Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of sram with redundancy |
| CN102890971A (en) * | 2012-10-22 | 2013-01-23 | 上海宏力半导体制造有限公司 | Reliability test method for memory |
| CN105448348A (en) * | 2014-06-06 | 2016-03-30 | 北京兆易创新科技股份有限公司 | Chip repair method and chip repair apparatus |
-
2019
- 2019-10-31 CN CN201911062917.3A patent/CN110797072B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1405886A (en) * | 2001-09-14 | 2003-03-26 | 富士通株式会社 | Semiconductor device |
| CN1819062A (en) * | 2005-02-08 | 2006-08-16 | 国际商业机器公司 | Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of sram with redundancy |
| CN102890971A (en) * | 2012-10-22 | 2013-01-23 | 上海宏力半导体制造有限公司 | Reliability test method for memory |
| CN105448348A (en) * | 2014-06-06 | 2016-03-30 | 北京兆易创新科技股份有限公司 | Chip repair method and chip repair apparatus |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111415700A (en) * | 2020-04-24 | 2020-07-14 | 西安紫光国芯半导体有限公司 | Repair method, repair device and computer storage medium |
| CN114078561A (en) * | 2020-08-18 | 2022-02-22 | 长鑫存储技术有限公司 | Method and device for determining failed bit repairing scheme |
| WO2022037197A1 (en) * | 2020-08-18 | 2022-02-24 | 长鑫存储技术有限公司 | Method and apparatus for determining failed-bit repair scheme |
| CN114078561B (en) * | 2020-08-18 | 2023-09-12 | 长鑫存储技术有限公司 | Method and device for determining failure bit repair scheme |
| US11791010B2 (en) | 2020-08-18 | 2023-10-17 | Changxin Memory Technologies, Inc. | Method and device for fail bit repairing |
| US11887685B2 (en) | 2020-08-18 | 2024-01-30 | Changxin Memory Technologies, Inc. | Fail Bit repair method and device |
| US11797371B2 (en) | 2020-08-18 | 2023-10-24 | Changxin Memory Technologies, Inc. | Method and device for determining fail bit repair scheme |
| US11853152B2 (en) | 2020-08-18 | 2023-12-26 | Changxin Memory Technologies, Inc. | Fail bit repair method and device |
| US11984179B2 (en) | 2021-03-26 | 2024-05-14 | Changxin Memory Technologies, Inc. | Redundant circuit assigning method and device, and medium |
| US11881278B2 (en) | 2021-03-31 | 2024-01-23 | Changxin Memory Technologies, Inc. | Redundant circuit assigning method and device, apparatus and medium |
| US11791012B2 (en) | 2021-03-31 | 2023-10-17 | Changxin Memory Technologies, Inc. | Standby circuit dispatch method, apparatus, device and medium |
| CN115881202A (en) * | 2023-02-09 | 2023-03-31 | 长鑫存储技术有限公司 | Repair circuit and method, memory and electronic equipment |
| CN117762069A (en) * | 2023-12-14 | 2024-03-26 | 上海源斌电子科技有限公司 | Control chip automatic data processing system and method based on Internet of things |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110797072B (en) | 2021-09-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110797072B (en) | DRAM chip repairing method | |
| US7228468B2 (en) | Method and apparatus of build-in self-diagnosis and repair in a memory with syndrome identification | |
| US10395749B2 (en) | Method and apparatus for repairing memory device | |
| US4627053A (en) | Method of repairing semiconductor memory | |
| US5795797A (en) | Method of making memory chips using memory tester providing fast repair | |
| CN110797071B (en) | Method for repairing defects of multi-subblock NAND flash memory | |
| US7188274B2 (en) | Memory repair analysis method and circuit | |
| USRE39016E1 (en) | Memory module assembly using partially defective chips | |
| US7076700B2 (en) | Method for reconfiguring a memory | |
| CN100403443C (en) | Method and apparatus for analyzing and repairing memory | |
| US7864577B2 (en) | Sharing physical memory locations in memory devices | |
| CN114550791B (en) | Method and device for determining repair position of standby circuit and integrated circuit repair method | |
| DE10254454A1 (en) | Repair analysis device for a DRAM in a semiconductor integrated circuit using the built-in CPU | |
| Bahl | A sharable built-in self-repair for semiconductor memories with 2-D redundancy scheme | |
| CN114078564B (en) | Repair method and device for failure bit | |
| EP0889408B1 (en) | Techniques for reducing the amount of fuses in a DRAM with redundancy | |
| CN112346714A (en) | Method for optimizing software development system | |
| KR101836748B1 (en) | Apparatus and method for repairing memory banks by using various spare cells | |
| CN114078563B (en) | Repair method and device for failure bit | |
| JPS60209999A (en) | Relieving system of ic memory | |
| CN114078561B (en) | Method and device for determining failure bit repair scheme | |
| KR102388906B1 (en) | Apparatus And Method For Repairable Memory Classification | |
| US20230317198A1 (en) | Dynamic fault clustering method and apparatus | |
| JPH1074397A (en) | Memory analysis device | |
| JP2000339992A (en) | Semiconductor-testing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |