CN110795299A - Floating point verification data space compression method - Google Patents
Floating point verification data space compression method Download PDFInfo
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- CN110795299A CN110795299A CN201910861818.5A CN201910861818A CN110795299A CN 110795299 A CN110795299 A CN 110795299A CN 201910861818 A CN201910861818 A CN 201910861818A CN 110795299 A CN110795299 A CN 110795299A
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- 238000010200 validation analysis Methods 0.000 claims description 9
- 230000003068 static effect Effects 0.000 claims description 3
- 238000004088 simulation Methods 0.000 abstract description 5
- 238000004422 calculation algorithm Methods 0.000 abstract description 4
- 238000012942 design verification Methods 0.000 abstract description 3
- 238000013461 design Methods 0.000 description 9
- 238000012360 testing method Methods 0.000 description 5
- 230000005284 excitation Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 3
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
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- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
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- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49905—Exception handling
- G06F7/4991—Overflow or underflow
- G06F7/49915—Mantissa overflow or underflow in handling floating-point numbers
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Abstract
The invention relates to the technical field of computer design verification, in particular to a floating point verification data space compression method. The invention is realized by the following technical scheme: the floating point verification data space compression method is used for compressing the data space of the following three contents: the content one is as follows: compressing according to the floating point data format; and II, content II: compressing according to the special value of the rounding function point; and thirdly: compressing according to the overflow function point special value; in the first content, the permutation and combination of various floating-point format special values is verified as motivational content. The invention aims to provide an effective method for compressing and verifying a data space, which is used for carrying out efficient simulation verification on a floating-point unit, establishing a set of efficient simulation verification environment through deep analysis of an IEEE-754 floating-point standard and various floating-point operation algorithms, and successfully and efficiently completing the verification of the floating-point unit in a short time.
Description
Technical Field
The invention relates to the technical field of computer design verification, in particular to a floating point verification data space compression method.
Background
With the continual desire for high performance computing, microprocessor designs have become increasingly complex. As an important link in microprocessor design, functional verification has become a bottleneck, and faces many challenges, and the main problem is how to efficiently perform functional verification within a limited time and ensure the sufficiency and completeness of the verification.
In the field of verification, software simulation verification is a conventional method for verifying the correctness of a design by applying stimulus checking results to the design. For example, chinese patent document No. CN200810133180.5, its technical difficulties disclose that a reference model is established in the field of software verification, and the same test stimulus is applied to the reference model and the design model, and the output result and the internal state of the two are compared to determine whether the design is correct.
Such a software simulation verification solution is always the preferred method for verifying the design of the microprocessor due to its advantages of low cost and easy error location. However, as the design scale increases, the test vector space increases in geometric progression, and the disadvantage is that the operation speed is slow, and the combination of simulating all the inputs cannot be realized. Therefore, how to generate efficient test excitation and ensure the sufficiency and completeness of verification are the key and difficulty of analog verification.
Floating point units are one of the core components of high performance microprocessors, and their designs are becoming more complex, ranging from software simulation to hardware support, from supporting basic operations such as addition and multiplication of two operands to complex multiply-add operations of three operands, and the data space for design verification is also increasing exponentially. For double precision floating point number, there are 2 different data of 64 powers, if simulation verification is performed by using a processor with 1GHz dominant frequency (IPC ═ 1), all data of single operand operation can be traversed in about 545 years, all data of two operand operation requires about 545 years × 2 of 64 powers, and all data of three operand operation requires about 545 years × 2 of 128 powers. Therefore, how to improve the efficiency of analog verification is more urgent and critical for 64-bit floating point units.
Disclosure of Invention
The invention aims to provide an effective method for compressing and verifying a data space, which is used for carrying out efficient simulation verification on a floating-point unit, establishing a set of efficient simulation verification environment through deep analysis of an IEEE-754 floating-point standard and various floating-point operation algorithms, and successfully and efficiently completing the verification of the floating-point unit in a short time.
The technical purpose of the invention is realized by the following technical scheme: the floating point verification data space compression method is used for compressing the data space of the following three contents:
the content one is as follows: compressing according to the floating point data format;
and II, content II: compressing according to the special value of the rounding function point;
and thirdly: compressing according to the overflow function point special value;
in the first content, the permutation and combination of various floating-point format special values is verified as motivational content.
Preferably, the floating point format special values are eight kinds, which are respectively static non-numbers, notified non-numbers, positive infinity, negative infinity, normalized floating point numbers, denormalized floating point numbers, positive 0 and negative 0.
In the second aspect of the present invention, it is preferable that verification of a rounding function specific value from a permutation and combination of all values of I, r, and s is performed as an incentive.
As a preference of the invention, let P be the infinite precision result before rounding, I be the least significant bit of the mantissa of P, r be the next bit of the LSB,
s is the result of all bit logic after r.
Preferably, in the third aspect, the overflow function point special value is used as an incentive for verification; and taking the boundary value of the corresponding data format as a starting point, selecting data in a left and right specified range of the boundary value, and constructing the overflow function point special value.
As a preferred aspect of the invention, the content one is sufficiently validated against invalid operations and divided by zero.
As a preferred aspect of the present invention, the second case is fully validated against four rounding modes and an inaccurate floating point exception.
As a preference of the present invention, the four rounding modes are the preferred "even" value when there are two closest class representation values; to the minus infinity; to the plus infinity; towards 0.
As a preferred aspect of the present invention, the third instance is sufficient to verify floating point exceptions such as overflow and underflow.
In conclusion, the invention has the following beneficial effects:
the data space is compressed according to the floating point data format, the rounding and overflow function points and the algorithm function points, and meanwhile, the points are used as centers to radiate to the periphery in a small range, so that the data selection has both typicality and generality, and the nearly infinite floating point verification data space is compressed into the limited verifiable data space.
Detailed Description
The present invention is described in further detail below.
The present embodiment is only for explaining the present invention, and it is not limited to the present invention, and those skilled in the art can make modifications of the present embodiment without inventive contribution as needed after reading the present specification, but all of them are protected by patent law within the scope of the claims of the present invention.
Embodiment 1, a floating point verification data space compression method, in the present technical solution, compression mainly comes from compression contents of three aspects.
The content one is as follows: and compressing according to a floating point data format.
The fundamental reason for the complexity of floating point operations comes from the complexity of the floating point data formats, each of which defines 8 floating point format specific values in addition to normal floating point numbers. The 8 floating-point format special values are: the number of static negatives, the number of notifications negatives, positive infinity, negative infinity, normalized floating point numbers, denormalized floating point numbers, positive 0 and negative 0, for a total of eight. Each operation requires special handling of operations involving these values.
For all operations, the combination of the special values in the floating-point format is used as excitation for verification, so that whether the processing of all the special values in the floating-point format is correct can be verified, and meanwhile, the conditions of all invalid operation exceptions, infinite operation, NaN operation and signs of signed zero operation results can be completely covered. Even if the multiply-add operation of three operands is performed, the total number of all the floating-point format special value combinations is not large, the operation can be completely traversed, the efficiency of the existing algorithm can be completely satisfied,
besides all operands are floating-point format special values, there are also cases where normal data is mixed with floating-point format special values. Considering sign bit, 8 floating-point format special values plus 2 normal data (positive/negative numbers), for multiply-add operation, the number of all input combinations is limited, even if the difference of single and double precision formats is considered, the total number is still not large, and all the combinations can be completely traversed.
And II, content II: compression is performed according to the rounding function point special value.
In the floating point standard, there are five floating point exceptions and four rounding directions. The five floating point exceptions are respectively: invalid operation, divide by zero, overflow, underflow and imprecision. And four rounds are: rounding nearby; to minus infinity (downwards); to the plus infinity (upwards); and to 0 (truncation).
In content one, with floating-point format special values, it is possible to fully verify for two contents out of five floating-point exceptions, respectively, invalid operation and divide by zero. But for the other 3 exceptions and 4 rounds, verification with floating point format special values is not possible. Thus, compression according to the rounding function point specific value of the content two needs to be used.
In the technical scheme, three numerical values, I, r and s, are required to be obtained.
In the following, let P be the infinite precision result before rounding.
I is the Least Significant Bit (LSB) of the mantissa of P, I being 52 th bit after the decimal point, for example, in double precision calculation.
r is the next bit of the LSB.
s is the result of all bits "logical OR" (OR) after r.
Through research, the applicant finds that three exceptions and four rounding modes which cannot be verified in the content I are closely related to intermediate results of the operations. Referring to table 1, table 1 reflects rounding in different cases. "AND" in table 1 is a logical AND.
TABLE 1 Overflow boundary rounding
If r or s is 1, the final result is not exact; the order of P after rounding may be increased by 1, and the final result may have order overflow or underflow (see Table 1, where MAX and MIN are the maximum normal floating point number and the minimum normal floating point number, respectively, that can be represented by the corresponding data format; and for double precision floating point numbers, 1ulp is the minus 52 th power of 2).
In this case, I, r, and s have a very important influence on rounding and verification of inaccurate results, and can be regarded as "function points". I. And r and s are arranged and combined into 3 powers of 2, and are 8 types in total, the number and the corresponding workload are not large in the test process, and the test process can be completely traversed, so that source operands (called 'rounding function point special values') capable of realizing the function point scenes are constructed and used as excitation for verification, and therefore the completeness and completeness of rounding processing and verification of inaccurate results are guaranteed.
By the compression processing of the content one and the content two, the verification of three of the four rounding modes and the five floating point exceptions is already satisfied, and the remaining two, namely the overflow and underflow floating point exceptions, cannot be sufficiently verified.
And thirdly: and compressing according to the overflow function point special value.
For the overflow up and down of the level code, the verification is performed by the scheme described below.
There are eight cases in table 1, namely four rounding modes and the positive and negative of P, which together form eight cases, each with different overflow and underflow conditions. In this case, first, a boundary value is found, which is constant.
For example, for a single precision floating point format, the boundary values are as follows:
+MAX_S:0x7f7f_ffff
-MAX_S:0xff7f_ffff
+MIN_S:0x0080_0000
-MIN_S:0x8080_0000
for another example, for a double precision floating point format, the boundary values are as follows:
+MAX_D:0x7fef_ffff_ffff_ffff
-MAX_D:0xff7f_ffff_ffff_ffff
+MIN_D:0x0010_0000_0000_0000
-MIN_D:0x8010_0000_0000_0000
then, by taking the boundary value of the corresponding data format as a starting point and selecting some points (for example, two points are taken for the left and the right) around the points, a source operand capable of realizing the scenes of the function points is constructed, which is called as an overflow function point special value, and is used as an excitation for verification, so that the sufficiency and completeness of the verification of the up-and-down overflow can be ensured.
All cases include five floating point exceptions and four rounding cases, and for each floating point operation, data space compression is performed according to the three points, and small-range radiation is performed around the points, so that data selection has both typicality and generality, nearly infinite floating point verification data space can be compressed into limited verifiable data space, and the completeness and completeness of verification are guaranteed. The near infinite floating point validation data space is compressed into a finite verifiable data space. Practice has proven that this method is effective.
Claims (9)
1. The floating point verification data space compression method is characterized in that the data space compression is carried out on the following three contents: the content one is as follows: compressing according to the floating point data format; and II, content II: compressing according to the special value of the rounding function point; and thirdly: compressing according to the overflow function point special value; in the first content, the permutation and combination of various floating-point format special values is verified as motivational content.
2. The floating point validation data space compression method of claim 1, wherein: the floating point format special values are eight, namely static nonnumbers, notified nonnumbers, positive infinity, negative infinity, normalized floating point numbers, denormalized floating point numbers, positive 0 and negative 0.
3. The floating point validation data space compression method of claim 1, wherein: in the second case, it is necessary to verify as a stimulus the rounding function-specific values from the permutation combination of all values I, r, s.
4. The floating point validation data space compression method of claim 3, wherein: let P be the infinite precision result before rounding, I be the least significant bit of the mantissa of P, r be the next bit of the LSB,
s is the result of all bit logic after r.
5. The floating point validation data space compression method of claim 1, wherein: in the third content, verifying by using the overflow function point special value as an incentive; and taking the boundary value of the corresponding data format as a starting point, selecting data in a left and right specified range of the boundary value, and constructing the overflow function point special value.
6. The floating point validation data space compression method of claim 1, wherein: the content one is sufficiently validated for invalid operations and divided by zero.
7. The floating point validation data space compression method of claim 1, wherein: the second case is fully validated against four rounding modes and an imprecise floating point exception.
8. The floating point validation data space compression method of claim 7, wherein: four rounding modes are the first "even" value when there are two nearest class-expressed values; to the minus infinity; to the plus infinity; towards 0.
9. The floating point validation data space compression method of claim 1, wherein: the third content is fully validated against overflow and underflow floating point exceptions.
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