CN110795150A - 依dmb操作用加载/存储操作实施加载撷取/存储释放指令 - Google Patents

依dmb操作用加载/存储操作实施加载撷取/存储释放指令 Download PDF

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Publication number
CN110795150A
CN110795150A CN201910999320.5A CN201910999320A CN110795150A CN 110795150 A CN110795150 A CN 110795150A CN 201910999320 A CN201910999320 A CN 201910999320A CN 110795150 A CN110795150 A CN 110795150A
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China
Prior art keywords
store
processor
load
memory
instruction
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Pending
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CN201910999320.5A
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English (en)
Chinese (zh)
Inventor
M·阿什克拉夫特
C·纳尔逊
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MACOM Connectivity Solutions LLC
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Applied Micro Circuits Corp
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Priority to CN201910999320.5A priority Critical patent/CN110795150A/zh
Publication of CN110795150A publication Critical patent/CN110795150A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Stored Programmes (AREA)
CN201910999320.5A 2015-07-21 2015-07-21 依dmb操作用加载/存储操作实施加载撷取/存储释放指令 Pending CN110795150A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910999320.5A CN110795150A (zh) 2015-07-21 2015-07-21 依dmb操作用加载/存储操作实施加载撷取/存储释放指令

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201580082189.6A CN108139903B (zh) 2015-07-21 2015-07-21 依dmb操作用加载/存储操作实施加载撷取/存储释放指令
PCT/US2015/041322 WO2017014752A1 (en) 2015-07-21 2015-07-21 Implementation of load acquire/store release instructions using load/store operation with dmb operation
CN201910999320.5A CN110795150A (zh) 2015-07-21 2015-07-21 依dmb操作用加载/存储操作实施加载撷取/存储释放指令

Related Parent Applications (1)

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CN201580082189.6A Division CN108139903B (zh) 2015-07-21 2015-07-21 依dmb操作用加载/存储操作实施加载撷取/存储释放指令

Publications (1)

Publication Number Publication Date
CN110795150A true CN110795150A (zh) 2020-02-14

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CN201910999320.5A Pending CN110795150A (zh) 2015-07-21 2015-07-21 依dmb操作用加载/存储操作实施加载撷取/存储释放指令
CN201580082189.6A Expired - Fee Related CN108139903B (zh) 2015-07-21 2015-07-21 依dmb操作用加载/存储操作实施加载撷取/存储释放指令

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Country Status (4)

Country Link
EP (1) EP3326059A4 (https=)
JP (1) JP6739513B2 (https=)
CN (2) CN110795150A (https=)
WO (1) WO2017014752A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10417002B2 (en) 2017-10-06 2019-09-17 International Business Machines Corporation Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses
US10572256B2 (en) 2017-10-06 2020-02-25 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
US10606591B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
US10606590B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Effective address based load store unit in out of order processors
US10394558B2 (en) 2017-10-06 2019-08-27 International Business Machines Corporation Executing load-store operations without address translation hardware per load-store unit port
US11175924B2 (en) 2017-10-06 2021-11-16 International Business Machines Corporation Load-store unit with partitioned reorder queues with single cam port

Citations (4)

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JP2000181891A (ja) * 1998-12-18 2000-06-30 Hitachi Ltd 共有メモリアクセス順序保証方式
US20050273583A1 (en) * 2004-06-02 2005-12-08 Paul Caprioli Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor
CN101828173A (zh) * 2007-10-18 2010-09-08 Nxp股份有限公司 具有多个处理器、缓存电路和共享存储器的数据处理系统
US20150046652A1 (en) * 2013-08-07 2015-02-12 Advanced Micro Devices, Inc. Write combining cache microarchitecture for synchronization events

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JPH07302200A (ja) * 1994-04-28 1995-11-14 Hewlett Packard Co <Hp> 順次付けロード動作および順序付け記憶動作を強制する命令を有するコンピュータのロード命令方法。
US6678810B1 (en) * 1999-12-30 2004-01-13 Intel Corporation MFENCE and LFENCE micro-architectural implementation method and system
US7552317B2 (en) * 2004-05-04 2009-06-23 Sun Microsystems, Inc. Methods and systems for grouping instructions using memory barrier instructions
US7725618B2 (en) * 2004-07-29 2010-05-25 International Business Machines Corporation Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment
US8060482B2 (en) * 2006-12-28 2011-11-15 Intel Corporation Efficient and consistent software transactional memory
GB2461716A (en) * 2008-07-09 2010-01-13 Advanced Risc Mach Ltd Monitoring circuitry for monitoring accesses to addressable locations in data processing apparatus that occur between the start and end events.
US8997103B2 (en) * 2009-09-25 2015-03-31 Nvidia Corporation N-way memory barrier operation coalescing
US8935513B2 (en) * 2012-02-08 2015-01-13 International Business Machines Corporation Processor performance improvement for instruction sequences that include barrier instructions
US9218289B2 (en) * 2012-08-06 2015-12-22 Qualcomm Incorporated Multi-core compute cache coherency with a release consistency memory ordering model
US9582276B2 (en) * 2012-09-27 2017-02-28 Apple Inc. Processor and method for implementing barrier operation using speculative and architectural color values
US9442755B2 (en) * 2013-03-15 2016-09-13 Nvidia Corporation System and method for hardware scheduling of indexed barriers
US9396112B2 (en) * 2013-08-26 2016-07-19 Advanced Micro Devices, Inc. Hierarchical write-combining cache coherence

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
JP2000181891A (ja) * 1998-12-18 2000-06-30 Hitachi Ltd 共有メモリアクセス順序保証方式
US20050273583A1 (en) * 2004-06-02 2005-12-08 Paul Caprioli Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor
CN101828173A (zh) * 2007-10-18 2010-09-08 Nxp股份有限公司 具有多个处理器、缓存电路和共享存储器的数据处理系统
US20150046652A1 (en) * 2013-08-07 2015-02-12 Advanced Micro Devices, Inc. Write combining cache microarchitecture for synchronization events

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JEFF PRESHING: ""Acquire and Release Semantics"", 《HTTPS://PRESHING.COM/20120913/ACQUIRE-AND-RELEASE-SEMANTICS/》, pages 1 - 18 *
LISA HIGHAM等: "Programmer-Centric Conditions for Itanium Memory Consistency", pages 58 *

Also Published As

Publication number Publication date
EP3326059A1 (en) 2018-05-30
JP6739513B2 (ja) 2020-08-12
WO2017014752A1 (en) 2017-01-26
CN108139903A (zh) 2018-06-08
CN108139903B (zh) 2019-11-15
EP3326059A4 (en) 2019-04-17
JP2018523235A (ja) 2018-08-16

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