CN110784211A - Phase-locked loop circuit adopting switched capacitor type loop filter - Google Patents
Phase-locked loop circuit adopting switched capacitor type loop filter Download PDFInfo
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- CN110784211A CN110784211A CN201910874456.3A CN201910874456A CN110784211A CN 110784211 A CN110784211 A CN 110784211A CN 201910874456 A CN201910874456 A CN 201910874456A CN 110784211 A CN110784211 A CN 110784211A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/083—Details of the phase-locked loop the reference signal being additionally directly applied to the generator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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Abstract
The invention discloses a phase-locked loop circuit adopting a switched capacitor type loop filter, which comprises a switched capacitor type loop filter circuit, wherein the switched capacitor type loop filter circuit comprises a loop filter capacitor and a pair of switched capacitor circuits; a pair of charge pumps in the same direction for providing input currents in the same direction to the switched capacitor loop filter circuit; and a reference clock for generating a clock control signal for switching control of a pair of the switched capacitor circuits; according to the phase-locked loop circuit, the traditional loop filter resistor is replaced by the switched capacitor circuit, the charge pump current control in the same direction is utilized, the matching of the charge pump is guaranteed, a zero point Wz is constructed through the charge pump current ratio and the switched capacitor circuit, the R and the C of the traditional loop filter are completely replaced, and the miniaturization of the loop filter is realized.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a phase-locked loop circuit adopting a switched capacitor type loop filter.
Background
A PLL (phase locked loop) circuit provides clocks for a plurality of communication chips, and a loop filter (LPF) is a core circuit of the PLL, as shown in fig. 1, a conventional loop filter is composed of a plurality of resistor capacitors (CN206498390U), a zero Wz composed of R002 and C002 affects a loop bandwidth of the PLL, R002 itself generates thermal noise and affects output noise of the PLL, and in a case where Wz is not changed, the larger the value of R002 is, the larger the noise contribution is, the lower the noise performance of the PLL is, but C002 can be reduced in equal proportion, thereby saving a chip area; conversely, if the value of R002 is smaller, the noise contribution is small, and the noise performance of the PLL is good, but C002 needs to be proportionally larger, so that the chip area is large, and there is no cost advantage. For the above reasons, the loop filter is usually the most area-consuming module in the pll circuit, and therefore, if the area of the loop filter can be reduced, a very good cost advantage can be obtained.
As shown in fig. 2, patent 1 (No. CN206498390U) utilizes two proportional Charge Pumps (CP), denoted by 100 and 200, to inject current into LPF at the same time, so as to multiply the equivalent capacitance of C001 by a factor equal to the ratio of the two charge pump currents; however, this method has two disadvantages, one is that the resistor R001 still exists and can contribute to noise, and the current directions of the two charge pumps are opposite, and the matching accuracy between the charge pumps is difficult to guarantee. As shown in fig. 3, patent 2 (publication No. CN 104052470 a) does not need two charge pumps, and switches control the on/off of C1 by a block (block) and a start signal generated by an UP/DN signal, and this control manner can also achieve equivalent multiplication of C1, and the multiplication effect is proportional to the blocking coefficient N; patent 2 has disadvantages, however, because the resistor R001 also contributes to noise.
Both the above-cited patent 1 and patent 2 achieve the effect of multiplying the capacitance in the loop filter by the inventive invention, but both have the drawbacks as described above.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a phase-locked loop circuit adopting a switched capacitor type loop filter, wherein the phase-locked loop circuit constructs an equivalent zero point Wz by combining a charge pump in the same direction with the switched capacitor type loop filter, replaces a general loop filter framework, and finally realizes the low noise and miniaturization of the loop filter.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a phase-locked loop circuit employing a switched-capacitor loop filter, the phase-locked loop circuit comprising: a switched-capacitor loop-filter circuit, wherein the switched-capacitor loop-filter circuit includes a loop-filter capacitor and a pair of switched-capacitor circuits; a pair of charge pumps in the same direction for providing input currents in the same direction to the switched capacitor loop filter circuit; and a reference clock for generating a clock control signal to switch control a pair of the switched capacitor circuits.
Furthermore, each switched capacitor circuit comprises a switched capacitor, wherein one end of each switched capacitor is connected with one charge pump in the same direction, and the other end of each switched capacitor is connected with the other charge pump in the same direction and is controlled by a switching clock signal of the reference clock.
Further, the reference clock comprises four first, second, third and fourth phase clock switches controlled by a phase clock, wherein the first, second, third and fourth phase clock switches are respectively disposed on the switch capacitor and used for controlling the coupling of the charge pump with the switch capacitor and the loop filter capacitor.
Further, the capacitance value of the switch capacitor is less than 1/5 of the capacitance value of the loop filter capacitor.
Further, the current ratio between a pair of the charge pumps in the same direction is N, wherein N is any positive integer.
Compared with the prior art, the scheme has the beneficial technical effects that: according to the phase-locked loop circuit, the traditional loop filter resistor is replaced by the switched capacitor circuit, the charge pump current control in the same direction is utilized, the matching of the charge pump is guaranteed, a zero point Wz is constructed through the charge pump current ratio and the switched capacitor circuit, the R and the C of the traditional loop filter are completely replaced, and the miniaturization of the loop filter is realized.
Drawings
Fig. 1 is a schematic diagram of a conventional pll circuit structure.
Fig. 2 is a schematic structural diagram of a conventional architecture for implementing a loop filter by using a dual charge pump.
Fig. 3 is a schematic diagram of a conventional structure for implementing a loop filter.
Fig. 4 is a schematic diagram of the overall structure of the phase-locked loop in this embodiment.
Fig. 5 is a schematic diagram of the structure of the pll filter in this embodiment.
Fig. 6 is a waveform diagram of a control signal in the present embodiment.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
The scheme aims at solving the problems that the existing loop filter circuit cannot well solve the miniaturization of the loop filter and the generated noise, and further provides the phase-locked loop circuit adopting the switched capacitor loop filter.
Referring to fig. 4 to 6, the pll circuit using a switched capacitor loop filter in the present embodiment includes a switched capacitor loop filter circuit, a pair of charge pumps in the same direction, and a reference clock, wherein the charge pumps in the same direction are connected to the switched capacitor loop filter circuit and are used for providing current Q flowing in the same direction to the switched capacitor loop filter circuit
iAnd Q
pAs input to the loop filter; switched capacitor loop filters employ a pair of switched capacitor circuits and a loop filter capacitor C1 in place of a conventional passive resistor, while generating a multiphase clock pair by using a reference clockAnd controlling the switch capacitor circuit to construct an equivalent zero point Wz so as to finally realize low noise and miniaturization of the loop filter.
Specifically, referring to fig. 5, each of the switched capacitor circuits in this embodiment includes a switched capacitor C2, wherein each switched capacitor C2 has one end connected to a co-directional charge pump Q1 and another end connected to another co-directional charge pump Q2 and controlled by a clock-referenced switched clock signal. The reference clock in this embodiment has four first clock phase switches CK1, second clock phase switches CK2, third clock phase switches CK1a and fourth clock phase switches CK2a controlled by phase clocks, wherein the first clock phase switches CK1, the second clock phase switches CK2, the third clock phase switches CK1a and the fourth clock phase switches CK2a are respectively disposed on the switched capacitor C2, and are used for controlling the coupling of the charge pumps Q1 and Q2 with the switched capacitor and the loop filter capacitor, that is, the coupling of the currents output by the charge pumps Q1 and Q2 with the capacitors C2 and C1 is realized by the four clock phase switches CK1, CK2, CK1a and CK2 a.
Referring to fig. 5, if the charge pump CP1 outputs Qi, the charge pump CP2 outputs Qp, and the current ratio between CP2 and CP1 is N (any positive integer), the transfer function of the loop filter can be derived as follows according to the switched capacitor circuit structure of the loop filter:
h (S) (N × T + S +1)/S × C1, where T is the clock period CK1/CK2 and S is laplace operator;
the zero Wz 1/N/T1/N Fck of the loop filter can be derived from the above formula, where Fck is the clock frequency of CK1/CK 2; it can be seen that through the combination of the charge pump in the same direction and the switched capacitor loop filter, a zero Wz unrelated to the passive devices R and C can be obtained, and the position of the zero is inversely proportional to the current ratio N of the two charge pumps and proportional to the switching frequency Fck, and the switching clock is generated by the reference clock CKREF of the PLL (phase locked loop circuit) in fig. 5, in the example of the present invention, the selected CKREF is 1/2 times, and the CKREF frequency can be flexibly set to 1/M times in practical application.
In summary, in the phase-locked loop circuit in the present embodiment, the switched capacitor circuit replaces the conventional loop filter resistor, and the charge pump current control in the same direction is used, so that the matching of the charge pump is ensured, and a zero Wz is constructed by the charge pump current ratio and the switched capacitor circuit, so as to completely replace R and C of the conventional loop filter, thereby achieving the miniaturization of the loop filter.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.
Claims (5)
1. A phase-locked loop circuit employing a switched-capacitor loop filter, the phase-locked loop circuit comprising:
a switched-capacitor loop-filter circuit, wherein the switched-capacitor loop-filter circuit includes a loop-filter capacitor and a pair of switched-capacitor circuits;
a pair of charge pumps in the same direction for providing input currents in the same direction to the switched capacitor loop filter circuit;
and a reference clock for generating a clock control signal to switch control a pair of the switched capacitor circuits.
2. A phase locked loop circuit using a switched capacitor loop filter according to claim 1, wherein: each switched capacitor circuit comprises a switched capacitor, wherein one end of each switched capacitor is connected with one charge pump in the same direction, and the other end of each switched capacitor is connected with the other charge pump in the same direction and is controlled by a switching clock signal of the reference clock.
3. A phase locked loop circuit using a switched capacitor loop filter according to claim 2, wherein: the reference clock comprises four first clock phase switches, four second phase clock switches, four third phase clock switches and four fourth phase clock switches which are controlled by phase clocks, wherein the first clock phase switches, the second phase clock switches, the third phase clock switches and the fourth phase clock switches are respectively arranged on the switch capacitors and are used for controlling the coupling on-off of the charge pump, the switch capacitors and the loop filter capacitors.
4. A phase locked loop circuit using a switched capacitor loop filter according to claim 2, wherein: the capacitance value of the switch capacitor is less than 1/5 of the capacitance value of the loop filter capacitor.
5. A phase locked loop circuit using a switched capacitor loop filter according to any one of claims 1 to 4, wherein: the current ratio between a pair of the charge pumps in the same direction is N, wherein N is any positive integer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910874456.3A CN110784211A (en) | 2019-09-17 | 2019-09-17 | Phase-locked loop circuit adopting switched capacitor type loop filter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910874456.3A CN110784211A (en) | 2019-09-17 | 2019-09-17 | Phase-locked loop circuit adopting switched capacitor type loop filter |
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| Publication Number | Publication Date |
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| CN110784211A true CN110784211A (en) | 2020-02-11 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0460274A1 (en) * | 1990-06-08 | 1991-12-11 | Siemens Aktiengesellschaft | Phase comparison circuit and method therefor |
| CN102360565A (en) * | 2011-08-26 | 2012-02-22 | 北京兆易创新科技有限公司 | Charge pump system and method for generating reading and writing operation word line voltage by aid of same and memory |
| CN107634759A (en) * | 2017-09-15 | 2018-01-26 | 北京华大九天软件有限公司 | A kind of phase-locked loop circuit of adaptive loop circuit bandwidth |
| CN107809240A (en) * | 2016-09-08 | 2018-03-16 | 中芯国际集成电路制造(上海)有限公司 | Loop filter and phase-locked loop circuit for phase-locked loop circuit |
| CN210274030U (en) * | 2019-09-07 | 2020-04-07 | 佛山市众信邦电子有限公司 | Phase-locked loop circuit adopting switched capacitor type loop filter |
-
2019
- 2019-09-17 CN CN201910874456.3A patent/CN110784211A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0460274A1 (en) * | 1990-06-08 | 1991-12-11 | Siemens Aktiengesellschaft | Phase comparison circuit and method therefor |
| CN102360565A (en) * | 2011-08-26 | 2012-02-22 | 北京兆易创新科技有限公司 | Charge pump system and method for generating reading and writing operation word line voltage by aid of same and memory |
| CN107809240A (en) * | 2016-09-08 | 2018-03-16 | 中芯国际集成电路制造(上海)有限公司 | Loop filter and phase-locked loop circuit for phase-locked loop circuit |
| CN107634759A (en) * | 2017-09-15 | 2018-01-26 | 北京华大九天软件有限公司 | A kind of phase-locked loop circuit of adaptive loop circuit bandwidth |
| CN210274030U (en) * | 2019-09-07 | 2020-04-07 | 佛山市众信邦电子有限公司 | Phase-locked loop circuit adopting switched capacitor type loop filter |
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Application publication date: 20200211 |