CN110783345A - Display device - Google Patents

Display device Download PDF

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Publication number
CN110783345A
CN110783345A CN201910692763.XA CN201910692763A CN110783345A CN 110783345 A CN110783345 A CN 110783345A CN 201910692763 A CN201910692763 A CN 201910692763A CN 110783345 A CN110783345 A CN 110783345A
Authority
CN
China
Prior art keywords
display
region
layer
electrode
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910692763.XA
Other languages
Chinese (zh)
Inventor
李周禧
朴钟宇
崔荣太
赵大衍
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung Display Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to KR10-2018-0089621 priority Critical
Priority to KR1020180089621A priority patent/KR20200014473A/en
Application filed by Samsung Display Co Ltd filed Critical Samsung Display Co Ltd
Publication of CN110783345A publication Critical patent/CN110783345A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266Details of drivers for scan electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays
    • H01L27/326Active matrix displays special geometry or disposition of pixel-elements
    • H01L27/3262Active matrix displays special geometry or disposition of pixel-elements of TFT
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays
    • H01L27/326Active matrix displays special geometry or disposition of pixel-elements
    • H01L27/3265Active matrix displays special geometry or disposition of pixel-elements of capacitor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays
    • H01L27/3276Wiring lines
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L51/00Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
    • H01L51/50Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for light emission, e.g. organic light emitting diodes [OLED] or polymer light emitting devices [PLED]
    • H01L51/52Details of devices
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0819Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202Addressing of scan or signal lines
    • G09G2310/0221Addressing of scan or signal lines with use of split matrices
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2251/00Indexing scheme relating to organic semiconductor devices covered by group H01L51/00
    • H01L2251/50Organic light emitting devices
    • H01L2251/53Structure
    • H01L2251/5338Flexible OLED
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/32Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes [OLED]
    • H01L27/3241Matrix-type displays
    • H01L27/3244Active matrix displays
    • H01L27/3272Shielding, e.g. of TFT
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L51/00Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
    • H01L51/0096Substrates
    • H01L51/0097Substrates flexible substrates
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/549Organic PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

A display device is provided. The display device includes: a substrate; a lower conductive layer including a protective pattern and an auxiliary conductive pattern on the substrate; a buffer layer on the lower conductive layer; an active pattern on the buffer layer and overlapping the protection pattern; a first insulating layer on the active pattern; and a first conductive layer on the first insulating layer, the first conductive layer including a gate electrode overlapping the active pattern and a load matching line overlapping the auxiliary conductive pattern.

Description

Display device
Technical Field
Exemplary embodiments of the inventive concepts relate to a display apparatus.
Background
Recently, a display apparatus having a light weight and a small size has been manufactured. Cathode Ray Tube (CRT) display devices have been used due to performance and competitive price. However, the CRT display device has a weakness in size or portability. Accordingly, display devices such as plasma display devices, liquid crystal display devices, and organic light emitting display devices have been highly valued for their small size, light weight, and low power consumption.
Display devices have been developed having display areas with different sized areas beyond a simple rectangular shape. However, for each region having a different size, a problem of luminance deviation and deterioration of display quality due to structural reasons, manufacturing reasons, and the like has been found.
Disclosure of Invention
According to an aspect of one or more exemplary embodiments of the inventive concept, a display apparatus having regions including regions of different sizes has improved manufacturing yield and improved luminance uniformity regardless of the regions.
According to one or more exemplary embodiments of the inventive concepts, a display apparatus includes: a substrate; a lower conductive layer including a protective pattern and an auxiliary conductive pattern on the substrate; a buffer layer on the lower conductive layer; an active pattern on the buffer layer and overlapping the protection pattern; a first insulating layer on the active pattern; and a first conductive layer on the first insulating layer, the first conductive layer including a gate electrode overlapping the active pattern and a load matching line overlapping the auxiliary conductive pattern.
In an exemplary embodiment, the display apparatus further includes: an interlayer insulating layer on the first conductive layer; and a second conductive layer on the interlayer insulating layer, the second conductive layer including a load matching electrode overlapping the load matching line.
In an exemplary embodiment, the first conductive layer may further include a connection line spaced apart from the load match line.
In an exemplary embodiment, the connection line may be electrically connected to the auxiliary conductive pattern through a first contact hole formed through the first insulating layer and the buffer layer, and electrically connected to the load matching electrode through a second contact hole formed through the interlayer insulating layer.
In an exemplary embodiment, the first contact hole and the second contact hole may not overlap each other.
In an exemplary embodiment, the substrate may include: a first pixel region; a second pixel region connected to the first pixel region and having a size smaller than that of the first pixel region; a first peripheral region serving as a non-display region and adjacent to the first pixel region; and a second peripheral region serving as a non-display region and adjacent to the second pixel region. The load match line may include a plurality of load match lines corresponding to the gate lines in the second pixel region. The connection line may include a plurality of connection lines.
In an exemplary embodiment, the auxiliary conductive pattern, the load match line, and the layer between the auxiliary conductive pattern and the load match line may form a first load match capacitor. The load match line, the load match electrode, and the layer between the load match line and the load match electrode may form a second load match capacitor.
In an exemplary embodiment, the first conductive layer may further include a first storage electrode. The display device may further include: a second insulating layer on the first conductive layer; and a third conductive layer on the second insulating layer, the third conductive layer including a second storage electrode overlapping the first storage electrode.
In an exemplary embodiment, the display apparatus may further include: a third insulating layer on the first conductive layer; and a light emitting structure on the third insulating layer, the light emitting structure including a first electrode, a second electrode facing the first electrode, and a light emitting layer between the first electrode and the second electrode.
In an exemplary embodiment, the second electrode may overlap the load matching electrode.
In an exemplary embodiment, a second power source (ELVSS) may be applied to the second electrode. A first power (ELVDD) may be applied to the auxiliary conductive pattern and the load matching electrode.
In an exemplary embodiment, the substrate may include: a first pixel region; a second pixel region connected to the first pixel region and having a size smaller than that of the first pixel region; a first peripheral region serving as a non-display region and adjacent to the first pixel region; and a second peripheral region serving as a non-display region and adjacent to the second pixel region. The auxiliary conductive pattern and the load matching line may be located in the second peripheral region. The active pattern and the gate electrode may constitute a thin film transistor. The thin film transistor may be located in the second pixel region.
In an exemplary embodiment, the second pixel region may be disposed adjacent to an upper side of the first pixel region, and the second peripheral region may include an upper second peripheral region positioned adjacent to the upper side of the second pixel region. The load match line may be located in the upper second peripheral region.
In an exemplary embodiment, the first conductive layer may further include a gate line. The load match line may be physically connected to the gate line.
In an exemplary embodiment, the substrate may further include: a third pixel region separated from the second pixel region, connected to the first pixel region, and having a size smaller than that of the first pixel region; and a third peripheral region as a non-display region adjacent to the third pixel region. The notch may be formed between the second pixel region and the third pixel region.
In an exemplary embodiment, the substrate may include at least one polyimide layer and at least one barrier layer.
In an exemplary embodiment, the lower conductive layer may further include molybdenum (Mo).
In an exemplary embodiment, the auxiliary conductive pattern may include a slit.
According to one or more exemplary embodiments of the inventive concepts, a display apparatus includes: a first region; a second region adjacent to the first region and having a size smaller than that of the first region; and a third region adjacent to the first region and spaced apart from the second region to form a recess between the second region and the third region. The display device further includes: a gate line in the second region; a first load matching capacitor electrically connected to the gate line; and a second load matching capacitor electrically connected to the gate line and overlapping the first load matching capacitor.
In an exemplary embodiment, the display apparatus further includes: a substrate; an auxiliary conductive pattern on the substrate; a load matching line on the auxiliary conductive pattern and formed of the same layer as the gate line; and a load matching electrode on the load matching line. The first load matching capacitor may be formed by the auxiliary conductive pattern, the load matching line, and an insulating layer between the auxiliary conductive pattern and the load matching line. The second load matching capacitor may be formed by the load match line, the load match electrode, and an insulating layer between the load match line and the load match electrode.
According to one or more exemplary embodiments of the present inventive concept, a display apparatus includes: a substrate; a lower conductive layer including a protective pattern and an auxiliary conductive pattern on the substrate; a buffer layer on the lower conductive layer; an active pattern on the buffer layer and overlapping the protective pattern; a first insulating layer on the active pattern; and a first conductive pattern on the first insulating layer, the first conductive pattern including a gate electrode overlapping the active pattern and a load matching line overlapping the auxiliary conductive pattern. Accordingly, since the scan line and the load matching line are physically connected and are not connected to each other through the contact hole or the like in the manufacturing process, use, or the like of the display device, it is possible to provide a structure that minimizes or reduces characteristic variation and damage of the thin film transistor caused by static electricity flowing into the active pattern through the contact hole.
In addition, since the load matching capacitor is formed by using the lower conductive layer, the possibility of short-circuiting with the gate conductive layer is reduced as compared with the case where the load matching capacitor is formed using the active layer.
In addition, since the thin film transistor can be protected by the protection pattern, display quality of the display device can be improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
Drawings
The above and other features of the inventive concept will become more apparent by describing in further detail some exemplary embodiments thereof with reference to the attached drawings, in which:
fig. 1 is a plan view illustrating a display apparatus according to an exemplary embodiment of the inventive concept;
fig. 2 is a block diagram of a pixel and a driver according to an example embodiment of the inventive concepts;
fig. 3 is a view illustrating an embodiment of the first pixel illustrated in fig. 2;
fig. 4 is a sectional view showing a display device in a display area;
fig. 5 is a plan view illustrating a region "a" of fig. 1;
FIG. 6 is a cross-sectional view taken along line I-I' of FIG. 5;
fig. 7A, 7B, 7C, and 7D are plan views illustrating an auxiliary conductive pattern, a first contact hole, a first gate conductive layer, and a second contact hole of the display device of fig. 5 and 6, respectively;
fig. 8 is a plan view illustrating an auxiliary conductive pattern of a display device according to another embodiment of the present invention;
fig. 9 is a plan view illustrating a first gate conductive layer of a display device according to another embodiment of the present invention;
FIG. 10 is a block diagram illustrating an electronic device according to an example embodiment;
fig. 11A is a diagram showing an example in which the electronic apparatus of fig. 10 is implemented as a television set; and
fig. 11B is a diagram illustrating an example in which the electronic device of fig. 10 is implemented as a smartphone.
Detailed Description
The inventive concept will be explained herein in further detail with reference to some exemplary embodiments and the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may take different forms and should not be construed as limited to the description set forth herein. Accordingly, the embodiments are described below only by referring to the drawings to explain aspects of the description. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When a statement such as "at least one of … …" follows a list of elements, the entire list of elements is modified rather than modifying individual elements within the list.
It will be understood that, although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It will be understood that the terms "comprises," "comprising," and "having," as used herein, specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.
The size and thickness of components in the drawings may be exaggerated for convenience of description. In other words, since the size and thickness of components in the drawings may be arbitrarily illustrated for convenience of description, the following embodiments are not limited thereto.
While certain embodiments may be practiced differently, the specific process sequence may be performed in an order different than that described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described.
It will be understood that when a layer, region or component is referred to as being "connected to" another layer, region or component, it can be directly connected to the other layer, region or component or be indirectly connected to the other layer, region or component with one or more intervening layers, regions or components interposed therebetween. For example, it will be understood that when a layer, region or component is referred to as being "electrically connected to" another layer, region or component, it can be directly electrically connected to the other layer, region or component, or can be indirectly electrically connected to the other layer, region or component with one or more intervening layers, regions or components interposed therebetween.
Spatially relative terms, such as "below … …," "below … …," "below," "above … …," "above," and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures for ease of description. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both an orientation of above and below. The device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments of the inventive concepts belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a plan view illustrating a display apparatus according to an exemplary embodiment of the inventive concept.
Referring to fig. 1, the display device may include a substrate 100, pixels PXL1, PXL2, and PXL3 (herein referred to as PXL) disposed on the substrate 100, a driving part (not shown) disposed on the substrate 100 and driving the pixels, a power supply unit for supplying power to the pixels, and a wiring part connecting the pixels to the driving part.
The substrate 100 may include a plurality of regions. The at least two regions may have different sizes. For example, the substrate 100 may include three regions, i.e., a first region a1, a second region a2, and a third region A3.
Each of the first, second, and third regions a1, a2, and A3 may have a different shape. For example, each of the first, second, and third regions a1, a2, and A3 may have a shape of any of a closed polygon including straight sides, a circle or ellipse including curved sides, or the like, and a semicircle or semi-ellipse including straight sides and curved sides.
In some embodiments, each of the first, second, and third regions a1, a2, and A3 may have a substantially rectangular shape, and corner portions may have a rounded shape.
The first, second, and third areas a1, a2, and A3 may have pixel areas PXA1, PXA2, and PXA3 (referred to herein as PXA) and peripheral areas PPA1, PPA2, and PPA3 (referred to herein as PPA), respectively. The pixel area PXA is an area in which pixels for displaying an image are disposed. Each pixel will be described later.
In some embodiments, each of the first, second, and third pixel areas PXA1, PXA2, and PXA3 may correspond to the shape of the first, second, and third areas a1, a2, and A3, respectively.
The peripheral region PPA is a region in which pixels are not set, and is a non-display region in which an image is not displayed. A driving part for driving the pixels, a power supply unit for applying power to the pixels, and a wiring part for connecting the pixels to the driving part may be provided in the peripheral region PPA. The peripheral area PPA may correspond to a bezel of the display device, and a width of the bezel may be determined according to the width of the peripheral area.
The first region a1, the second region a2, and the third region A3 will be described here.
The first region a1 may have the largest area among the first region a1, the second region a2, and the third region A3. The first area a1 may have a first pixel area PXA1 as a display area and a first peripheral area PPA1 surrounding at least a portion of the first pixel area PXA1 and being a non-display area.
The first pixel area PXA1 may be disposed in a shape corresponding to that of the first area a 1.
The first peripheral area PPA1 may be disposed on at least one side of the first pixel area PXA 1. In some example embodiments, the first peripheral area PPA1 may surround the boundary of the first pixel area PXA1, and may be disposed at a position other than the positions where the second area a2 and the third area A3, which will be described later, are located. In some embodiments, the first peripheral region PPA1 may include a horizontal portion extending in a width direction and a vertical portion extending in a longitudinal direction. The vertical portion of the first peripheral area PPA1 may be provided as a pair of partition portions in the width direction of the first pixel area PXA 1. In an embodiment, among the pair of partition portions, the partition portion located at the opposite left side in the first direction DR1 may be referred to as a left vertical portion, and the partition portion located at the opposite right side may be referred to as a right vertical portion.
The second region a2 may have a size smaller than that of the first region a 1. The second area a2 may have a second pixel area PXA2 as a display area and a second peripheral area PPA2 surrounding at least a portion of the second pixel area PXA2 and being a non-display area. The second peripheral area PPA2 may include an upper second peripheral area PPA2U disposed on an upper side (a direction opposite to the second direction DR 2) of the second pixel area PXA2 and right and left second peripheral areas PPA2R and PPA2L disposed at right and left sides (the first direction DR1 and a direction opposite to the first direction DR 1) of the second pixel area PXA2, respectively.
The second pixel area PXA2 may be disposed in a shape corresponding to that of the second area a 2. The second pixel area PXA2 may be disposed to protrude from the first pixel area PXA1 and may be directly connected to the first pixel area PXA 1. In other words, an edge of the second pixel area PXA2 closest to the first pixel area PXA1 may coincide with an edge of the first pixel area PXA 1.
The second peripheral area PPA2 may be disposed on at least one side of the second pixel area PXA 2. In some example embodiments, the second peripheral area PPA2 may surround the second pixel area PXA2 and may not be disposed at a position where the first pixel area PXA1 and the second pixel area PXA2 are connected. In some example embodiments, the second peripheral region PPA2 may also include an upper second peripheral region PPA2U extending in the width direction and left and right second peripheral regions PPA2L and PPA2R extending in the longitudinal direction.
The third region A3 may have a size smaller than that of the first region a 1. In an embodiment, the third region A3 may have the same size as the second region a 2. The third area a3 may have a third pixel area PXA3 in which an image is displayed and a third peripheral area PPA3 surrounding at least a portion of the third pixel area PXA3 and being a non-display area. Similar to the second peripheral area PPA2, the third peripheral area PPA3 may also include an upper third peripheral area PPA3U disposed on an upper side (in a direction opposite to the second direction DR 2) of the third pixel area PXA3 and right and left third peripheral areas PPA3R and PPA3L disposed on right and left sides (in the first direction DR1 and a direction opposite to the first direction DR 1) of the third pixel area PXA 3.
The third pixel area PXA3 may be disposed in a shape corresponding to that of the third area A3.
The third pixel area PXA3 may be disposed to protrude from the first pixel area PXA1 and may be directly connected to the first pixel area PXA 1. In other words, an edge of the third pixel area PXA3 closest to the first pixel area PXA1 may coincide with an edge of the first pixel area PXA 1.
The third peripheral area PPA3 may be disposed on at least one side of the third pixel area PXA 3. In some example embodiments, the third peripheral area PPA3 may surround the third pixel area PXA3 and may not be disposed at a position where the first pixel area PXA1 and the third pixel area PXA3 are connected. In some example embodiments, the third peripheral region PPA3 may also include an upper third peripheral region PPA3U extending in the width direction and left and right third peripheral regions PPA3L and PPA3R extending in the longitudinal direction.
In some example embodiments, the third region A3 may have a shape linearly symmetrical to the shape of the second region a2, based on the center line of the first region a 1. In this case, the arrangement relationship of each component provided in the third region A3 may be substantially the same as that of each component provided in the second region a2, except for some wirings.
Accordingly, the substrate 100 may have a shape in which the second and third regions a2 and A3 protrude from the first region a1 in a direction opposite to the second direction DR 2. In an embodiment, the second and third regions a2 and A3 are separated, and the substrate 100 may have a concave shape between the second and third regions a2 and A3. Accordingly, the substrate 100 may have a notch NH disposed between the second and third regions a2 and A3.
In some example embodiments, the left and right vertical portions of the first peripheral region PPA1 may be connected to the left second peripheral region PPA2L of the second peripheral region PPA2 and the right third peripheral region PPA3R of the third peripheral region PPA3, respectively.
In some example embodiments, the second peripheral region PPA2 and the third peripheral region PPA3 may be connected by a notched peripheral region NPA. For example, the notch peripheral area NPA may be disposed between the second pixel area PXA2 and the third pixel area PXA3 to connect the second peripheral area PPA2 to the third peripheral area PPA 3. Accordingly, the recess peripheral area NPA may be disposed on a side of the first pixel area PXA1 between the second area a2 and the third area A3.
The pixels may be disposed in the pixel area PXA on the substrate 100, i.e., in the first, second, and third pixel areas PXA1, PXA2, and PXA 3. Each pixel may be set as a minimum unit for displaying a plurality of images. A pixel may include a display element that emits colored light. For example, the display element may be a liquid crystal display device (LCD device), an electrophoretic display device (EPD device), an electrowetting display device (EWD device), or an organic light emitting diode device (OLED device). Hereinafter, for convenience of explanation, an organic light emitting diode device will be described as an example of the display element.
Each pixel may emit light of one color of red, green, and blue, but is not limited thereto. For example, each pixel may emit light of a color such as cyan, magenta, yellow, and white.
The pixels may include first pixels PXL1 arranged in the first pixel area PXA1, second pixels PXL2 arranged in the second pixel area PXA2, and third pixels PXL3 arranged in the third pixel area PXA 3. In some example embodiments, the plurality of first, second, and third pixels PXL1, PXL2, and PXL3 may be arranged in a matrix form along rows extending in the first direction DR1 and columns extending in the second direction DR 2. However, the arrangement form of the first, second, and third pixels PXL1, PXL2, and PXL3 is not particularly limited and may be arranged in any of various forms. For example, the first pixels PXL1 may be arranged such that the first direction DR1 is a row direction, but the second pixels PXL2 may be arranged in another direction other than the first direction DR 1; for example, the direction inclined with respect to the first direction DR1 may be a row direction of the second pixels PXL 2. It should be noted that the third pixel PXL3 may be arranged in the same or different direction as the first pixel PXL1 and/or the second pixel PXL 2. Alternatively, in some example embodiments, the row direction may be the second direction DR2 and the column direction may be the first direction DR 1.
In the second and third areas a2 and A3, the number of the second pixels PXL2 and the number of the third pixels PXL3 may vary according to the rows. For example, in the second and third areas a2 and A3, the number of the second and third pixels PXL2 and PXL3 arranged in the row corresponding to the rounded corner may be smaller than the number of the second and third pixels PXL2 and PXL3 arranged in the row corresponding to the corner formed by the straight line. In addition, the number of the second pixels PXL2 and the number of the third pixels PXL3 arranged in a row may decrease as the row length becomes shorter.
The driving section may supply a signal to each pixel through the wiring section, thereby controlling driving of each pixel.
In an embodiment, the driving section may include a scan driver (not shown) for supplying a scan signal to each pixel along a scan line, an emission driver (not shown) for supplying an emission control signal to each pixel along an emission control line (hereinafter, may also be referred to as an "emission control line"), a data driver DDV for supplying a data signal to each pixel along a data line, and a timing controller (not shown). The timing controller may control the scan driver, the light emitting driver, and the data driver DDV.
In some example embodiments, the scan driver may include a first scan driver (SDV 1 of fig. 2) connected to the first pixel PXL1, a second scan driver (SDV 2 of fig. 2) connected to the second pixel PXL2, and a third scan driver (SDV 3 of fig. 2) connected to the third pixel PXL 3. In some example embodiments, the light emitting driver may include a first light emitting driver (EDV 1 of fig. 2) connected to the first pixel PXL1, a second light emitting driver (EDV 2 of fig. 2) connected to the second pixel PXL2, and a third light emitting driver (EDV 3 of fig. 3) connected to the third pixel PXL 3.
The first scan driver SDV1 may be disposed on a vertical portion of the first peripheral region PPA 1. Since the vertical portion of the first peripheral area PPA1 is provided as a pair of partition portions in the width direction of the first pixel area PXA1, the first scan driver SDV1 may be provided on at least one of the vertical portions of the first peripheral area PPA 1. The first scan driver SDV1 may extend in the longitudinal direction of the first peripheral region PPA 1.
In a similar manner, the second scan driver SDV2 may be disposed in the second peripheral region PPA2, and the third scan driver SDV3 may be disposed in the third peripheral region PPA 3.
In some example embodiments, the scan driver may be directly mounted on the substrate 100. When the scan drivers are directly mounted on the substrate 100, they may be formed together in a process of forming the pixels. However, the position and method of setting the scan driver are not limited thereto. For example, the scan driver may be formed on a separate chip in the form of a chip on glass and disposed on the substrate 100, or may be mounted on a printed circuit board and connected to the substrate 100 through a connection member.
Similar to the first scan driver SDV1, the first light emitting driver EDV1 may also be disposed on a vertical portion of the first peripheral region PPA 1. The first light emitting driver EDV1 may be disposed on at least one of the vertical portions of the first peripheral region PPA 1. The first light emitting driver EDV1 may extend in the longitudinal direction of the first peripheral region PPA 1.
In a similar manner, the second light emission driver EDV2 may be disposed in the second peripheral region PPA2 and the third light emission driver EDV3 may be disposed in the third peripheral region PPA 3.
In some example embodiments, the light emission driver may be directly mounted on the substrate 100. When the light emission drivers are directly mounted on the substrate 100, they may be formed together in a process of forming a pixel. However, the position and method of disposing the light emission driver are not limited thereto. For example, the light emission driver may be formed on a separate chip in the form of a chip on glass and disposed on the substrate 100, or may be mounted on a printed circuit board and connected to the substrate 100 through a connection member.
In some example embodiments, the scan driver and the light emission driver may be disposed adjacent to each other and may be formed on only one of the vertical portions of the peripheral region PPA. However, the present invention is not limited thereto. The arrangement of the scan driver and the light emission driver may be changed in various ways.
The data driver DDV may be disposed on the first peripheral area PPA 1. Specifically, the data driver DDV may be disposed on the horizontal portion of the first peripheral region PPA 1. The data driver DDV may extend in the width direction of the first peripheral region PPA 1.
In some example embodiments, the positions of the scan driver, the light emitting driver, and/or the data driver DDV may be changed.
A timing controller (not shown) may be connected to the first, second, and third scan drivers SDV1, SDV2, and SDV3, the first, second, and third light-emitting drivers EDV1, EDV2, and EDV3, and the data driver DDV through wiring, and the position of the timing controller is not particularly limited. For example, the timing controller may be mounted on a printed circuit board, and may be connected to the first, second, and third scan drivers SDV1, SDV2, and SDV3, the first, second, and third light emitting drivers EDV1, EDV2, and EDV3, and the data driver DDV through a flexible circuit board. The printed circuit board may be disposed at any of various positions such as one side of the substrate 100 or a rear side of the substrate 100.
The power supply unit may include at least one power line ELVDD and ELVSS. For example, the power supply unit may include a first power line ELVDD (hereinafter, also referred to as "first power source ELVDD") to which the first power supply voltage is applied and a second power line ELVSS (hereinafter, also referred to as "second power supply ELVSS") to which the second power supply voltage is applied (see fig. 2). The first power line ELVDD and the second power line ELVSS may supply power to the first pixel PXL1, the second pixel PXL2, and the third pixel PXL 3.
The first power line ELVDD may be disposed to correspond to one side of the first pixel area PXA 1. For example, the first power line ELVDD may be positioned in a region of the data driver DDV in which the first peripheral region PPA1 is disposed. In addition, the first power line ELVDD may extend in the width direction of the first pixel area PXA 1.
In addition, the first power supply line ELVDD may be disposed in the upper second and third peripheral regions PPA2U and PPA3U to extend in the first direction DR 1. The portion of the first power supply line ELVDD disposed in the upper second and third peripheral regions PPA2U and PPA3U may serve as a load matching electrode (refer to the LCE in fig. 6).
In the above example, it is assumed that the first power supply line ELVDD is arranged to correspond to one side of the first pixel region PXA1 in the first peripheral region PPA1, and the second power supply line ELVSS is arranged in the remaining peripheral region. However, the present invention is not limited thereto. For example, the first power line ELVDD and the second power line ELVSS may be arranged to surround the first pixel area PXA1, the second pixel area PXA2, and the third pixel area PXA 3.
The first power supply voltage applied to the first power supply line ELVDD may be higher than the second power supply voltage applied to the second power supply line ELVSS.
Here, due to the difference in structure, the scan lines GL disposed in the second pixel area PXA2 may have different electrical characteristics from those of the scan lines disposed in the first pixel area PXA 1. Therefore, a load deviation of the scanning line may occur. To compensate for this load deviation, a load match line LML (see fig. 5) may be formed in the second peripheral area PPA2 and connected to the scan line (e.g., gate line) GL of the second pixel area PXA 2. Although not shown, the scan lines disposed in the third pixel area PXA3 may have a structure similar to that of the scan line GL and the load matching line LML. For example, the scan line GL may be formed of a first gate conductive layer (refer to the description of fig. 6), and may extend through the right second peripheral region PPA2R to the load match line LML in the upper second peripheral region PPA2U in the first direction DR 1. Although two scan lines and two load match lines are illustrated in the drawings, a plurality of load match lines corresponding to the scan lines of the second pixel area PXA2 may be formed.
Although the load match lines are described only with respect to the scan lines in the drawings, the load match lines of similar concept may be applied to lines crossing the first direction DR1, for example, emission control lines.
Fig. 2 is a block diagram of a pixel and a driver according to an example embodiment of the inventive concepts.
Referring to fig. 1 and 2, the display device may include a pixel, a driving part, and a wiring part.
The pixels may include a first pixel PXL1, a second pixel PXL2, and a third pixel PXL 3. The driving part may include a first scan driver SDV1, second and third scan drivers SDV2 and SDV3, a first light emitting driver EDV1, second and third light emitting drivers EDV2 and EDV3, a data driver DDV, and a timing controller (or referred to as a "timing control unit") TC. In fig. 2, for convenience of explanation, positions of the first, second and third scan drivers SDV1, SDV2 and SDV3, the first, second and third light-emitting drivers EDV1, EDV2 and EDV3, and the data driver DDV and the timing controller TC are set, and when the display device is implemented, the first, second and third scan drivers SDV1, SDV2 and SDV3, the first, second and third light-emitting drivers EDV1, EDV2 and EDV3, and the data driver DDV and the timing controller TC may be disposed at other positions in the display device. For example, the data driver DDV may be disposed closer to the first region a1 than to the second and third regions a2 and A3, but is not limited thereto.
The wiring part may supply a signal of the driving part to each pixel, and may include a scan line, a data line, an emission control line, a power line, and an initialization power line (not shown).
The scan lines may include first scan lines S11 to S1n, second scan lines S21 and S22, and third scan lines S31 and S32 connected to the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3, respectively. The emission control lines may include first emission control lines E11 to E1n, second emission control lines E21 and E22, and third emission control lines E31 and E32 connected to the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3, respectively. The data lines D1 to Dm and the power supply line may be connected to the first, second, and third pixels PXL1, PXL2, and PXL 3.
The first pixels PXL1 may be positioned in the first pixel area PXA 1. The first pixel PXL1 is connected to the first scan lines S11 to S1n, the first light-emitting control lines E11 to E1n, and the data lines D1 to Dm. When the scan signals are supplied from the first scan lines S11 to S1n, the first pixel PXL1 is supplied with the data signals from the data lines D1 to Dm. The first pixel PXL1 receiving the data signal controls the amount of current flowing from the first power source ELVDD to the second power source ELVSS via an organic light emitting diode (not shown).
The second pixels PXL2 are disposed in the second pixel area PXA 2. The second pixel PXL2 is connected to the second scan lines S21, S22, the second light emission control lines E21, E22, and the data lines D1 to D3. When the scan signals are supplied from the second scan lines S21, S22 and the third scan lines S31, S32, the second pixel PXL2 is supplied with the data signals from the data lines D1 to D3. The second pixel PXL2 receiving the data signal controls the amount of current flowing from the first power source ELVDD to the second power source ELVSS via the organic light emitting diode.
In addition, although it is shown in fig. 2 that six second pixels PXL2 are disposed in the second pixel region PXA2 through two second scan lines S21, S22, two second emission control lines E21, E22, and three data lines D1 to D3, it is not limited thereto. That is, the plurality of second pixels PXL2 are arranged to correspond to the size of the second pixel area PXA2, and the numbers of the second scan lines, the second light emission control lines, and the data lines may be differently set to correspond to the second pixels PXL 2.
The third pixel PXL3 is disposed in the third pixel area PXA3 and is connected to the third scan lines S31, S32, the third light emission control lines E31, E32, and the data lines Dm-2 to Dm. When the scan signals are supplied from the third scan lines S31, S32 and the second scan lines S21, S22, the third pixel PXL3 is supplied with the data signals from the data lines Dm-2 to Dm. The third pixel PXL3 receiving the data signal controls the amount of current flowing from the first power source ELVDD to the second power source ELVSS via the organic light emitting diode.
In addition, although it is shown in fig. 2 that six third pixels PXL3 are disposed in the third pixel area PXA3 through two third scanning lines S31, S32, two third light emission control lines E31, E32, and three data lines Dm-2 to Dm, it is not limited thereto. That is, the plurality of third pixels PXL3 are arranged to correspond to the size of the third pixel area PXA3, and the numbers of the third scanning lines, the third light emission control lines, and the data lines may be differently set to correspond to the third pixels PXL 3.
The first scan driver SDV1 supplies scan signals to the first scan lines S11 to S1n in response to a first gate control signal GCS1 from the timing control unit TC. For example, the first scan driver SDV1 may sequentially supply scan signals to the first scan lines S11 to S1 n. When the scan signals are sequentially supplied to the first scan lines S11 to S1n, the first pixels PXL1 are sequentially selected in units of horizontal lines.
The second scan driver SDV2 supplies scan signals to the second scan lines S21, S22 in response to the second gate control signal GCS2 from the timing control unit TC. Here, the scan signals supplied to the second scan lines S21, S22 are supplied to the third scan lines S31, S32 via the scan line connecting portions. The second scan driver SDV2 may sequentially supply scan signals to the second scan lines S21, S22. When the scan signals are sequentially supplied to the second scan lines S21, S22, the second pixel PXL2 and the third pixel PXL3 are sequentially selected in units of horizontal lines.
The third scan driver SDV3 supplies scan signals to the third scan lines S31, S32 in response to a third gate control signal GCS3 from the timing control unit TC. Here, the scan signals supplied to the third scan lines S31, S32 are supplied to the second scan lines S21, S22 via the scan line connection portions. The third scan driver SDV3 may sequentially supply scan signals to the third scan lines S31, S32. When the scan signals are sequentially supplied to the third scan lines S31, S32, the second pixel PXL2 and the third pixel PXL3 are sequentially selected in units of horizontal lines.
In the embodiment, since the second scan lines S21, S22 and the third scan lines S31, S32 are electrically connected by the scan line connection portion, the scan signal supplied from the second scan driver SDV2 and the scan signal supplied from the third scan driver SDV3 are supplied so that they are synchronized with each other.
In addition, the second and third scan drivers SDV2 and SDV3 may be driven such that they are synchronized with each other, and thus, the second and third scan drivers SDV2 and SDV3 may be driven by the same gate control signal GCS. For example, the third gate control signal GCS3 supplied to the third scan driver SDV3 may be set to the same signal as the second gate control signal GCS 2.
The first light emission driver EDV1 supplies light emission control signals to the first light emission control lines E11 to E1n in response to the fourth gate control signal GCS4 from the timing control unit TC. For example, the first light emitting driver EDV1 may sequentially supply light emission control signals to the first light emission control lines E11 to E1 n.
Here, the light emission control signal may be set to have a width greater than that of the scan signal. For example, the light emission control signal supplied to the i-th (i is a natural number greater than 1) first light emission control line E1i may be supplied such that it overlaps with the scan signal supplied to the i-1-th first scan line S1i-1 and the scan signal supplied to the i-th first scan line S1i for at least a partial period of time.
The second light emission driver EDV2 supplies a light emission control signal to the second light emission control lines E21, E22 in response to a fifth gate control signal GCS5 from the timing control unit TC. The second light emission driver EDV2 may sequentially supply light emission control signals to the second light emission control lines E21, E22.
The third light emission driver EDV3 supplies a light emission control signal to the third light emission control lines E31, E32 in response to the sixth gate control signal GCS6 from the timing control unit TC. The third light emission driver EDV3 may sequentially supply light emission control signals to the third light emission control lines E31, E32.
In addition, the light emission control signal may be set to a gate-off voltage (e.g., a high voltage) so that the transistors included in the pixels PXL may be turned off, and the scan signal may be set to a gate-on voltage (e.g., a low voltage) so that the transistors included in the pixels PXL may be turned on.
In an embodiment, the light emission control signal supplied from the second light emission driver EDV2 to the second light emission control line E21 may be supplied at the same time as the light emission control signal supplied from the third light emission driver EDV3 to the third light emission control line E31. Likewise, the light emission control signal supplied from the second light emission driver EDV2 to the second light emission control line E22 may be supplied at the same time as the light emission control signal supplied from the third light emission driver EDV3 to the third light emission control line E32.
In an embodiment, the second and third light emission drivers EDV2 and EDV3 may be driven such that they are synchronized with each other, and thus, the second and third light emission drivers EDV2 and EDV3 may be driven by the same gate control signal GCS. For example, the sixth gate control signal GCS6 supplied to the third light emission driver EDV3 may be set to the same signal as the fifth gate control signal GCS 5.
The data driver DDV may supply data signals to the data lines D1 to Dm in response to a data control signal DCS. The data signals supplied to the data lines D1 to Dm are supplied to the pixels PXL selected by the scan signal.
The timing control unit TC supplies gate control signals GCS1 to GCS6 generated based on timing signals supplied from the outside to the scan driver SDV and the light emission driver EDV, and supplies a data control signal DCS to the data driver DDV.
Each of the gate control signals GCS1 through GCS6 includes a start pulse and a clock signal. The start pulse controls a timing of the first scan signal or the first light emission control signal. The clock signal is used to shift the start pulse.
The data control signal DCS includes a source start pulse and a clock signal. The source start pulse controls the start time point of sampling of data. The clock signal is used to control the sampling operation.
In an embodiment, when sequentially driving the display devices, the first scan driver SDV1 may be supplied with the last output signal of the second scan driver SDV2 as a start pulse. Likewise, when the display devices are sequentially driven, the first light emitting driver EDV1 may be supplied with the last output signal of the second light emitting driver EDV2 as a start pulse.
The load matching capacitor LMCAP may be connected to the scan lines S21, S22, S31, and S32 and the emission control lines E21, E22, E31, and E32 disposed in the second and third areas a2 and A3. The load matching capacitor LMCAP may be formed to correspond to each of the scan lines S21, S22, S31, and S32 and the emission control lines E21, E22, E31, and E32, respectively. Each of the load matching capacitors LMCAP may include one electrode connected to the scan lines S21, S22, S31, and S32 or the emission control lines E21, E22, E31, and E32 and the other electrode connected to the first power source ELVDD.
Fig. 3 is a view illustrating an embodiment of the first pixel illustrated in fig. 2.
In fig. 3, for convenience of explanation, the first pixel PXL1 connected to the mth data line Dm, the ith first scan line S1i, and the ith first light emission control line E1i is shown.
Referring to fig. 3, the first pixel PXL1 according to the embodiment of the present disclosure is provided with an organic light emitting diode OLED, first to seventh transistors T1 to T7, and a storage capacitor CST.
An anode of the organic light emitting diode OLED is connected to the first transistor T1 via the sixth transistor T6, and a cathode of the organic light emitting diode OLED is connected to the second power source ELVSS. Such an organic light emitting diode OLED generates light of a certain luminance corresponding to the amount of current supplied from the first transistor T1.
The first power source ELVDD may be set to a voltage higher than the second power source ELVSS so that current may flow to the organic light emitting diode OLED.
The seventh transistor T7 is connected between the initialization power supply VINT and the anode of the organic light emitting diode OLED. In addition, a gate electrode of the seventh transistor T7 is connected to the i-1 st first scan line S1i-1 or the i +1 th first scan line S1i + 1. When a scan signal is supplied to the i-1 st first scan line S1i-1 or the i +1 th first scan line S1i +1, such a seventh transistor T7 is turned on and supplies the voltage of the initialization power supply VINT to the anode electrode of the organic light emitting diode OLED. Here, the initialization power supply VINT may be set to a voltage lower than the data signal.
The sixth transistor T6 is connected between the first transistor T1 and the organic light emitting diode OLED. In addition, a gate electrode of the sixth transistor T6 is connected to the ith first light emission control line E1 i. Such a sixth transistor T6 is turned off when a light emission control signal is supplied to the ith first light emission control line E1i, and otherwise, the sixth transistor T6 is turned on.
The fifth transistor T5 is connected between the first power source ELVDD and the first transistor T1. In addition, a gate electrode of the fifth transistor T5 is connected to the ith first light emission control line E1 i. Such a fifth transistor T5 is turned off when a light emission control signal is supplied to the ith first light emission control line E1i, and otherwise, the fifth transistor T5 is turned on.
A first electrode of the first transistor T1 (driving transistor) is connected to the first power source ELVDD via a fifth transistor T5, and a second electrode of the first transistor T1 is connected to the anode electrode of the organic light emitting diode OLED via a sixth transistor T6. In addition, the gate electrode of the first transistor T1 is connected to the first node N1. Such a first transistor T1 controls an amount of current flowing from the first power source ELVDD to the second power source ELVSS via the organic light emitting diode OLED in response to the voltage of the first node N1.
The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. In addition, a gate electrode of the third transistor T3 is connected to the ith first scan line S1 i. When a scan signal is supplied to the ith first scan line S1i, such a third transistor T3 is turned on and electrically connects the second electrode of the first transistor T1 and the first node N1. Accordingly, when the third transistor T3 is turned on, the first transistor T1 is diode-connected.
The fourth transistor T4 is connected between the first node N1 and the initialization power supply VINT. In addition, a gate electrode of the fourth transistor T4 is connected to the i-1 st first scan line S1 i-1. Such a fourth transistor T4 is turned on when the scan signal is supplied to the i-1 th first scan line S1i-1, and supplies the voltage of the initialization power supply VINT to the first node N1.
The second transistor T2 is connected between the mth data line Dm and the first electrode of the first transistor T1. In addition, a gate electrode of the second transistor T2 is connected to the ith first scan line S1 i. When a scan signal is supplied to the ith first scan line S1i, such a second transistor T2 is turned on and electrically connects the mth data line Dm and the first electrode of the first transistor T1.
The storage capacitor CST is connected between the first power source ELVDD and the first node N1. Such a storage capacitor CST stores the data signal and a voltage corresponding to the threshold voltage of the first transistor T1.
In an embodiment, the second pixel PXL2 and the third pixel PXL3 may be implemented in the same circuit as that of the first pixel PXL 1. Therefore, detailed descriptions of the second pixel PXL2 and the third pixel PXL3 are omitted.
Fig. 4 is a sectional view showing a display device in a display area.
Referring to fig. 4, in an embodiment, a display apparatus may include a substrate 100, a lower conductive layer, a buffer layer 110, an active pattern ACT, a first gate insulating layer 120, a first gate conductive layer, a second gate insulating layer 130, a second gate conductive layer, an interlayer insulating layer 140, a first data conductive layer, a first insulating layer 150, a second insulating layer 160, a second data conductive layer, a third insulating layer 170, a pixel defining layer PDL, a light emitting structure 180, and a thin film encapsulation layer TFE.
The substrate 100 may be provided including any of transparent or opaque insulating materials. For example, the substrate 100 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluoride-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, and the like. Alternatively, the substrate 100 may include a flexible transparent material such as a flexible transparent resin substrate (e.g., a polyimide substrate). For example, the substrate 100 may include a first polyimide layer 101, a first barrier layer 102 disposed on the first polyimide layer 101, a second polyimide layer 103 disposed on the first barrier layer 102, and a second barrier layer 104 disposed on the second polyimide layer 103.
A lower conductive layer including a protective pattern BML1 may be disposed on the substrate 100. The protection pattern BML1 may be disposed to overlap the active pattern ACT and serve as a protection layer for preventing or substantially preventing degradation of electrical characteristics of the active pattern ACT of the thin film transistor TFT. For example, in a process of manufacturing the display device 100, the thin film transistor TFT may be protected from laser light or moisture flowing from the bottom of the substrate 100 which is a flexible substrate. The protection pattern BML1 may minimize or reduce variation in the threshold voltage of the thin film transistor TFT caused by laser light irradiated into the active pattern ACT of the thin film transistor TFT through the substrate 100. The lower conductive layer may be formed of a metal having low light transmittance. For example, the lower conductive layer may include molybdenum (Mo).
In an embodiment, the buffer layer 110 may be entirely disposed on the substrate 100 on which the lower conductive layer is disposed. The buffer layer 110 may prevent or substantially prevent metal atoms and/or impurities from diffusing from the substrate 100 into the active pattern ACT. In addition, the buffer layer 110 may control a heat transfer rate in a crystallization process for forming the active pattern ACT, thereby obtaining a substantially uniform active pattern ACT.
The active pattern ACT may be disposed on the buffer layer 110. In an embodiment, the active pattern ACT may include amorphous silicon or polysilicon. In some example embodiments, the active pattern ACT may include an oxide of at least one selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The active pattern ACT may include a channel region C and impurity-doped source and drain regions S and D.
The first gate insulating layer 120 may be disposed on the buffer layer 110. The first gate insulating layer 120 may be uniformly formed on the buffer layer 110 along the contour of the active pattern ACT. The first gate insulating layer 120 may include a silicon compound, a metal oxide, and the like. In an embodiment, the first gate insulating layer 120 may be formed of a plurality of layers.
A first gate conductive layer including the scan line, the gate electrode GE, and the first storage electrode CE1 may be disposed on the first gate insulating layer 120. The gate electrode GE may overlap the active pattern ACT. The first gate conductive layer may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like.
The second gate insulating layer 130 may be disposed on the first gate insulating layer 120 on which the first gate conductive layer is disposed. For example, the second gate insulating layer 130 may be uniformly formed on the first gate insulating layer 120 along the profile of the first gate conductive layer. Here, the second gate insulating layer 130 may have a relatively small thickness, so that a stepped portion may be formed at a portion of the second gate insulating layer 130 adjacent to the first gate conductive layer. In some example embodiments, the second gate insulating layer 130 may have a relatively large thickness to sufficiently cover the first gate conductive layer, so that the second gate insulating layer 130 may have a substantially horizontal surface. The second gate insulating layer 130 may include a silicon compound, a metal oxide, or the like. In an embodiment, the second gate insulating layer 130 may be formed of a plurality of layers.
A second gate conductive layer including the second storage electrode CE2 may be disposed on the second gate insulating layer 130. The second storage electrode CE2 may overlap the first storage electrode CE1 to form a storage capacitor. The second gate conductive layer may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like.
The interlayer insulating layer 140 may be disposed on the second gate insulating layer 130 on which the second gate conductive layer is disposed. For example, the interlayer insulating layer 140 may have a relatively large thickness to sufficiently cover the second gate conductive layer, so that the interlayer insulating layer 140 may have a substantially horizontal surface. In some example embodiments, the interlayer insulating layer 140 may be uniformly formed on the second gate insulating layer 130 along the profile of the second gate conductive layer. In an embodiment, the interlayer insulating layer 140 may be formed of a plurality of layers.
The first data conductive layer may be disposed on the interlayer insulating layer 140. The first data conductive layer may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. The first data conductive layer may include a first source-drain pattern SD1 and a data line, the first source-drain pattern SD1 being electrically connected to the active pattern ACT through a contact hole formed through the first gate insulating layer 120, the second gate insulating layer 130, and the interlayer insulating layer 140.
The active pattern ACT and the gate electrode GE may be included in the thin film transistor TFT. For example, the thin film transistor TFT may be any one of the transistors described with respect to fig. 3.
The first insulating layer 150 may be disposed on the interlayer insulating layer 140 on which the first data conductive layer is disposed. The first insulating layer 150 may be formed using an inorganic material such as a silicon compound, a metal, or a metal oxide.
The second insulating layer 160 may be disposed on the first insulating layer 150. The second insulating layer 160 may have a single-layer structure or a multi-layer structure including at least two insulating films. In an embodiment, the second insulating layer 160 may be formed using an organic material. For example, the second insulating layer 160 may include a photoresist, an acrylic resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, or the like.
A second data conductive layer may be disposed on the second insulating layer 160, the second data conductive layer including a second source-drain pattern SD2 electrically connected to the first source-drain pattern SD1 through a contact hole formed through the first insulating layer 150 and the second insulating layer 160.
A third insulating layer 170 may be disposed on the second insulating layer 160 on which the second data conductive layer is disposed. The third insulating layer 170 may have a single-layer structure or a multi-layer structure including at least two insulating films. In an embodiment, the third insulating layer 170 may be formed using an organic material. For example, the third insulating layer 170 may include a photoresist, an acrylic resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, or the like.
The light emitting structure 180 may include a first electrode 181, a light emitting layer 182, and a second electrode 183.
The first electrode 181 may be disposed on the third insulating layer 170. The first electrode 181 may be electrically connected to a contact pad (pad, also referred to as a "pad" or a "pad") through a contact hole formed through the third insulating layer 170.
The first electrode 181 may include a reflective material or a transmissive material according to an emission type of the display device. For example, the first electrode 181 may be formed using aluminum, an alloy containing aluminum, aluminum nitride, silver, an alloy containing silver, tungsten nitride, copper, an alloy containing copper, nickel, an alloy containing nickel, chromium nitride, molybdenum, an alloy containing molybdenum, titanium nitride, platinum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, indium tin oxide, indium oxide, gallium oxide, indium zinc oxide, or the like. These materials may be used alone or in combination. In example embodiments, the first electrode 181 may have a single-layer structure or a multi-layer structure, which may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and/or a transparent conductive film.
The pixel defining layer PDL may be disposed on the third insulating layer 170 on which the first electrode 181 is disposed. The pixel defining layer PDL may be formed using an organic material. For example, the pixel defining layer PDL may include a photoresist, an acrylic resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, or the like. In some example embodiments, the opening exposing the first electrode 181 may be formed by etching the pixel defining layer PDL. An emission area and a non-emission area of the display device may be defined by an opening of the pixel defining layer PDL. For example, a portion where the opening of the pixel defining layer PDL is located may correspond to an emission region, and the non-emission region may correspond to a portion adjacent to the opening of the pixel defining layer PDL.
The light emitting layer 182 may be disposed on the first electrode 181 exposed through the opening of the pixel defining layer PDL. In addition, the light emitting layer 182 may extend on the sidewall of the opening of the pixel defining layer PDL. In some example embodiments, the light emitting layer 182 may include an organic light Emitting Layer (EL), a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Transport Layer (ETL), an Electron Injection Layer (EIL), and the like. In some example embodiments, the hole injection layer, the hole transport layer, the electron transport layer, and the electron injection layer may be collectively formed to correspond to a plurality of pixels, in addition to the organic light emitting layer. In some example embodiments, the plurality of organic light emitting layers may be formed using light emitting materials for generating different colors of light (such as red, green, and blue light) according to color pixels of the display device. In some example embodiments, the organic light emitting layer of the light emitting layer 182 may include a plurality of stacked light emitting materials for generating red, green and blue light, thereby emitting white light. Here, the elements of the light emitting layer 182 are collectively formed to correspond to a plurality of pixels, and each pixel may be divided by a color filter layer.
The second electrode 183 may be disposed on the pixel defining layer PDL and the light emitting layer 182. The second electrode 183 may include a transmissive material or a reflective material according to an emission type of the display device. For example, the second electrode 183 can be formed using aluminum, an alloy containing aluminum, aluminum nitride, silver, an alloy containing silver, tungsten nitride, copper, an alloy containing copper, nickel, an alloy containing nickel, chromium nitride, molybdenum, an alloy containing molybdenum, titanium nitride, platinum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, indium tin oxide, indium oxide, gallium oxide, indium zinc oxide, or the like. These materials may be used alone, or may be used in combination of these materials. In example embodiments, the second electrode 183 may also have a single-layer structure or a multi-layer structure, which may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and/or a transparent conductive film.
The thin film encapsulation layer TFE may be disposed on the second electrode 183. The thin film encapsulation layer TFE can prevent or substantially prevent moisture and oxygen from penetrating from the outside. In an embodiment, the thin film encapsulation layer TFE may include at least one organic layer and at least one inorganic layer. The at least one organic layer and the at least one inorganic layer may be alternately stacked with each other. For example, the thin film encapsulation layer TFE may include two inorganic layers and one organic layer between the two inorganic layers, but is not limited thereto. In some example embodiments, a sealing substrate for shielding external air and moisture from penetrating into the display device can be provided instead of the thin film encapsulation layer TFE.
Fig. 5 is a plan view illustrating a region "a" of fig. 1; FIG. 6 is a cross-sectional view taken along line I-I' of FIG. 5; fig. 7A, 7B, 7C, and 7D are plan views illustrating the auxiliary conductive pattern, the first contact hole, the first gate conductive layer, and the second contact hole of the display device of fig. 5 and 6, respectively.
Referring to fig. 1 and 4 to 7D, in the upper second peripheral region PPA2U, the display device may include a substrate 100, a lower conductive layer, a buffer layer 110, a first gate insulating layer 120, a first gate conductive layer, a second gate insulating layer 130, an interlayer insulating layer 140, a first insulating layer 150, a second insulating layer 160, a third insulating layer 170, a second electrode 183, and a thin film encapsulation layer TFE.
The lower conductive layer may further include an auxiliary conductive pattern BML 2. The auxiliary conductive pattern BML2 may be used to form a capacitor with the load match line LML to appropriately compensate for the load of the scan line connected to the load match line LML. In an embodiment, the auxiliary conductive pattern BML2 may be formed of the same layer as that of the protective pattern BML 1. Therefore, the load of the scan line can be compensated for by using the lower conductive layer without using a separate additional layer structure.
The first gate conductive layer may further include a load match line LML and a connection line CTL.
The load match line LML may overlap the auxiliary conductive pattern BML 2. The load match lines LML may extend in a first direction DR 1. The load match line LML may be formed for each scan line requiring load compensation. The connection line CTL may be separated from the load match line LML. The connection line CTL may be connected to the auxiliary conductive pattern BML2 through a first contact hole CNT1 formed through the first gate insulating layer 120 and the buffer layer 110. The connection line CTL may be connected to the load matching electrode LCE through a second contact hole CNT2 formed through the second gate insulating layer 130 and the interlayer insulating layer 140. The first and second contact holes CNT1 and CNT2 may be arranged not to overlap each other, and a plurality of contact holes may be alternately arranged along the connection line CTL.
The first data conductive layer may include a load matching electrode LCE. The load matching electrode LCE may overlap the load matching line LML to form a capacitor. That is, in order to reduce the load deviation of the scan line, a load matching capacitor corresponding to the scan line requiring load compensation may be formed. The load matching capacitor may include a first load matching capacitor formed by the auxiliary conductive pattern BML2, the load match line LML, and an insulating layer between the auxiliary conductive pattern BML2 and the load match line LML, and a second load matching capacitor formed by the load match line LML, the load match electrode LCE, and an insulating layer between the load match line LML and the load match electrode LCE.
Although the load matching electrode LCE and the auxiliary conductive pattern BML2 are connected by the connection line CTL in the present embodiment, they may be directly connected to each other or may be connected to each other through a conductive pattern of another layer.
The second electrode 183 may overlap the load matching electrode LCE.
The second power source ELVSS may be applied to the second electrodes 183 and the first power source ELVDD may be applied to the auxiliary conductive patterns BML2 and the load matching electrodes LCE. In some example embodiments, the second power source ELVSS may be applied to the load matching electrode LCE.
In addition, the load matching capacitor is formed by the auxiliary conductive pattern BML2 and the load matching electrode LCE, so that it has a more stable structure than the case where the load matching capacitor is formed using the active pattern ACT and the first gate conductive layer. This is because when the load matching capacitor is formed using the active pattern ACT and the first gate conductive layer, a short defect may occur between the active pattern ACT and the first gate conductive layer due to the narrow gap.
On the other hand, in the notch peripheral area NPA, not only the load matching line LML but also the auxiliary conductive pattern BML2 in the area "a" in fig. 1 (which is a peripheral area adjacent to the notch peripheral area NPA) may be formed for load matching. The display device may have a structure similar to the sectional view shown in fig. 6.
Fig. 8 is a plan view illustrating an auxiliary conductive pattern of a display device according to another embodiment of the present invention.
The display apparatus is substantially the same as that of fig. 1 to 7D except that a plurality of slits SLT are formed in the auxiliary conductive pattern BML 2. Therefore, duplicate description will be omitted.
In an embodiment, the auxiliary conductive pattern BML2 may be formed with a slit SLT. The slit SLT may be disposed not to overlap the load match line LML. The connecting line CTL may be arranged not to overlap the slit SLT or to overlap the slit SLT.
In the embodiment shown in fig. 7A, the auxiliary conductive pattern BML2 has a plate shape. In the embodiment shown in fig. 8, the slit SLT is formed in the auxiliary conductive pattern BML 2. However, the shape of the auxiliary conductive pattern BML2 is not limited thereto, and various modifications may be made.
Fig. 9 is a plan view illustrating a first gate conductive layer of a display device according to another embodiment of the present invention.
The display apparatus is substantially the same as that of fig. 1 to 7D except for the arrangement of the load match line LML and the connection line CTL. Therefore, duplicate description will be omitted.
In the embodiment of fig. 7C, the connection lines CTL are arranged above and below the four load match lines LML, respectively. In the embodiment of fig. 9, one connection line CTL is arranged for each of the two load match lines LML. However, the arrangement and number of the load match lines LML and the connection lines CTL are not limited thereto, and may be variously changed.
According to an exemplary embodiment of the inventive concept, a display apparatus includes: a substrate; a lower conductive layer including a protective pattern and an auxiliary conductive pattern disposed on the substrate; a buffer layer disposed on the lower conductive layer; an active pattern disposed on the buffer layer and overlapping the protective pattern; a first gate insulating layer disposed on the active pattern; and a first gate conductive pattern disposed on the first gate insulating layer, including a gate electrode overlapping the active pattern and a load matching line overlapping the auxiliary conductive pattern. Accordingly, since the scan line and the load matching line are physically connected and are not connected to each other through the contact hole or the like in the manufacturing process, use, or the like of the display device, it is possible to provide a structure that minimizes or reduces characteristic variation and damage of the thin film transistor caused by static electricity flowing into the active pattern through the contact hole.
In addition, since the load matching capacitor is formed by using the lower conductive layer, the possibility of short-circuiting with the gate conductive layer can be reduced as compared with the case where the load matching capacitor is formed using the active layer.
In addition, since the thin film transistor can be protected by the protection pattern, display quality of the display device can be improved.
FIG. 10 is a block diagram illustrating an electronic device according to an example embodiment; fig. 11A is a diagram showing an example in which the electronic apparatus of fig. 10 is implemented as a television set; fig. 11B is a diagram illustrating an example in which the electronic apparatus of fig. 10 is implemented as a smartphone.
Referring to fig. 10 through 11B, the electronic device 500 may include a processor 510, a memory device 520, a storage device 530, an input/output (I/O) device 540, a power supply 550, and a display device 560. Here, the display unit 560 may correspond to the display apparatus of fig. 1. Additionally, electronic device 500 may also include multiple ports for communicating with video cards, sound cards, memory cards, Universal Serial Bus (USB) devices, other electronic devices, and the like. In an example embodiment, as shown in fig. 11A, the electronic device 500 may be implemented as a television. In another example embodiment, as shown in fig. 11B, the electronic device 500 may be implemented as a smartphone. However, the electronic device 500 is not limited thereto. For example, the electronic device 500 may be implemented as a cellular phone, video phone, smart tablet, smart watch, tablet PC, car navigation system, computer monitor, laptop, Head Mounted Display (HMD), and so on.
Processor 510 may perform various computing functions. Processor 510 may be a microprocessor, Central Processing Unit (CPU), Application Processor (AP), or the like. Processor 510 may be coupled to other components via an address bus, a control bus, a data bus, and the like. Further, the processor 510 may be coupled to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus. The memory device 520 may store data for operation of the electronic device 500. For example, the memory device 520 may include at least one non-volatile memory device, such as an Erasable Programmable Read Only Memory (EPROM) device, an Electrically Erasable Programmable Read Only Memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a Resistive Random Access Memory (RRAM) device, a Nano Floating Gate Memory (NFGM) device, a polymer random access memory (popram) device, a Magnetic Random Access Memory (MRAM) device, a Ferroelectric Random Access Memory (FRAM) device, etc., and/or at least one volatile memory device, such as a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a mobile DRAM device, etc. The storage device 530 may include a Solid State Drive (SSD) device, a Hard Disk Drive (HDD) device, a CD-ROM device, and the like. The I/O devices 540 may include input devices such as keyboards, keypads, mouse devices, touch pads, touch screens, etc., as well as output devices such as printers, speakers, etc. The power supply 550 may provide power for the operation of the electronic device 500.
The display device 560 may be coupled to the other components via a bus or other communication link. In some example embodiments, display device 560 may be included in I/O device 540. As described above, the display device 560 may have the notch-formed display region including the regions having different surface areas, and the display device 560 may have uniform luminance regardless of the regions. However, since this has been described above, a repetitive description thereof is omitted.
The inventive concept can be applied to a display device and an electronic device including the same. For example, the inventive concept may be applied to cellular phones, smart phones, video phones, smart tablets, smart watches, tablet PCs, car navigation systems, televisions, computer monitors, laptops, head mounted displays, and the like.
The foregoing is illustrative of the inventive concept and is not to be construed as limiting thereof. Although a few exemplary embodiments of the inventive concept have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and aspects of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as set forth in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of the inventive concept and is not to be construed as limiting the specific exemplary embodiments disclosed, and that modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the scope of the appended claims. The inventive concept is defined by the claims included therein and the equivalents of the claims.

Claims (20)

1. A display device, the display device comprising:
a substrate;
a lower conductive layer including a protective pattern and an auxiliary conductive pattern on the substrate;
a buffer layer on the lower conductive layer;
an active pattern on the buffer layer and overlapping the protection pattern;
a first insulating layer on the active pattern; and
a first conductive layer on the first insulating layer, the first conductive layer including a gate electrode overlapping the active pattern and a load matching line overlapping the auxiliary conductive pattern.
2. The display device of claim 1, further comprising:
an interlayer insulating layer on the first conductive layer; and
a second conductive layer on the interlayer insulating layer, the second conductive layer including a load match electrode overlapping the load match line.
3. The display device of claim 2, wherein the first conductive layer further comprises a connection line spaced apart from the load match line.
4. The display device according to claim 3, wherein the connection line is electrically connected to the auxiliary conductive pattern through a first contact hole formed through the first insulating layer and the buffer layer, and is electrically connected to the load matching electrode through a second contact hole formed through the interlayer insulating layer.
5. The display device of claim 4, wherein the first contact hole and the second contact hole do not overlap each other.
6. The display device of claim 3, wherein the substrate comprises: a first pixel region; a second pixel region connected to the first pixel region and having a size smaller than that of the first pixel region; a first peripheral region serving as a non-display region and adjacent to the first pixel region; and a second peripheral region which is a non-display region and is adjacent to the second pixel region, and
wherein the load match line includes a plurality of load match lines corresponding to gate lines in the second pixel region, and
the connecting lines comprise a plurality of connecting lines.
7. The display device of claim 2, wherein the auxiliary conductive pattern, the load match line, and a layer between the auxiliary conductive pattern and the load match line form a first load match capacitor, and
the load match line, the load match electrode, and the layer between the load match line and the load match electrode form a second load match capacitor.
8. The display device according to claim 2, wherein the first conductive layer further comprises a first storage electrode,
wherein the display device further comprises:
a second insulating layer on the first conductive layer; and
a third conductive layer on the second insulating layer, the third conductive layer including a second storage electrode overlapping the first storage electrode.
9. The display device of claim 8, further comprising:
a third insulating layer on the first conductive layer; and
and a light emitting structure on the third insulating layer, the light emitting structure including a first electrode, a second electrode facing the first electrode, and a light emitting layer between the first electrode and the second electrode.
10. The display device according to claim 9, wherein the second electrode overlaps the load matching electrode.
11. The display device according to claim 9, wherein a second power source is applied to the second electrode, and
a first power is applied to the auxiliary conductive pattern and the load matching electrode.
12. The display device of claim 1, wherein the substrate comprises: a first pixel region; a second pixel region connected to the first pixel region and having a size smaller than that of the first pixel region; a first peripheral region serving as a non-display region and adjacent to the first pixel region; and a second peripheral region which is a non-display region and is adjacent to the second pixel region, and
wherein the auxiliary conductive pattern and the load match line are located in the second peripheral region,
the active pattern and the gate electrode constitute a thin film transistor, and
the thin film transistor is located in the second pixel region.
13. The display device according to claim 12, wherein the second pixel region is adjacent to an upper side of the first pixel region, and the second peripheral region includes an upper second peripheral region positioned adjacent to the upper side of the second pixel region,
wherein the load match line is located in the upper second peripheral region.
14. The display device according to claim 13, wherein the first conductive layer further comprises a gate line, and
the load match line is physically connected to the gate line.
15. The display device of claim 12, wherein the substrate further comprises: a third pixel region separated from the second pixel region, connected to the first pixel region, and having a size smaller than that of the first pixel region; and a third peripheral region as a non-display region adjacent to the third pixel region,
wherein a notch is formed between the second pixel region and the third pixel region.
16. The display device of claim 1, wherein the substrate comprises:
at least one polyimide layer; and
at least one barrier layer.
17. The display device according to claim 1, wherein the lower conductive layer comprises molybdenum.
18. The display device according to claim 1, wherein the auxiliary conductive pattern comprises a slit.
19. A display device, the display device comprising: a first region; a second region adjacent to the first region and having a size smaller than that of the first region; and a third region adjacent to the first region and spaced apart from the second region to form a notch between the second region and the third region, the display device further comprising:
a gate line in the second region;
a first load matching capacitor electrically connected to the gate line; and
a second load matching capacitor electrically connected to the gate line and overlapping the first load matching capacitor.
20. The display device of claim 19, further comprising:
a substrate;
an auxiliary conductive pattern on the substrate;
a load match line on the auxiliary conductive pattern and formed of the same layer as the gate line; and
a load matching electrode on the load matching line,
wherein the first load matching capacitor is formed by the auxiliary conductive pattern, the load matching line, and an insulating layer between the auxiliary conductive pattern and the load matching line, and
the second load matching capacitor is formed by the load match line, the load match electrode, and an insulating layer between the load match line and the load match electrode.
CN201910692763.XA 2018-07-31 2019-07-30 Display device Pending CN110783345A (en)

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