CN110783341A - Method for forming step structure in 3D memory device - Google Patents
Method for forming step structure in 3D memory device Download PDFInfo
- Publication number
- CN110783341A CN110783341A CN201910932697.9A CN201910932697A CN110783341A CN 110783341 A CN110783341 A CN 110783341A CN 201910932697 A CN201910932697 A CN 201910932697A CN 110783341 A CN110783341 A CN 110783341A
- Authority
- CN
- China
- Prior art keywords
- photoresist layer
- layer
- photoresist
- forming
- initial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Landscapes
- Semiconductor Memories (AREA)
Abstract
Disclosed is a method for forming a step structure in a 3D memory device, including: forming a first stacked structure on a substrate; forming a photoresist layer on the first laminated structure, wherein the photoresist layer at least comprises a first photoresist layer and a second photoresist layer; etching the first laminated structure according to the photoresist layer to form a multi-stage step; the method for forming the first photoresist layer comprises the following steps: coating photoresist on a substrate to form a first initial photoresist layer, and carrying out first baking on the first initial photoresist layer; the method for forming the second photoresist layer comprises the following steps: pre-wetting the first photoresist layer, and coating photoresist on the surface of the first photoresist layer to form a second initial photoresist layer; and carrying out second baking on the second initial photoresist layer. According to the method, the photoresist layer is coated in a segmented mode, so that the thickness of the photoresist layer is increased, more step levels can be formed through one photoetching process, the photoetching process steps in the 3D memory device manufacturing process are reduced, the process stability is improved, and the process cost is reduced.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a method for forming a step structure in a 3D memory device.
Background
The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the aperture of a semiconductor manufacturing process becomes smaller, the memory density of a memory device becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost. In a three-dimensional memory device, such as a 3DNAND flash memory, having a substrate and a stack structure on the substrate. The stacked structure is formed by alternately stacking the interlayer insulating layers and the grid electrodes, the central area of the stacked structure is a core storage area, the edge area of the stacked structure is a step structure, and the core storage area is used for forming a storage unit string. And each layer of grid electrode is used as a grid line of each layer of storage unit, and further, the grid electrode is led out through the contact on the step, so that the stacked 3D NAND memory device is realized.
In the process of manufacturing the 3DNAND memory, the step structure is usually formed by a method of combining one lithography with multiple etching, and the specific steps include: step S1, referring to fig. 1a, forming an etching mask pattern on the stacked structure 1 by a photolithography process (e.g., by the photoresist mask 2); step S2, referring to fig. 1b, etching a step structure vertically downward, step S3, referring to fig. 1c, trimming the size of the photoresist mask 2 to expose the surface of the stacked structure with a certain width; step S4, referring to fig. 1d, continuing to etch downward to form a two-stage step structure; step S5: referring to fig. 1e, steps S3 and S4 are repeated, finally forming the multi-step structure 3.
With the gradual development of the 3DNAND process, more and more steps need to be made in the step process, and the required number of steps can be made only by increasing the thickness of the photoresist mask formed in the photolithography process. However, due to the nature of the existing photoresist, the formed photoresist mask can only reach 12 μm at the thickest, and cannot meet the requirement of more step etching. In addition, the photoresist formed by one-time coating is too thick, which also affects the stability of the baking process.
Disclosure of Invention
In view of the foregoing problems, an object of the present invention is to provide a method for forming a step structure in a 3D memory device, in which the photoresist layer is coated in sections to increase the thickness of the photoresist layer, so that more steps can be formed by one photolithography process, the photolithography process steps in the manufacturing of the 3D memory device are reduced, the process stability is improved, and the process cost is reduced.
According to an aspect of the present invention, there is provided a method of forming a step structure in a 3D memory device, including:
forming a first stacked structure on a substrate;
forming a photoresist layer on the first laminated structure, wherein the photoresist layer at least comprises a first photoresist layer and a second photoresist layer;
etching the first laminated structure according to the photoresist layer to form a multi-stage step;
the method for forming the first photoresist layer comprises the following steps: coating photoresist on the substrate to form a first initial photoresist layer, and carrying out first baking on the first initial photoresist layer;
the method for forming the second photoresist layer comprises the following steps: prewetting the first photoresist layer, and coating photoresist on the surface of the first photoresist layer to form a second initial photoresist layer; and carrying out second baking on the second initial photoresist layer.
Preferably, the pre-wetting the first photoresist layer comprises: and spraying a wetting agent in the middle of the first photoresist layer.
Preferably, a wetting agent is sprayed on the photoresist while the photoresist is coated on the surface of the first photoresist layer.
Preferably, the wetting agent is deionized water.
Preferably, the first photoresist layer and the second photoresist layer respectively comprise a photosensitive resin, a sensitizer and a solvent; the solvent comprises: one or more of acetonitrile, n-amyl ester, anisole, isobutanol, butyl acetate, butyl benzoate, chlorobenzene and cyclohexanone.
Preferably, the formation process of the first initial photoresist layer and the second initial photoresist layer is as follows: and (4) spin coating.
Preferably, the thickness of the first photoresist layer is 6 micrometers to 11 micrometers; the second photoresist layer has a thickness of 4 microns to 9 microns.
Preferably, the parameters for performing the first baking on the first initial photoresist layer include: the first baking temperature is 120-200 ℃, and the first baking time is 60-120 s; the parameters for performing the second baking on the second initial photoresist layer comprise: the second baking temperature is 80-160 ℃, and the second baking time is 120-240 s.
Preferably, the first stacked structure includes a plurality of insulating layers and a plurality of sacrificial layers alternately stacked; the bottom layer of the first laminated structure is an insulating layer, and the top layer of the first laminated structure is a sacrificial layer.
Preferably, the etching the first stacked structure according to the photoresist layer to form a multi-step includes:
carrying out a trimming process on the side wall of the photoresist layer to expose the surface of the top sacrificial layer of the first laminated structure around the photoresist layer;
etching the exposed first laminated structure by taking the trimmed photoresist layer as a mask until the surface of the sacrificial layer of the next layer is exposed;
and repeating the steps of carrying out the trimming process and etching to expose the first laminated structure by taking the trimmed photoresist layer as a mask, so that the sacrificial layer is stepped from the bottom layer to the top layer and gradually reduced in size layer by layer, thereby forming a multi-stage step.
According to the method for forming the step structure in the 3D memory device, the thickness of the photoresist layer is increased by means of sectionally coating the photoresist, more step levels can be formed through one photoetching process, photoetching process steps in 3D memory device manufacturing are reduced, process stability is improved, and process cost is reduced.
Further, the first photoresist layer is pre-wetted, so that the surface of the hardened photoresist after baking is softened again, and the adhesion between the first photoresist layer and the second photoresist layer is improved.
Further, when coating the photoresist to form the second photoresist layer, a wetting agent is sprayed on the photoresist to optimize the flatness of the photoresist surface.
Furthermore, when the first photoresist layer is baked, the photoresist close to the first laminated structure is quickly baked by high temperature, and the photoresist far away from the first laminated structure keeps certain humidity, so that the surface of the photoresist can be better softened when the second photoresist layer is formed.
Furthermore, the second baking temperature is lower than the first baking temperature, and the second baking time is longer than the first baking time, so that the photoresist on the first laminated structure is baked more uniformly, and the overall uniformity of the photoresist is improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIGS. 1a to 1e are schematic structural diagrams illustrating steps of a step structure forming method in the prior art, respectively;
fig. 2 to 9 are schematic structural views illustrating steps of a method of forming a step structure in a 3D memory device according to an embodiment of the present invention;
fig. 10 illustrates a flowchart of forming a photoresist layer in a 3D memory device according to an embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
The term "above" as used herein means above the plane of the substrate, and may refer to direct contact between materials or spaced apart.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The present invention may be embodied in various forms, some examples of which are described below.
Fig. 2 to 6 are schematic structural views illustrating steps of a method of forming a step structure in a 3D memory device according to an embodiment of the present invention. The forming method comprises the following steps:
as shown in fig. 2, a basic structure of a method for forming a step structure in a 3D memory device according to an embodiment of the present invention is shown, the step of forming the structure including: a plurality of insulating layers 111 and a plurality of sacrificial layers 112 are alternately deposited on the substrate 100 to form a stacked first stacked structure 110. The bottom layer of the first stacked structure 110 is an insulating layer 111, and the top layer of the first stacked structure 110 is a sacrificial layer 112. The substrate 100 may be single crystal silicon, polycrystalline silicon, or amorphous silicon; the substrate 100 may also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like. In the present embodiment, the substrate 100 is silicon.
In the present embodiment, the insulating layer 111 is made of silicon oxide, for example, and the sacrificial layer 112 is made of silicon nitride, for example, a Chemical Vapor Deposition (CVD), an Atomic Layer Deposition (ALD), or another suitable deposition method may be adopted to alternately deposit an inter-metal dielectric layer (e.g., silicon oxide, etc.) and a metal replacement sacrificial layer (e.g., silicon nitride, etc.) on the substrate 100, wherein the sacrificial layer 112 is used to occupy the position for the control gate to be formed later, the sacrificial layer 112 is removed later, and the control gate is formed in the position left after the sacrificial layer 112 is removed.
In the present embodiment, the insulating layer 111 at the bottom of the first stacked structure 110 functions as: a sacrificial layer 112 for isolating the surfaces of the substrate 100 and the underlying insulating layer 111; after the sacrificial layer 112 is subsequently removed and the control gate is formed in the position left after the sacrificial layer 112 is removed, the insulating layer 111 at the bottom of the first stacked structure 110 serves to isolate the substrate 100 and the control gate.
A photoresist layer 120 is formed on the first stacked structure 110, wherein the photoresist layer at least includes a first photoresist layer 121 and a second photoresist layer 122, and the forming method refers to fig. 3 to fig. 4.
Referring to fig. 3, a first initial photoresist layer (not shown) is formed on the surface of the first stacked structure 110; the first initial photoresist layer is first baked to form a first photoresist layer 121.
In a preferred embodiment, before forming the first initial photoresist layer, the method further comprises: forming an improvement layer (not shown) on the surface of the first stacked structure 110; pre-wetting the amelioration layer.
Wherein the material of the improvement layer comprises: hexamethyldisilazane for increasing adhesion between the subsequent first photoresist layer 121 and the first stacked structure 110. The modifying layer makes the surface of the first stacked structure 110 hydrophobic, which is beneficial to increase the adhesion between the subsequent first initial photoresist layer and the first stacked structure 110. The pre-wetting is performed on the surface of the improved layer, so that the subsequent first initial photoresist layer can be better bonded with the first stacked structure 110, and the first initial photoresist layer is prevented from being peeled off from the first stacked structure 110 in the subsequent process.
In this embodiment, the first initial photoresist layer includes a photosensitive resin, a sensitizer, and a solvent; the solvent comprises: one or more of acetonitrile, n-amyl ester, anisole, isobutanol, butyl acetate, butyl benzoate, chlorobenzene and cyclohexanone. The first initial photoresist layer forming process comprises a spin coating process.
In this example, the first photoresist layer has a thickness of 6 microns to 11 microns. The parameters for the first baking of the first initial photoresist layer include: the first baking temperature is 120-200 ℃, and the first baking time is 60-120 s. When the first photoresist layer 121 is first baked, the photoresist close to the first stacked structure is quickly baked at a high temperature, and the photoresist farther from the first stacked structure retains a certain degree of wettability, so that the surface of the photoresist can be better softened when the second photoresist layer is formed.
Referring to fig. 4, the first photoresist layer 121 is pre-wetted, and a second initial photoresist layer (not shown) is formed by coating a photoresist on the surface of the first photoresist layer 121; and carrying out second baking on the second initial photoresist layer to form a second photoresist layer 122.
Wherein pre-wetting the first photoresist layer 121 comprises: a wetting agent is sprayed in the middle of the first photoresist layer 121. The first photoresist layer 121 is pre-wetted such that the hardened photoresist surface is re-softened after baking, improving adhesion between the first photoresist layer 121 and the second photoresist layer 122.
In a preferred embodiment, a wetting agent is sprayed on the photoresist while the photoresist is coated on the surface of the first photoresist layer 121, so that the flatness of the photoresist surface can be optimized.
In this embodiment, the wetting agent is deionized water. The deionized water is used for wetting the photoresist, so that on one hand, an ideal wetting effect can be achieved for wetting the photoresist, and on the other hand, new ions cannot be added in the subsequent developing step, so that the subsequent developing solution is prevented from being polluted. Of course, in other embodiments, the wetting agent may be other solvents, and any wetting agent that can wet the photoresist layer and does not contaminate the subsequent developing process is within the scope of the present invention.
In this embodiment, the second initial photoresist layer includes a photosensitive resin, a sensitizer, and a solvent; the solvent comprises: one or more of acetonitrile, n-amyl ester, anisole, isobutanol, butyl acetate, butyl benzoate, chlorobenzene and cyclohexanone. The first initial photoresist layer forming process comprises a spin coating process.
In this embodiment, the process of forming the second initial photoresist layer includes a spin coating process.
In this example, the thickness of the second photoresist layer is 4 microns to 9 microns. The parameters for performing the second baking on the second initial photoresist layer comprise: the second baking temperature is 80-160 ℃, and the second baking time is 120-240 s. The second baking temperature is lower than the first baking temperature, and the second baking time is longer than the first baking time, so that the photoresist on the first laminated structure is baked more uniformly, and the integral uniformity of the photoresist is improved.
In other embodiments, the photoresist layer further comprises a third photoresist layer. The method for forming the third photoresist layer comprises the following steps: pre-wetting the second photoresist layer, and coating photoresist on the surface of the second photoresist layer to form a third initial photoresist layer; and carrying out third baking on the third initial photoresist layer.
Fig. 10 illustrates a flowchart of forming a photoresist layer in a 3D memory device according to an embodiment of the present invention. Specifically, the wetting agent MRRC is sprayed on the first stacked structure 110 for pre-wetting; spraying a photoresist PR (photo resist) to perform first photoresist coating to form a first initial photoresist layer; baking the first initial photoresist for the first time to form a first photoresist layer 121; spraying a wetting agent MRRC on the first photoresist layer 121 for pre-wetting; spraying a photoresist PR for secondary photoresist coating to form a second initial photoresist layer, and spraying a wetting agent on the photoresist during the secondary photoresist coating; the second initial photoresist layer is baked a second time to form a second photoresist layer 122.
Referring to fig. 5 to 9, etching the first stacked structure according to the photoresist layer to form a multi-step specifically includes: performing a trimming process on the sidewall of the photoresist layer 120 to expose the surface of the top sacrificial layer 112 of the first stacked structure around the photoresist layer 120; etching the exposed first stacked structure 110 by using the trimmed photoresist layer as a mask until the surface of the sacrificial layer 112 of the next layer is exposed; the trimming process and the step of etching and exposing the first stacked structure 110 by using the trimmed photoresist layer as a mask are repeated, so that the sacrificial layer 112 is stepped from the bottom layer to the top layer and gradually reduced in size layer by layer, thereby forming a multi-step.
The process of etching the exposed first stacked structure 110 until the surface of the sacrificial layer 112 of the next layer is exposed is an anisotropic dry etching process with the trimmed photoresist layer 120 as a mask, and the parameters include: the gas used comprises CF
4，CHF
3、CH
2F
2、CH
3F、C
4F
6、Ar、O
2And NF
3，CF
4，CHF
3、CH
2F
2、CH
3F、C
4F
6The gas flow rates of (A) and (B) are respectively 20sccm to 200sccm, the gas flow rate of Ar is 200sccm to 2000sccm, and O is
2The gas flow rate of (3) is 5sccm to 100sccm, NF
3The gas flow of the gas source is 5 sccm-100 sccm, the source radio frequency power is 100 watts-1000 watts, the bias video power is 10 watts-1000 watts, and the chamber pressure is 3 mtorr-100 mtorr.
In the process of etching the exposed first stacked structure 110 until the surface of the sacrificial layer 112 of the next layer is exposed by using the trimmed photoresist layer as a mask, although the photoresist layer is continuously consumed, since the thickness of the photoresist layer is thicker, more step numbers can be formed by one photolithography process, the complexity of the subsequent process is reduced, and the process cost is reduced.
In this embodiment, the sacrificial layer 112 has a step shape from the bottom layer to the top layer and has a gradually decreasing size, and further includes: removing the photoresist layer 120; the sacrificial layer 112 is removed, a cavity is formed between adjacent insulating layers 111, and a control gate is formed in the cavity.
According to the method for forming the step structure in the 3D memory device, the thickness of the photoresist layer is increased by means of sectionally coating the photoresist, more step levels can be formed through one photoetching process, photoetching process steps in 3D memory device manufacturing are reduced, process stability is improved, and process cost is reduced.
Other details of the 3D memory device, such as the structure of the memory array, the peripheral interconnections, etc., are not important to the present invention and will not be described herein.
In the context of the present invention, the three-dimensional memory device may be a 3D flash memory, such as a 3D nand flash memory.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.
Claims (10)
1. A method for forming a step structure in a 3D memory device includes:
forming a first stacked structure on a substrate;
forming a photoresist layer on the first laminated structure, wherein the photoresist layer at least comprises a first photoresist layer and a second photoresist layer;
etching the first laminated structure according to the photoresist layer to form a multi-stage step;
the method for forming the first photoresist layer comprises the following steps: coating photoresist on the substrate to form a first initial photoresist layer, and carrying out first baking on the first initial photoresist layer;
the method for forming the second photoresist layer comprises the following steps: prewetting the first photoresist layer, and coating photoresist on the surface of the first photoresist layer to form a second initial photoresist layer; and carrying out second baking on the second initial photoresist layer.
2. The method of forming as claimed in claim 1, wherein pre-wetting the first photoresist layer comprises:
and spraying a wetting agent in the middle of the first photoresist layer.
3. The forming method according to claim 1, wherein a wetting agent is sprayed on the photoresist while the photoresist is coated on the surface of the first photoresist layer.
4. The forming method of claim 2 or 3, wherein the wetting agent is deionized water.
5. The forming method of claim 1, wherein the first photoresist layer and the second photoresist layer each comprise a photosensitive resin, a sensitizer, and a solvent; the solvent comprises: one or more of acetonitrile, n-amyl ester, anisole, isobutanol, butyl acetate, butyl benzoate, chlorobenzene and cyclohexanone.
6. The method of forming as claimed in claim 1, wherein the first and second initial photoresist layers are formed by a process comprising: and (4) spin coating.
7. The method of forming as claimed in claim 1, wherein the first photoresist layer has a thickness of 6-11 microns; the second photoresist layer has a thickness of 4 microns to 9 microns.
8. The method of forming as claimed in claim 1, wherein the parameters of the first bake of the first initial photoresist layer include: the first baking temperature is 120-200 ℃, and the first baking time is 60-120 s; the parameters for performing the second baking on the second initial photoresist layer comprise: the second baking temperature is 80-160 ℃, and the second baking time is 120-240 s.
9. The forming method according to claim 1, wherein the first stacked structure includes a plurality of insulating layers and a plurality of sacrificial layers which are alternately stacked; the bottom layer of the first laminated structure is an insulating layer, and the top layer of the first laminated structure is a sacrificial layer.
10. The forming method of claim 1, wherein etching the first stack structure to form a multi-level step according to the photoresist layer comprises:
carrying out a trimming process on the side wall of the photoresist layer to expose the surface of the top sacrificial layer of the first laminated structure around the photoresist layer;
etching the exposed first laminated structure by taking the trimmed photoresist layer as a mask until the surface of the sacrificial layer of the next layer is exposed;
and repeating the steps of carrying out the trimming process and etching to expose the first laminated structure by taking the trimmed photoresist layer as a mask, so that the sacrificial layer is stepped from the bottom layer to the top layer and gradually reduced in size layer by layer, thereby forming a multi-stage step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910932697.9A CN110783341A (en) | 2019-09-29 | 2019-09-29 | Method for forming step structure in 3D memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910932697.9A CN110783341A (en) | 2019-09-29 | 2019-09-29 | Method for forming step structure in 3D memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110783341A true CN110783341A (en) | 2020-02-11 |
Family
ID=69384681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910932697.9A Pending CN110783341A (en) | 2019-09-29 | 2019-09-29 | Method for forming step structure in 3D memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110783341A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111769037A (en) * | 2020-05-29 | 2020-10-13 | 长江存储科技有限责任公司 | Etching method for semiconductor structure and manufacturing method of 3D memory device |
| WO2024045268A1 (en) * | 2022-08-29 | 2024-03-07 | 长鑫存储技术有限公司 | Manufacturing method for semiconductor structure, and semiconductor structure |
-
2019
- 2019-09-29 CN CN201910932697.9A patent/CN110783341A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111769037A (en) * | 2020-05-29 | 2020-10-13 | 长江存储科技有限责任公司 | Etching method for semiconductor structure and manufacturing method of 3D memory device |
| WO2024045268A1 (en) * | 2022-08-29 | 2024-03-07 | 长鑫存储技术有限公司 | Manufacturing method for semiconductor structure, and semiconductor structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102510610B1 (en) | Plated metal hard mask for vertical nand hole etch | |
| US10825690B2 (en) | Semiconductor structures | |
| TWI405244B (en) | Methods of fabricating substrates | |
| US9887350B2 (en) | MTJ etching with improved uniformity and profile by adding passivation step | |
| US9892933B2 (en) | Lithography using multilayer spacer for reduced spacer footing | |
| US11545388B2 (en) | Staircase formation in three-dimensional memory device | |
| US20120220132A1 (en) | Semiconductor device manufacturing method | |
| TW201913972A (en) | Step structure of memory device | |
| US20210035803A1 (en) | Semiconductor structure and method for forming the same | |
| TW202010108A (en) | Semiconductor structure and method of forming the same | |
| WO2009099769A2 (en) | Double mask self-aligned double patterning technology (sadpt) process | |
| US20150087150A1 (en) | Semiconductor structures and fabrication method thereof | |
| WO2022100070A1 (en) | Photoresist treatment method and self-aligned double patterning method | |
| US7718529B2 (en) | Inverse self-aligned spacer lithography | |
| EP3618103A1 (en) | A patterning method | |
| CN108933140A (en) | The manufacturing method of semiconductor devices | |
| CN110783341A (en) | Method for forming step structure in 3D memory device | |
| TW201923834A (en) | Method of forming semiconductor structure | |
| US20110300712A1 (en) | Methods of Forming a Photoresist Pattern Using Plasma Treatment of Photoresist Patterns | |
| KR100924611B1 (en) | Method of forming a micro pattern in a semiconductor device | |
| CN109950140B (en) | Method for forming self-aligned double-layer pattern | |
| US20200098581A1 (en) | Extreme ultraviolet lithography patterning with directional deposition | |
| KR20190002269A (en) | High aspect ratio gap fill | |
| US20120225560A1 (en) | Manufacturing method of integrated circuits based on formation of lines and trenches | |
| TWI252535B (en) | Method for forming contact plug of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |