CN110781637B - Chip verification auxiliary environment and chip verification system - Google Patents
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Abstract
The invention discloses a chip verification auxiliary environment and a chip verification system; the chip verification auxiliary environment comprises an application scene database used for recording all application scenes of the chip; the verification scene generation and conversion unit automatically generates various verification scenes to be verified according to each application scene, and converts all configured formats of each verification scene into a language which can be identified by the verification environment; the data acquisition and analysis processing unit is used for generating random seeds and acquiring verification results of verification scenes in the verification environment; the scene configuration unit selects a verification scene according to the random seed, and sends each configuration of the verification scene to the verification environment to verify the verification scene; the auxiliary environment can automatically generate all verification scenes according to the settings and convert the verification scenes into languages which can be identified by the verification environment; the accuracy of verification environment setting and the speed of chip verification are greatly improved, and the progress of chip development is quickened.
Description
Technical Field
The present invention relates to the field of chip verification, and in particular, to a chip verification auxiliary environment and a chip verification system.
Background
The verification of the chip means that the hardware and the software of the chip are fully verified before the chip is subjected to chip streaming, so that defects which are difficult to find in the chip design process can be found in time, and timely adjustment and iteration are performed to ensure that the chip streaming is smoothly performed, and 50-80% of the work is verified in the design of the modern complex chip, so that the verification determines the efficiency of the whole design flow in the chip design.
Chip verification becomes more and more important as the integration scale and complexity of chips become higher and higher. In the verification process, thousands of verification tasks of different projects are often faced at the same time, and how to quickly and effectively perform chip verification becomes a great challenge.
In the prior art, chip verification generally only pays attention to whether single configuration of an application scene is covered or not, and for a combined application scene between the configuration, the configuration is randomized by the environment, so that the number of randomization is very large, and not all scenes can be completely verified.
In the prior art, there are also combination scenes between the verification configurations, which are also verified in a random manner, and some combination scenes may not be verified; for example, the verification of a certain chip includes verification of 4 configuration a/B/C/D, in the existing verification environment, the four configuration a/B/C/D combinations have more than 100 application scenarios, which may need to be randomly 500 times or more to verify all combinations, and because all the combinations are random, a part of the application scenarios of the configuration combinations may not be verified, thus resulting in incomplete verification; in addition, no special environment exists in the prior art to count whether all application scenes can be covered.
In addition, in the prior art, if all verification scenes (including various combined application scenes) are to be counted, the statistics is needed manually, the workload is large, the time is long, and errors are easy to occur, so that the traditional chip simulation verification mode has the disadvantages of long time, low automation degree, time and labor consumption, easy errors of personnel verification and the like, and the development period of the whole chip is prolonged.
Disclosure of Invention
The first object of the present invention is to provide a chip verification auxiliary environment, which is matched with the chip verification environment, and can realize the automation of chip verification, and effectively improve the efficiency of chip verification. The first object of the invention is achieved by the following technical scheme:
the chip verification auxiliary environment is used for being matched with the chip verification environment to carry out automatic verification of the chip; the chip verification auxiliary environment is characterized by comprising an application scene database, a verification scene generation and conversion unit, a scene configuration unit and a data acquisition and analysis processing unit;
the application scene database is used for recording all application scenes of the chip;
the verification scene generation and conversion unit is connected with the application scene database and the scene configuration unit, various verification scenes to be verified are automatically generated according to each application scene of the application scene database, all configurations of each verification scene are subjected to format conversion, and data after format conversion are stored in the scene configuration unit;
the data acquisition and analysis processing unit is connected with the scene configuration unit and the verification environment; the data acquisition and analysis processing unit is used for generating random seeds and sending the random seeds to the scene configuration unit; the data acquisition and analysis processing unit is also used for acquiring the verification result of the verification scene in the verification environment, and when the verification of a certain verification scene is completed, the data acquisition and analysis processing unit generates another random seed;
the scene configuration unit is connected with the verification environment, selects one verification scene according to the random seed, and sends various configurations of the verification scene to the verification environment to verify the verification scene.
Further, the system also comprises a configuration sampling unit, a sampling unit and a sampling unit, wherein the configuration sampling unit is used for storing sampling conditions for recording various configurations corresponding to various application scenes; and the verification scene generation and conversion unit automatically generates various verification scenes to be verified according to each application scene of the application scene database and the sampling conditions.
Specifically, the sampling conditions include the range of values of each configuration and the sampling interval.
Specifically, the application scene database is in an Excel format, the verification scene generation and conversion unit identifies an application scene in the application scene database through VBA, and generates verification scenes one by combining sampling conditions of each configuration of the application scene in the configuration sampling unit.
Further, the system also comprises a verification statistical unit; the verification scene generation and conversion unit is connected with the verification statistics unit and the data acquisition and analysis processing unit; the verification statistics unit acquires all verification scenes generated by the verification scene generation and conversion unit and is used for counting verification results of all verification scenes; the data acquisition and analysis processing unit acquires all configurations in the verification environment according to the verification scene generation and conversion unit, combines the acquired configurations to restore a verification scene, and updates the verification result of the verification scene in the verification statistics unit.
Specifically, the verification statistics unit is further configured to count verification times of each verification scene.
Specifically, the verification scene generation and conversion unit converts all the configured formats of each verification scene of the scene configuration unit into SV language, and the language format of the data stored by the scene configuration unit is SV language; and the data storage format of the verification statistical unit is an excel format.
Further, the system also comprises a random seed storage unit which is connected with the data acquisition and analysis processing unit and is used for storing random seeds corresponding to each verification scene during verification.
Further, the data acquisition and analysis processing unit also judges whether each verification scene is fully verified according to the information stored in the verification statistics unit, and the random seed generated by the data acquisition and analysis processing unit randomly generates one verification scene for verification outside the fully verified verification scene.
Further, when the random seeds generated by the data acquisition and analysis processing unit do not have corresponding verification scenes, the scene configuration unit randomly selects combinations of the configurations to form an illegal verification environment for verifying the verification environment; and the verification statistical unit is also used for recording verification results and verification times of the illegal verification environment.
Specifically, the verification scene configuration unit is connected with the verification environment through a software interface; the data acquisition and analysis processing unit is connected with the verification environment through a software interface.
The second object of the present invention is to provide a chip verification system, and the second object of the present invention is achieved by the following technical scheme:
the chip verification system is characterized by comprising a verification environment and an auxiliary environment according to the technical scheme of the first object, wherein the scene configuration unit of the auxiliary environment is connected with the verification environment, and the data acquisition and analysis processing unit of the auxiliary environment is connected with the verification environment.
The invention has the beneficial effects that:
the chip verification auxiliary environment and the chip verification system can automatically generate all verification environments according to the settings and convert the verification environments into languages which can be identified by the verification environments; and the verification condition of each verification scene can be judged, and for the verification scene with insufficient verification, the verification can be preferentially selected, so that the number of complete verification times of the verification is effectively reduced, the verification speed is greatly improved, and the development progress of the chip is accelerated.
In addition, the auxiliary environment has independence and compatibility, and for a verifier, the application scene database, the configuration sampling unit and the embedding of a software interface for carrying out data interaction between the auxiliary environment and the verification environment can be completed; under the cooperation of the auxiliary environment and the verification environment, the verification environment can automatically and rapidly complete the verification work of all verification scenes.
Drawings
Fig. 1 is a block diagram of a chip verification system according to an embodiment of the present invention.
Detailed Description
In order to more clearly understand the technical solution of the present invention, the present invention is further described below with reference to the following examples, and the specific examples are only for convenience of explanation of the solution content of the present invention, and the protection content of the present invention is not limited to the disclosure content of the specific examples.
The embodiment provides a chip auxiliary environment which is used for being matched with a chip verification environment to carry out automatic verification of the chip; the verification environment comprises a verification unit, and the chip verification auxiliary environment comprises an application scene database, a configuration sampling unit, a verification scene generation and conversion unit, a scene configuration unit, a data acquisition and analysis processing unit, a verification statistics unit and a random seed storage unit.
The application scene database is used for recording all application scenes to be verified of the chip; the application scene database is stored in an excel format and is manually input by a verifier or a chip developer; the application scenario described herein refers to, for example, in verification of a chip in an air conditioner application, an application mode of the air conditioner includes refrigeration, drying, heating, and ventilation, where "refrigeration", "drying", "ventilation", and "heating" are each an application scenario.
The configuration sampling unit is used for recording sampling conditions of each configuration corresponding to each application scene; the sampling conditions comprise the value ranges of each configuration and sampling intervals.
The above-mentioned value range refers to, for example, in the verification of the above-mentioned chip, each configuration under various application modes includes configuring A-temperature, configuring B-wind speed; when the application scene is refrigeration, the value range of the configuration A is 15-30 ℃, and the value range of the configuration B is 0-4 (wherein 0-wind speed 1 gear, 1-wind speed 2 gear, 2-wind speed 3 gear, 3-wind speed 4 gear and 4-wind speed 5 gear); when the application scene is heating, the value range of the configuration A is 26-35 ℃, and the value range of the configuration B is 0-4.
The sampling interval refers to, for example, that the sampling interval of configuration a is 1 ℃, i.e. sampling is performed at intervals of 1 ℃ within the range of the value of configuration a; for example, the sampling interval of configuration A is 2 ℃, i.e. sampling is performed at intervals of 2 ℃ within the range of the value of configuration A.
It can be known that under a certain application scene, according to the different values of the configuration a and the configuration B, there may be a plurality of combinations, each combination being a verification scene; the number of the combination of the configuration A and the configuration B is determined according to the sampling interval of the configuration A and the configuration B; of course, the sampling interval is flexibly adjusted by the verifier according to the verification load of the whole chip and the verification requirement. The application scenario here also serves as a configuration of the verification scenario.
The verification scene generation and conversion unit is connected with the application scene database and the scene configuration unit, various verification scenes to be verified are automatically generated according to each application scene of the application scene database, all configurations of each verification scene are subjected to format conversion, and data after format conversion are stored in the scene configuration unit; the verification scene generation and conversion unit is connected with the verification statistics unit and the data acquisition and analysis processing unit; the verification statistics unit acquires all verification scenes generated by the verification scene generation and conversion unit and is used for counting verification information of all verification scenes.
Specifically, the verification scene generation and conversion unit identifies an application scene in the application scene database through the VBA, and generates the verification scenes one by combining sampling conditions configuring each configuration of the application scene in the configuration sampling unit. The verification scene generation and conversion unit performs format conversion on all configurations of each verification scene into SV language and stores the SV language into the scene configuration unit; the data format required for verifying the statistical unit is a user oriented data format, such as an excel format.
In other embodiments, the sampling unit may not be configured, and at this time, each application scene in the application scene database and the verification scene are in a one-to-one correspondence relationship, that is, the application scene is split by a person and input into the application scene database, and the verification scene generation and conversion unit only needs to convert the data formats of various application scenes; the application scenes at this time can be the refrigeration, the temperature of 20 degrees and the wind speed of 1 level, but under the condition, when the difference between certain application scenes is only the value of certain configurations is different (such as the temperature), the workload of manual input is huge, errors are easy to occur, and the situation of combination missing is easy to occur; the configuration sampling unit is adopted, the verification scene generation and the conversion unit are matched, various verification scenes are automatically generated, labor can be effectively saved, the accuracy is high, and later modification is facilitated.
A scene configuration unit for providing various parameters required in verification for the verification environment; the data of the scene configuration unit is expressed in the form of SV language (SystemVerilog) and can be directly input into a verification environment to provide parameters during verification for the verification environment; the verification scene configuration unit is connected with the verification environment through a software interface; in this way, the scene configuration unit can be connected to the verification environment, and the independence and compatibility of the auxiliary environment of the invention can be ensured. When the verification environment is maintained, only the application scene database and the configuration sampling unit are planned, and the verification environment is not required to be changed.
The verification statistics unit is used for counting verification information of each verification scene, and the verification information comprises verification times and verification results of the verification scenes, so that verification conditions of each verification scene can be checked at any time in the verification statistics unit at a later stage. The authentication statistics unit is stored here in a user oriented format, such as an excel format.
The data acquisition and analysis processing unit is used for acquiring specific data of each configuration in the verification environment, wherein specific acquisition items are provided by the verification scene generation and conversion unit, the data acquisition and analysis processing unit carries out combination record on each configuration to restore a verification scene, verification information of the verification scene in the verification statistics unit is updated, if the verification scene is not in the verification statistics unit, data of the verification scene is added in the verification statistics unit, and at the moment, the verification scene is an illegal verification scene; the data acquisition and analysis processing unit judges whether each verification scene is fully verified according to the information stored in the verification statistics unit, one verification scene is randomly selected out of the fully verified verification scenes (by generating verification random seeds, each verification scene corresponds to one random seed), the data acquisition and analysis processing unit sends the random seeds to the scene configuration unit, and the scene configuration unit selects each configuration of the verification scene corresponding to the random seed and sends the configuration to the verification environment for verification; and sequentially cycling until all verification scenes are verified.
When the random seeds generated by the data acquisition and analysis processing unit do not have corresponding verification scenes, the scene configuration unit randomly selects combinations of the configurations to form an illegal verification environment for verifying the verification environment; and the verification statistical unit also uses and records verification information of the illegal verification environment.
The fact that the verification scenes are not verified sufficiently means that verification scenes are not verified or verification times are small. Because the random seed has a larger value range and strong randomness, the obtained random seed is easy to generate no corresponding verification scene, at the moment, the scene configuration unit randomly selects the combination of each configuration to verify the verification environment, for example, the combination of each configuration selected randomly is 'heating +0 ℃ plus wind speed 1 gear' (in the verification scene, no information of the combination is contained), and after the verification of the verification environment is completed, the data acquisition and analysis processing unit acquires various information and stores the information in the verification statistics unit.
And the random seed storage unit is used for storing the random seeds of the verification scenes and macro definitions of verification scene verification so as to reproduce verification conditions and processes of the verification scenes according to the random seeds and the macro definitions at a later stage.
The auxiliary environment can automatically generate all verification scenes according to the settings and convert the verification scenes into languages which can be identified by the verification environment; and the verification condition of each verification scene can be judged, and for the verification scenes with insufficient verification, the verification can be preferentially selected, so that the complete verification times of verification, such as 100 verification scenes for the verification of a certain chip, can be covered by 100 verification scenes only after 500 or more verifications in the previous verification process, and the auxiliary environment can finish the verification of all the verification scenes at least by only 100 verification workload, thereby greatly improving the verification speed and accelerating the development progress of the chip.
In addition, the auxiliary environment has independence and compatibility, and for a verifier, the application scene database, the configuration sampling unit and the embedding of a software interface for carrying out data interaction between the auxiliary environment and the verification environment can be completed; under the cooperation of the auxiliary environment and the verification environment, the verification environment can automatically and rapidly complete the verification work of all verification scenes.
The invention also provides a chip verification system which comprises a verification environment and the chip verification auxiliary environment.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. without being creatively made are included in the protection scope of the present invention.
Claims (12)
1. The chip verification auxiliary environment is used for being matched with the chip verification environment to carry out automatic verification of the chip; the chip verification auxiliary environment is characterized by comprising an application scene database, a verification scene generation and conversion unit, a scene configuration unit and a data acquisition and analysis processing unit;
the application scene database is used for recording all application scenes of the chip;
the verification scene generation and conversion unit is connected with the application scene database and the scene configuration unit, various verification scenes to be verified are automatically generated according to each application scene of the application scene database, all configurations of each verification scene are subjected to format conversion, and data after format conversion are stored in the scene configuration unit;
the data acquisition and analysis processing unit is connected with the scene configuration unit and the verification environment; the data acquisition and analysis processing unit is used for generating random seeds and sending the random seeds to the scene configuration unit; the data acquisition and analysis processing unit is also used for acquiring the verification result of the verification scene in the verification environment, and when the verification of a certain verification scene is completed, the data acquisition and analysis processing unit generates another random seed;
the scene configuration unit is connected with the verification environment, selects one verification scene according to the random seed, and sends various configurations of the verification scene to the verification environment to verify the verification scene.
2. The chip authentication auxiliary environment according to claim 1, further comprising a configuration sampling unit for storing sampling conditions for recording each configuration corresponding to each application scenario; and the verification scene generation and conversion unit automatically generates various verification scenes to be verified according to each application scene of the application scene database and the sampling conditions.
3. The chip authentication assistance environment of claim 2, wherein the sampling conditions comprise a range of values for each configuration and a sampling interval.
4. The chip authentication auxiliary environment according to claim 3, wherein the application scene database is in an Excel format, the authentication scene generation and conversion unit identifies an application scene in the application scene database through VBA, and generates the authentication scenes one by one in combination with sampling conditions configuring each configuration of the application scene in the configuration sampling unit.
5. The chip authentication assistance environment according to claim 1, further comprising an authentication statistics unit; the verification scene generation and conversion unit is connected with the verification statistics unit and the data acquisition and analysis processing unit; the verification statistics unit acquires all verification scenes generated by the verification scene generation and conversion unit and is used for counting verification results of all verification scenes; the data acquisition and analysis processing unit acquires all configurations in the verification environment according to the verification scene generation and conversion unit, combines the acquired configurations to restore a verification scene, and updates the verification result of the verification scene in the verification statistics unit.
6. The chip authentication assistance environment according to claim 5, wherein the authentication statistics unit is further configured to count the number of times of authentication of each authentication scenario.
7. The chip authentication auxiliary environment according to claim 5, wherein the authentication scene generation and conversion unit converts formats of all configurations of each authentication scene of the scene configuration unit into SV language, and the language format of the data stored by the scene configuration unit is SV language; and the data storage format of the verification statistical unit is an excel format.
8. The chip authentication assistance environment of claim 5, further comprising a random seed storage unit, coupled to the data acquisition and analysis processing unit, for storing random seeds corresponding to each authentication scenario during authentication.
9. The chip authentication assistance environment according to claim 5, wherein the data collection and analysis processing unit further determines whether each authentication scene is sufficiently authenticated according to the information stored in the authentication statistics unit, and the random seed generated by the data collection and analysis processing unit is used for randomly generating one authentication scene for authentication in addition to the sufficiently authenticated authentication scene.
10. The chip authentication auxiliary environment according to claim 6, wherein when the random seed generated by the data acquisition and analysis processing unit has no corresponding authentication scene, the scene configuration unit randomly selects combinations of configurations to form an illegal authentication environment for authentication; and the verification statistical unit is also used for recording verification results and verification times of the illegal verification environment.
11. The chip authentication assistance environment according to any one of claims 1 to 10, wherein the authentication scene configuration unit is connected to the authentication environment through a software interface; the data acquisition and analysis processing unit is connected with the verification environment through a software interface.
12. A chip verification system, comprising a verification environment and an auxiliary environment according to any one of claims 1 to 11, wherein the scene configuration unit of the auxiliary environment is connected to the verification environment, and the data acquisition and analysis processing unit of the auxiliary environment is connected to the verification environment.
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