CN110780994A - Method, equipment and medium for regulating and controlling memory - Google Patents
Method, equipment and medium for regulating and controlling memory Download PDFInfo
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- CN110780994A CN110780994A CN201910911388.3A CN201910911388A CN110780994A CN 110780994 A CN110780994 A CN 110780994A CN 201910911388 A CN201910911388 A CN 201910911388A CN 110780994 A CN110780994 A CN 110780994A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5022—Mechanisms to release resources
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/5011—Pool
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Abstract
The invention discloses a method for regulating and controlling a memory, which comprises the following steps: creating a father memory pool based on all memories; occupying a memory with a preset size from a father memory pool to create a child memory pool; judging whether the memory size of the sub memory pool can meet the current requirements of the system; responding to the situation that the memory size of the child memory pool cannot meet the current requirement of the system, and sending a memory request to the father memory pool; and the child memory pool receives the new memory allocated by the parent memory pool. The invention also discloses a computer device and a readable storage medium. The method, the device and the medium for regulating and controlling the memory realize dynamic change of the memory by matching the father memory pool and the son memory pool, fully utilize memory resources of the system, improve the response speed of writing data by a user and improve the read-write performance of the storage system.
Description
Technical Field
The present invention relates to the field of storage, and more particularly, to a method, device and readable medium for regulating and controlling a memory.
Background
The cache is a module in the storage device software system. When the data to be written into the disk array by the user passes through the cache module, the cache module caches the data and replies a storage success response to the user, and then the user data is written into the disk array. Compared with the response after the user data is written into the disk array, the response speed of the user data to be written into the disk array can be improved, the cache module has the read-hit and read-ahead functions to improve the response speed of the storage to the user command to be read, and the read-write speed performance of the storage device can be improved by the cache write-data, read-hit and read-ahead functions.
The larger the memory occupied by the cache module is, the larger the data amount capable of being cached by the cache is, the more obvious the functions of caching data writing, reading hit and pre-reading are exerted, and the more obvious the improvement on the read-write performance of the storage device is. However, other software modules are still in the storage device software system, if the cache module occupies all or too much system memory during initialization, other software modules cannot be allocated to enough memory, and thus other software modules cannot run; if too little memory is occupied by the cache module, the performance of the storage system is poor, so how to set the system memory occupied by the cache module is a more important problem.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method, a device, and a medium for regulating and controlling a memory, which implement dynamic change of the memory by using a parent memory pool and a child memory pool in a coordinated manner, fully utilize system memory resources, improve response speed for user write data, and improve read-write performance of a storage system.
Based on the above object, an aspect of the embodiments of the present invention provides a method for regulating and controlling a memory, including the following steps: creating a father memory pool based on all memories; occupying a memory with a preset size from a father memory pool to create a child memory pool; judging whether the memory size of the sub memory pool can meet the current requirements of the system; responding to the situation that the memory size of the child memory pool cannot meet the current requirement of the system, and sending a memory request to the father memory pool; and the child memory pool receives the new memory allocated by the parent memory pool.
In some embodiments, determining whether the memory size of the sub memory pool can meet the current needs of the system includes: and monitoring the current available memory size of the sub memory pool, and judging whether the current available memory size of the sub memory pool is smaller than a threshold value.
In some embodiments, further comprising: and judging whether the current available memory size of the sub memory pool is larger than a preset size.
In some embodiments, further comprising: and returning the new memory allocated by the father memory pool to the father memory pool in response to the fact that the size of the current available memory of the child memory pool is larger than the preset size.
In some embodiments, sending the memory request to the parent memory pool comprises: and determining the current maximum available memory of the sub memory pool according to the current maximum available memory of the father memory pool.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: creating a father memory pool based on all memories; occupying a memory with a preset size from a father memory pool to create a child memory pool; judging whether the memory size of the sub memory pool can meet the current requirements of the system; responding to the situation that the memory size of the child memory pool cannot meet the current requirement of the system, and sending a memory request to the father memory pool; and the child memory pool receives the new memory allocated by the parent memory pool.
In some embodiments, determining whether the memory size of the sub memory pool can meet the current needs of the system includes: and monitoring the current available memory size of the sub memory pool, and judging whether the current available memory size of the sub memory pool is smaller than a threshold value.
In some embodiments, the steps further comprise: and judging whether the current available memory size of the sub memory pool is larger than a preset size.
In some embodiments, the steps further comprise: and returning the new memory allocated by the father memory pool to the father memory pool in response to the fact that the size of the current available memory of the child memory pool is larger than the preset size.
In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has the following beneficial technical effects: by using the parent memory pool and the child memory pool in a matching way, the dynamic change of the memory is realized, the memory resources of the system are fully utilized, the response speed of writing data by a user is improved, and the read-write performance of the storage system is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic diagram illustrating an embodiment of a method for regulating a memory according to the present invention;
fig. 2 is a flowchart of a method for regulating a memory according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the foregoing, a first aspect of the embodiments of the present invention provides an embodiment of a method for regulating and controlling a memory. Fig. 1 is a schematic diagram illustrating an embodiment of a method for regulating a memory according to the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:
s1, creating a father memory pool based on all memories;
s2, occupying a memory with a preset size from the father memory pool to create a child memory pool;
s3, judging whether the memory size of the sub memory pool can meet the current needs of the system;
s4, responding to the situation that the memory size of the child memory pool can not meet the current needs of the system, and sending a memory request to the father memory pool; and
and S5, the child memory pool receives the new memory allocated by the father memory pool.
A parent memory pool is created based on all memories. And when the memory module of the storage device software system is initialized, a father memory pool is created, the father memory pool comprises all memories which can be occupied by the software system, and other software modules in the storage device software system apply for memories from the father memory pool. The available memory size in the current parent memory pool can be recorded by a base _ available variable in the parent memory pool, and the memory size which is applied by each module of the software system can be recorded by a base _ reserve variable.
Occupying a predetermined size of memory from the parent memory pool to create a child memory pool. In the embodiment of the present invention, the predetermined size may be set to 4G, that is, the child memory pool applies for a memory of 4G size from the parent memory pool, and the base _ available variable in the parent memory pool is reduced by 4G.
The child memory pool may record the size of the memory available in the current child memory pool through a child _ available variable, and may record the size of the memory already used in the cache module through a child _ reserve variable. In some embodiments, the current maximum available memory of the child memory pool is positively correlated with the current maximum available memory of the parent memory pool. Sending the memory request to the parent memory pool includes: and determining the current maximum available memory of the sub memory pool according to the current maximum available memory of the father memory pool. The maximum value of the available memory of the cache module is the value of child _ available variable of the child memory pool plus the value of base _ available variable of the father memory pool, when the value of the base _ available variable in the father pool is reduced due to the memory occupied by other modules in the software system, the maximum value of the available memory of the cache module is reduced, and when the value of the base _ available variable in the father pool is increased due to the memory released by other modules in the software system to the father pool, the maximum value of the available memory of the cache module is increased.
And judging whether the memory size of the sub memory pool can meet the current requirement of the system. In some embodiments, determining whether the memory size of the sub memory pool can meet the current needs of the system includes: and monitoring the current available memory size of the sub memory pool, and judging whether the current available memory size of the sub memory pool is smaller than a threshold value. For example, the threshold may be set to 1G, and when the currently available memory size of the sub memory pool is smaller than 1G, it may be determined that the current needs of the system cannot be met.
And responding to the condition that the memory size of the child memory pool cannot meet the current needs of the system, and sending a memory request to the father memory pool. If the memory size of the child memory pool cannot meet the current needs of the system, a new memory space can be applied to the parent memory pool, for example, a new memory space of 1G can be applied to the parent memory pool again. When the memory size of the child memory pool is detected again to be incapable of meeting the current needs of the system, a new memory space can be applied to the father memory pool again.
And when the memory occupied by the cache module is used up, releasing the memory to the sub memory pool. In some embodiments, further comprising: and judging whether the current available memory size of the sub memory pool is larger than a preset size. In some embodiments, further comprising: and returning the new memory allocated by the father memory pool to the father memory pool in response to the fact that the size of the current available memory of the child memory pool is larger than the preset size. When the cache module releases more memory, the memory space occupied by the child memory pool may be too large, and the redundant memory space needs to be returned to the parent memory pool. For example, when the cache module releases the memory while occupying more memory in the parent pool, the variable a may be used to record the child _ available value when the child memory pool is initialized, and when the cache module continuously releases the resource, which results in the child _ available value being greater than the variable a, in this embodiment, that is, when the currently available memory in the child memory pool is greater than 4G, the child memory pool may return the resource occupying the parent memory pool to the parent memory pool, and the parent memory pool base _ available variable increases a corresponding value.
Fig. 2 is a flowchart illustrating an embodiment of a method for regulating a memory according to the present invention. As shown in FIG. 2, beginning at block 101 and proceeding to block 102, a parent memory pool is created based on all memory; continuing to block 103, occupying a predetermined size of memory from the parent memory pool to create a child memory pool; then, go to block 104, determine whether the memory size of the child memory pool can meet the current needs of the system, if yes, go to block 105, send a memory request to the parent memory pool, then go to block 106, the child memory pool receives the new memory allocated by the parent memory pool, and then go to block 109 to end; if the memory size of the child memory pool cannot meet the current needs of the system, go to block 107, determine whether the current available memory size of the child memory pool is larger than a predetermined size, if so, go to block 108, return the new memory allocated by the parent memory pool to the parent memory pool, then go to block 109 to end, if not, end directly.
The embodiment of the invention realizes the dynamic change of the cache size by adopting a method of mutually combining the father memory pool and the son memory pool. When a system memory module is initialized, all applicable memories are stored in a father memory pool, after the system memory module is initialized, when a cache module is initialized, a child memory pool corresponding to the cache module is created and a configured amount of memories are applied from the father memory pool, the maximum upper limit of the usable memories of the cache module is the sum of the applied memories in the child memory pool and the memories not occupied by other modules in the father pool, when the memories of the father memory pool occupied by other modules are increased, the usable memories in the father memory pool are decreased, so that the usable maximum memories of the cache module are decreased, and otherwise, when the memories of the father memory pool occupied by other modules are decreased, the usable memories in the father pool are increased, so that the usable memories of the cache module are increased.
It should be particularly noted that, in the embodiments of the method for regulating a memory, steps of the method for regulating a memory may be intersected, replaced, added, or deleted, and therefore, the method for regulating a memory by reasonable permutation and combination conversion shall also belong to the scope of the present invention, and shall not limit the scope of the present invention to the embodiments.
In view of the above object, a second aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, creating a father memory pool based on all memories; s2, occupying a memory with a preset size from the father memory pool to create a child memory pool; s3, judging whether the memory size of the sub memory pool can meet the current needs of the system; s4, responding to the situation that the memory size of the child memory pool can not meet the current needs of the system, and sending a memory request to the father memory pool; and S5, the child memory pool receives the new memory allocated by the father memory pool.
In some embodiments, determining whether the memory size of the sub memory pool can meet the current needs of the system includes: and monitoring the current available memory size of the sub memory pool, and judging whether the current available memory size of the sub memory pool is smaller than a threshold value.
In some embodiments, further comprising: and judging whether the current available memory size of the sub memory pool is larger than a preset size.
In some embodiments, further comprising: and returning the new memory allocated by the father memory pool to the father memory pool in response to the fact that the size of the current available memory of the child memory pool is larger than the preset size.
In some embodiments, the current maximum available memory of the child memory pool is positively correlated with the current maximum available memory of the parent memory pool.
The invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs the method as above.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the method for regulating and controlling memory can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods as described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method for regulating and controlling a memory is characterized by comprising the following steps:
creating a father memory pool based on all memories;
occupying a memory with a preset size from the father memory pool to create a child memory pool;
judging whether the memory size of the sub memory pool can meet the current requirement of the system;
responding to the situation that the memory size of the child memory pool cannot meet the current needs of the system, and sending a memory request to the father memory pool; and
and the child memory pool receives the new memory allocated by the father memory pool.
2. The method according to claim 1, wherein said determining whether the memory size of the sub memory pool can meet the current needs of the system comprises:
and monitoring the current available memory size of the sub memory pool, and judging whether the current available memory size of the sub memory pool is smaller than a threshold value.
3. The method of claim 1, further comprising:
and judging whether the current available memory size of the sub memory pool is larger than the preset size.
4. The method of claim 3, further comprising:
and returning the new memory allocated by the father memory pool to the father memory pool in response to the fact that the current available memory size of the child memory pool is larger than the preset size.
5. The method of claim 1, wherein sending a memory request to the parent memory pool comprises: and determining the current maximum available memory of the child memory pool according to the current maximum available memory of the father memory pool.
6. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of:
creating a father memory pool based on all memories;
occupying a memory with a preset size from the father memory pool to create a child memory pool;
judging whether the memory size of the sub memory pool can meet the current requirement of the system;
responding to the situation that the memory size of the child memory pool cannot meet the current needs of the system, and sending a memory request to the father memory pool; and
and the child memory pool receives the new memory allocated by the father memory pool.
7. The computer device according to claim 6, wherein said determining whether the memory size of the sub memory pool can meet the current needs of the system comprises:
and monitoring the current available memory size of the sub memory pool, and judging whether the current available memory size of the sub memory pool is smaller than a threshold value.
8. The computer device of claim 6, wherein the steps further comprise:
and judging whether the current available memory size of the sub memory pool is larger than the preset size.
9. The computer device of claim 8, wherein the steps further comprise:
and returning the new memory allocated by the father memory pool to the father memory pool in response to the fact that the current available memory size of the child memory pool is larger than the preset size.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 5.
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| CN201910911388.3A CN110780994A (en) | 2019-09-25 | 2019-09-25 | Method, equipment and medium for regulating and controlling memory |
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| CN201910911388.3A CN110780994A (en) | 2019-09-25 | 2019-09-25 | Method, equipment and medium for regulating and controlling memory |
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| CN111581288A (en) * | 2020-05-07 | 2020-08-25 | 苏州浪潮智能科技有限公司 | Object cloning method, system, device and medium |
| CN112181637A (en) * | 2020-09-10 | 2021-01-05 | 苏州浪潮智能科技有限公司 | Memory resource allocation method and device |
| CN112416569A (en) * | 2020-09-17 | 2021-02-26 | 上海哔哩哔哩科技有限公司 | Cache memory adjusting method and device and computer equipment |
| CN113553195A (en) * | 2021-09-22 | 2021-10-26 | 苏州浪潮智能科技有限公司 | Memory pool resource sharing method, device, equipment and readable medium |
-
2019
- 2019-09-25 CN CN201910911388.3A patent/CN110780994A/en not_active Withdrawn
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| CN111581288A (en) * | 2020-05-07 | 2020-08-25 | 苏州浪潮智能科技有限公司 | Object cloning method, system, device and medium |
| CN111581288B (en) * | 2020-05-07 | 2023-01-06 | 苏州浪潮智能科技有限公司 | Object cloning method, system, device and medium |
| CN112181637A (en) * | 2020-09-10 | 2021-01-05 | 苏州浪潮智能科技有限公司 | Memory resource allocation method and device |
| CN112181637B (en) * | 2020-09-10 | 2022-11-11 | 苏州浪潮智能科技有限公司 | Memory resource allocation method and device |
| CN112416569A (en) * | 2020-09-17 | 2021-02-26 | 上海哔哩哔哩科技有限公司 | Cache memory adjusting method and device and computer equipment |
| CN112416569B (en) * | 2020-09-17 | 2022-12-06 | 上海哔哩哔哩科技有限公司 | Cache memory adjusting method and device and computer equipment |
| CN113553195A (en) * | 2021-09-22 | 2021-10-26 | 苏州浪潮智能科技有限公司 | Memory pool resource sharing method, device, equipment and readable medium |
| WO2023045250A1 (en) * | 2021-09-22 | 2023-03-30 | 苏州浪潮智能科技有限公司 | Memory pool resource sharing method and apparatus, and device and readable medium |
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