CN110780108A - Peak detection unit, detection system and detection method - Google Patents

Peak detection unit, detection system and detection method Download PDF

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Publication number
CN110780108A
CN110780108A CN201911175147.3A CN201911175147A CN110780108A CN 110780108 A CN110780108 A CN 110780108A CN 201911175147 A CN201911175147 A CN 201911175147A CN 110780108 A CN110780108 A CN 110780108A
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port
pin
tested
diode
output
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黄金星
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Guangdong Shenghe Technology Co Ltd
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Guangdong Shenghe Technology Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/04—Measuring peak values or amplitude or envelope of ac or of pulses
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
    • G01R19/16576—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

The invention relates to a peak detection unit, a detection system and a detection method, which are used for detecting whether an ESD diode in a chip to be detected is damaged or not. The positive input end of a first operational amplifier A1 included in the peak detection unit is electrically connected with the input port P1, the negative input end of a first operational amplifier A1 is electrically connected with the VSS port P5, and the output end of the first operational amplifier A1 is electrically connected with the pin connection port P3; the positive input end of the second operational amplifier a2 is grounded through the charge-discharge capacitor C, and the positive input end of the second operational amplifier a2 is also electrically connected to the VDD port P4; the negative input terminal of the second operational amplifier a2 and the output terminal of the second operational amplifier a2 are both electrically connected to the output port P2, one end of the resistor R is electrically connected to the VSS port P5, and the other end of the resistor R is electrically connected to the output port P2. The invention can quickly judge whether the two diodes connected with the test pin are normal or not, thereby effectively reducing the detection time.

Description

Peak detection unit, detection system and detection method
Technical Field
The invention relates to the technical field of electrostatic discharge testing, in particular to a peak detection unit, a detection system and a detection method.
Background
By Electro-Static Discharge (ESD), it is meant the transfer of charge caused by objects with different electrostatic potentials coming into close proximity or direct contact with each other. During use of the chip, static electricity is inevitably generated, for example, by hand holding or rubbing with the apparatus. In this process, electrostatic discharge can be caused, and instantaneous voltage of kilovolt can be generated, so that electrostatic damage can be caused, internal circuits can be damaged, and the chip can be damaged.
Common electrostatic discharge modes include a Human Body discharge mode (HBM) and a Machine discharge mode (MM). In order to avoid electrostatic damage, an ESD protection circuit is added at the pin position of the chip, as shown in fig. 1, which is formed by connecting two ESD diodes (ESD diodes). At present, when the ESD diodes are tested to be damaged or not, because the pins of some chips to be tested are too many, the test period is longer, and because the same pin comprises two ESD diodes, two test operations are needed, so that the time cost is increased.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the peak detection unit, the detection system and the detection method are used for detecting whether an ESD diode in a chip to be detected is damaged or not, the detection is convenient and quick, and the detection time is effectively reduced.
The technical scheme adopted by the invention for solving the technical problems is as follows: a peak detection unit is used for detecting whether an ESD diode in a chip to be detected is damaged or not, and particularly comprises a first operational amplifier A1, a second operational amplifier A2, a charge-discharge capacitor C, a resistor R, an input port P1, an output port P2, a pin connection port P3, a VDD port P4 and a VSS port P5.
The positive input end of the first operational amplifier A1 is electrically connected with the input port P1, the negative input end of the first operational amplifier A1 is electrically connected with the VSS port P5, and the output end of the first operational amplifier A1 is electrically connected with the pin connection port P3; the positive input end of the second operational amplifier a2 is grounded through the charge-discharge capacitor C, and the positive input end of the second operational amplifier a2 is electrically connected to the VDD port P4; the negative input terminal of the second operational amplifier a2 and the output terminal of the second operational amplifier a2 are both electrically connected to the output port P2, one end of the resistor R is electrically connected to the VSS port P5, and the other end of the resistor R is electrically connected to the output port P2.
The VDD port P4 is used for being electrically connected with a VDD pin of a chip to be tested, the VSS port P5 is used for being electrically connected with a VSS pin of the chip to be tested, the pin connection port P3 is used for being electrically connected with the pin to be tested of the chip to be tested, the input port P1 is used for being connected with an external signal generator, the external signal generator inputs sine voltage through the input port P1, the output port P2 is used for being connected with a judging unit, and the judging unit judges whether output waveforms are normal or not.
Preferably, the first operational amplifier a1, the second operational amplifier a2, the charge/discharge capacitor C, and the resistor R of the peak detection unit are all replaceable modules.
A detection system for detecting whether an ESD diode in a chip to be detected is damaged by using the peak detection unit comprises: the main control module and the test board module.
The main control module comprises: the device comprises a data processing unit, an MCU (microprogrammed control unit), a judging unit and a switch control unit, wherein the test board module comprises a peak value detection unit, a relay unit and pin access equipment; the pin access equipment is used for accessing each pin of the chip to be tested.
The data processing unit receives user setting data output from an external operation unit, the MCU controller reads the user setting data in the data processing unit, the MCU controller sends a signal generation command to the external signal generator according to the user setting data, the MCU controller sends a switch signal to the switch control unit according to the user setting data, the external signal generator generates a sine voltage signal as an input signal of the peak detection unit according to the signal generation command, and the switch control unit controls a corresponding relay switch in the relay unit to be attracted and conducted according to the switch signal so that a corresponding port of the peak detection unit is electrically connected with a corresponding pin of a chip to be detected; the judging unit judges the output waveform of the peak value detecting unit and feeds back the judging result to the MCU controller.
A method for detecting whether an ESD diode in a chip to be tested is damaged or not by using the peak detection unit,
the chip to be tested is provided with a VDD pin, a VSS pin and at least one pin to be tested, the pin to be tested is connected with an ESD protection circuit, the ESD protection circuit comprises a diode D1 and a diode D2, the anode of the diode D1 is connected with the VSS pin, the cathode of the diode D2 is connected with the VDD pin, and the cathode of the diode D1 and the anode of the diode D2 are connected with the pin to be tested.
The method comprises the following steps:
selecting a pin to be tested, wherein a peak detection unit VDD port P4 is communicated with a VDD pin of a chip to be tested, a VSS port P5 is communicated with a VSS pin of the chip to be tested, a pin connection port P3 is communicated with the pin to be tested of the chip to be tested, an input port P1 is connected with an external signal generator, a sinusoidal voltage with a peak value larger than the conduction voltage of a diode D1 and a diode D2 is input through the input port P1 by the external signal generator, an output port P2 is connected with a judgment unit, and the judgment unit judges whether an output waveform is normal or not;
judging whether the output voltage of the output port P2 is the peak voltage, if so, further judging whether the output voltage of the output port P2 is the stable peak voltage;
if the output voltage of the output port P2 is not the peak voltage, it indicates that the diode D2 connected to the pin to be tested is damaged;
if the output voltage of the output port P2 is a stable peak voltage, it indicates that the diode D1 and the diode D2 connected to the test pin are normal;
if the output voltage of the output port P2 is not the stable peak voltage, it indicates that the diode D1 connected to the pin to be tested is damaged.
The invention has the beneficial effects that: by adopting the peak value detection unit, the detection system and the detection method, whether the two diodes connected with the test pin are normal can be quickly judged, and which diode is damaged can be quickly confirmed, so that the detection is convenient and quick, and the detection time is effectively reduced.
Drawings
The invention is further described below with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a pin under test of a chip under test connected to an ESD protection circuit according to an exemplary embodiment of the present application;
fig. 2 is a schematic diagram of a connection between a chip to be tested and a peak detection unit according to an exemplary embodiment of the present application;
FIG. 3 is a specific circuit diagram of a chip under test and a peak detection unit after connection according to an exemplary embodiment of the present application;
FIG. 4 is a flow chart of a detection method in an exemplary embodiment of the present application;
FIG. 5 is a graph of a sinusoidal voltage waveform input by the external signal generator;
fig. 6 is a waveform diagram in which the output voltage of the output port P2 is not the peak voltage;
fig. 7 is a waveform diagram in which the output voltage of the output port P2 is a stable peak voltage;
fig. 8 is a waveform diagram in which the output voltage of the output port P2 is not a stable peak voltage;
FIG. 9 is a functional block diagram of a detection system in accordance with an exemplary embodiment of the present application;
FIG. 10 is a schematic diagram of the detection steps of the detection system of the exemplary embodiment of the present application;
fig. 11 is a schematic view of a partial connection of a switch control unit and a relay unit according to an exemplary embodiment of the present application;
Detailed Description
The invention will now be further described with reference to the accompanying drawings. These drawings are simplified schematic diagrams only illustrating the basic structure of the present invention in a schematic manner, and thus show only the constitution related to the present invention.
As shown in fig. 1 and 2, the chip to be tested has a VDD pin, a VSS pin, and at least one pin to be tested, the pin to be tested is connected to the ESD protection circuit, the ESD protection circuit includes a diode D1 and a diode D2, an anode of the diode D1 is connected to the VSS pin, a cathode of the diode D2 is connected to the VDD pin, and a cathode of the diode D1 and an anode of the diode D2 are connected to the pin to be tested. The diodes D1 and D2 are ESD diodes.
As shown in fig. 2 and 3, a peak detection unit 300 is used for detecting whether an ESD diode in a chip to be tested is damaged, and includes a first operational amplifier a1, a second operational amplifier a2, a charging/discharging capacitor C, a resistor R, an input port P1, an output port P2, a pin connection port P3, a VDD port P4, and a VSS port P5.
As shown in fig. 3, the positive input terminal of the first operational amplifier a1 is electrically connected to the input port P1, the negative input terminal of the first operational amplifier a1 is electrically connected to the VSS port P5, and the output terminal of the first operational amplifier a1 is electrically connected to the pin connection port P3; the positive input end of the second operational amplifier a2 is grounded through the charge-discharge capacitor C, and the positive input end of the second operational amplifier a2 is electrically connected to the VDD port P4; the negative input terminal of the second operational amplifier a2 and the output terminal of the second operational amplifier a2 are both electrically connected to the output port P2, one end of the resistor R is electrically connected to the VSS port P5, and the other end of the resistor R is electrically connected to the output port P2.
The VDD port P4 is used for being electrically connected with a VDD pin of a chip to be tested, the VSS port P5 is used for being electrically connected with a VSS pin of the chip to be tested, the pin connection port P3 is used for being electrically connected with the pin to be tested of the chip to be tested, the input port P1 is used for being connected with an external signal generator, the external signal generator inputs sine voltage through the input port P1, the output port P2 is used for being connected with a judging unit, and the judging unit judges whether output waveforms are normal or not.
The first operational amplifier A1, the second operational amplifier A2, the charge-discharge capacitor C and the resistor R of the peak detection unit are all replaceable modules. The devices are designed into replaceable modules, and the devices with corresponding specifications can be selected according to the specific model of the ESD protection circuit of the chip to be detected, so that the compatibility of the peak detection unit is improved.
As shown in fig. 4, a method for detecting whether an ESD diode in a chip under test is damaged by using the peak detecting unit,
the method comprises the following steps:
selecting a pin to be tested, wherein a peak detection unit VDD port P4 is communicated with a VDD pin of a chip to be tested, a VSS port P5 is communicated with a VSS pin of the chip to be tested, a pin connection port P3 is communicated with the pin to be tested of the chip to be tested, an input port P1 is connected with an external signal generator, a sinusoidal voltage with a peak value larger than the conduction voltage of a diode D1 and a diode D2 is input through the input port P1 by the external signal generator, an output port P2 is connected with a judgment unit, and the judgment unit judges whether an output waveform is normal or not;
judging whether the output voltage of the output port P2 is the peak voltage, if so, further judging whether the output voltage of the output port P2 is the stable peak voltage;
if the output voltage of the output port P2 is not the peak voltage, it indicates that the diode D2 connected to the pin to be tested is damaged;
if the output voltage of the output port P2 is a stable peak voltage, it indicates that the diode D1 and the diode D2 connected to the test pin are normal;
if the output voltage of the output port P2 is not the stable peak voltage, it indicates that the diode D1 connected to the pin to be tested is damaged.
The external signal generator inputs a periodic sinusoidal voltage as shown in fig. 5. If the output voltage of the output port P2 is not the peak voltage, as shown in fig. 6, it indicates that the diode D2 connected to the pin to be tested is damaged. If the output voltage of the output port P2 is a stable peak voltage, as shown in fig. 7, it indicates that the diodes D1 and D2 connected to the test pin are normal. If the output voltage of the output port P2 is not the stable peak voltage, as shown in fig. 8, it indicates that the diode D1 connected to the pin under test is damaged. The detection method can quickly judge whether the diode D1 and the diode D2 connected with the test pin are normal or not and can quickly confirm which diode is damaged. The detection time is greatly reduced.
As shown in fig. 9, a detection system for detecting whether an ESD diode in a chip to be detected is damaged by using the peak detection unit includes: a main control module 201 and a test board module 202;
the main control module 201 includes: the testing board module 202 comprises a peak detection unit 2020, a relay unit 2021 and a pin access device 2022; the pin access equipment is used for accessing a pin of a chip to be tested;
the data processing unit 2010 receives user setting data output from the external operation unit 200, the MCU controller 2011 reads the user setting data in the data processing unit 2010, the MCU controller 2011 sends a signal generation command to the external signal generator 203 according to the user setting data, the MCU controller 2011 sends a switch signal to the switch control unit 2013 according to the user setting data, the external signal generator 203 generates a sinusoidal voltage signal according to the signal generation command as an input signal of the peak detection unit, and the switch control unit 2013 controls the corresponding relay switch in the relay unit 2021 to be attracted and conducted according to the switch signal, so that the corresponding port of the peak detection unit is electrically connected to the corresponding pin of the chip to be tested; the determination unit 2012 determines the output waveform of the peak detection unit 2020 and feeds back the determination result to the MCU controller.
As shown in fig. 10, the detection steps using the detection system include the following steps:
step 601: the data processing unit 2010 receives user setting data including test mode selection information, signal cycle information, peak value information, and the like from the operation unit. The test mode may be a continuous test mode or a single test mode. The method can be realized by switching the relay switch in the relay unit to change the pin to be tested, which is connected with the chip to be tested.
Step 602: the MCU controller 2011 reads the user setting data in the data processing unit 2010, and the MCU controller 2011 sends a signal generation command to the external signal generator 203 according to the user setting data;
step 603: the external signal generator 203 generates a sinusoidal voltage signal as an input signal of the peak detection unit according to the signal generation command;
step 604: the MCU controller 2011 sends a switching signal to the switching control unit 2013 according to the user setting data;
steps 605 and 606: the switch control unit 2013 controls the corresponding relay switch of the relay unit 2021 to be closed and conducted according to the switch signal, so that the corresponding port of the peak detection unit is electrically connected with the corresponding pin of the chip to be tested.
Step 607: the determination unit 2012 determines the output waveform of the peak detection unit 2020 and feeds back the determination result to the MCU controller.
Step 608: and the MCU controller feeds back the judgment result to the operation unit.
The switch control unit may adopt a triode as a switching device, the relay unit has a plurality of relays, as shown in fig. 11, a base of the triode is used for receiving a switching signal, an emitter of the triode is grounded, a collector of the triode is connected in series with a coil of a corresponding relay and then connected to a power VCC terminal, and two ends of the switch of the corresponding relay are used as leading-out terminals for respectively connecting each port of the peak detection unit and each corresponding pin of the chip to be tested. For example, the peak detection unit VDD port P4 and the VDD pin of the chip to be tested are respectively connected to two ends of a relay switch, and the corresponding transistor is turned on after receiving the switching signal, so that the corresponding relay coil is powered on, and the corresponding relay switch is pulled in, so that the peak detection unit VDD port P4 is communicated with the VDD pin of the chip to be tested. Other ports of the peak detection unit can be communicated with corresponding pins of the chip to be detected by adopting the mode. The mode is convenient for switching the pins to be tested in the chip to be tested, and is quick and convenient.
In light of the foregoing description of the preferred embodiment of the present invention, many modifications and variations will be apparent to those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.

Claims (5)

1. A peak detection unit is used for detecting whether an ESD diode in a chip to be detected is damaged or not, and is characterized in that: the peak detection unit comprises a first operational amplifier A1, a second operational amplifier A2, a charge-discharge capacitor C, a resistor R, an input port P1, an output port P2, a pin connection port P3, a VDD port P4 and a VSS port P5;
the positive input end of the first operational amplifier A1 is electrically connected with the input port P1, the negative input end of the first operational amplifier A1 is electrically connected with the VSS port P5, and the output end of the first operational amplifier A1 is electrically connected with the pin connection port P3; the positive input end of the second operational amplifier a2 is grounded through the charge-discharge capacitor C, and the positive input end of the second operational amplifier a2 is electrically connected to the VDD port P4; the negative input terminal of the second operational amplifier a2 and the output terminal of the second operational amplifier a2 are both electrically connected to the output port P2, one end of the resistor R is electrically connected to the VSS port P5, and the other end of the resistor R is electrically connected to the output port P2.
2. The peak detection unit according to claim 1, characterized in that: the VDD port P4 is used for being electrically connected with a VDD pin of a chip to be tested, the VSS port P5 is used for being electrically connected with a VSS pin of the chip to be tested, the pin connection port P3 is used for being electrically connected with the pin to be tested of the chip to be tested, the input port P1 is used for being connected with an external signal generator, the external signal generator inputs sine voltage through the input port P1, the output port P2 is used for being connected with a judging unit, and the judging unit judges whether output waveforms are normal or not.
3. The peak detection unit according to claim 1, characterized in that: the first operational amplifier A1, the second operational amplifier A2, the charge-discharge capacitor C and the resistor R of the peak detection unit are all replaceable modules.
4. A detection system for detecting whether an ESD diode in a chip under test is damaged by using the peak detection unit according to any one of claims 1 to 3, comprising: a main control module (201) and a test board module (202);
the master control module (201) comprises: the testing board module (202) comprises a peak value detection unit (2020), a relay unit (2021) and pin access equipment (2022);
the data processing unit (2010) receives user setting data output from an external operation unit, the MCU controller (2011) reads the user setting data in the data processing unit (2010), the MCU controller (2011) sends a signal generation command to the external signal generator (203) according to the user setting data, the MCU controller (2011) sends a switching signal to the switch control unit (2013) according to the user setting data, the external signal generator (203) generates a sine voltage signal as an input signal of the peak detection unit according to the signal generation command, and the switch control unit (2013) controls a corresponding relay switch in the relay unit (2021) to be attracted and conducted according to the switching signal, so that a corresponding port of the peak detection unit is electrically connected with a corresponding pin of a chip to be detected; the judging unit (2012) judges the output waveform of the peak value detecting unit (2020) and feeds back the judgment result to the MCU controller.
5. A method for detecting whether an ESD diode in a chip under test is damaged or not by using the peak detecting unit of any claim 1-3,
the chip to be tested is provided with a VDD pin, a VSS pin and at least one pin to be tested, the pin to be tested is connected with an ESD protection circuit, the ESD protection circuit comprises a diode D1 and a diode D2, the anode of the diode D1 is connected with the VSS pin, the cathode of the diode D2 is connected with the VDD pin, and the cathode of the diode D1 and the anode of the diode D2 are connected with the pin to be tested;
the method comprises the following steps:
selecting a pin to be tested, wherein a peak detection unit VDD port P4 is communicated with a VDD pin of a chip to be tested, a VSS port P5 is communicated with a VSS pin of the chip to be tested, a pin connection port P3 is communicated with the pin to be tested of the chip to be tested, an input port P1 is connected with an external signal generator, a sinusoidal voltage with a peak value larger than the conduction voltage of a diode D1 and a diode D2 is input through the input port P1 by the external signal generator, an output port P2 is connected with a judgment unit, and the judgment unit judges whether an output waveform is normal or not;
judging whether the output voltage of the output port P2 is the peak voltage, if so, further judging whether the output voltage of the output port P2 is the stable peak voltage;
if the output voltage of the output port P2 is not the peak voltage, it indicates that the diode D2 connected to the pin to be tested is damaged;
if the output voltage of the output port P2 is a stable peak voltage, it indicates that the diode D1 and the diode D2 connected to the test pin are normal;
if the output voltage of the output port P2 is not the stable peak voltage, it indicates that the diode D1 connected to the pin to be tested is damaged.
CN201911175147.3A 2019-11-26 2019-11-26 Peak detection unit, detection system and detection method Pending CN110780108A (en)

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CN201911175147.3A CN110780108A (en) 2019-11-26 2019-11-26 Peak detection unit, detection system and detection method

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111721999A (en) * 2020-06-30 2020-09-29 上海创功通讯技术有限公司 Peak voltage detection circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111721999A (en) * 2020-06-30 2020-09-29 上海创功通讯技术有限公司 Peak voltage detection circuit

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