CN110770699A

CN110770699A - Data instruction processing method, storage chip, storage system and movable platform

Info

Publication number: CN110770699A
Application number: CN201880039744.0A
Authority: CN
Inventors: 庹伟; 宋喆喆; 张强
Original assignee: Shenzhen Dajiang Innovations Technology Co Ltd
Current assignee: SZ DJI Technology Co Ltd; Shenzhen Dajiang Innovations Technology Co Ltd
Priority date: 2018-08-22
Filing date: 2018-08-22
Publication date: 2020-02-07
Also published as: WO2020037542A1

Abstract

A data instruction processing method, a storage chip, a storage system and a movable platform are provided, the method comprises the following steps: generating a data instruction; writing a data command into a storage unit in the memory chip, and sending indication information to a first memory outside the memory chip; the indication information comprises a storage address of the data instruction, so that the first memory acquires the data instruction from a storage unit in the storage chip according to the storage address. According to the embodiment, the generated data command is written into the storage unit in the storage chip, the time for writing the data command is shorter, the first memory acquires the data command from the storage unit in the storage chip, and the time for acquiring the data command by the first memory is shorter, so that the execution time of the data command is reduced, and the storage efficiency is improved.

Description

Data instruction processing method, storage chip, storage system and movable platform

Technical Field

The embodiment of the invention relates to the technical field of storage, in particular to a data instruction processing method, a storage chip, a storage system and a movable platform.

Background

With the higher resolution of the image sensor, the deeper and deeper the bit depth of the pixel, the larger and larger the data amount of the image, and the higher and higher the requirement for the storage performance of the digital image acquisition system. The digital image acquisition system is an important part of products such as cameras and video cameras, image Data acquired by a general image sensor can be stored in a Double Data Rate (DDR) Synchronous dynamic random Access Memory (DDR SDRAM) of the products such as cameras and video cameras in real time, the DDR SDRAM is also called a DDR Memory, the DDR Memory can be transferred to a Solid State Drive (SSD), and when the image Data stored in the SSD needs to be displayed, the image Data can be written into the DDR Memory by the SSD.

The existing DDR memory complies with a Non-Volatile memory host controller interface specification (NVME), and the NVME driver operates on the DDR memory, so that image data can be read from or written to the DDR memory by NVME commands. Since a Central Processing Unit (CPU) in a camera, a video camera, or the like generally has limited performance, the CPU generates an NVME command, stores the NVME command in a DDR memory, and notifies the SSD of the NVME command. When the command needs to be executed, the SSD reads the NVME command from the DDR memory and then executes the NVME command. For each NVME command, there are processes of entering into and exiting from the DDR memory, but since the access delay of the DDR memory is large, the execution time of each NVME command becomes long, and the storage efficiency is reduced.

Disclosure of Invention

The embodiment of the invention provides a data instruction processing method, a storage chip, a storage system and a movable platform, which are used for reducing the execution time of a data instruction and improving the storage efficiency.

In a first aspect, an embodiment of the present invention provides a data instruction processing method, applied to a memory chip, including:

generating a data instruction;

writing a data command into a storage unit in the memory chip, and sending indication information to a first memory outside the memory chip;

the indication information comprises a storage address of the data instruction, so that the first memory acquires the data instruction from a storage unit in the storage chip according to the storage address.

In a second aspect, an embodiment of the present invention provides a memory chip, including: a processor and a memory unit;

the processor is used for generating a data instruction, writing the data instruction into a storage unit in the storage chip and sending indication information to a first memory outside the storage chip; the indication information comprises a storage address of the data instruction, so that the first memory acquires the data instruction from a storage unit of the memory chip according to the storage address;

and the storage unit is used for storing the data instruction.

In a third aspect, an embodiment of the present invention provides a storage system, including: a memory chip and a first memory external to the memory chip;

the memory chip is used for generating a data instruction and writing the data instruction into a memory unit in the memory chip; sending indication information to a first memory, wherein the indication information comprises a storage address of a data instruction;

the first memory is used for acquiring data instructions from memory cells in the memory chip according to the memory addresses.

In a fourth aspect, embodiments of the present invention provide a mobile platform, including a body and a storage system according to embodiments of the present invention in the third aspect, where the storage system is disposed on the body.

In a fifth aspect, the present invention provides a computer-readable storage medium, where a computer program is stored, where the computer program includes at least one code segment that is executable by a computer to control the computer to execute the data instruction processing method according to the first aspect.

In a sixth aspect, an embodiment of the present invention provides a computer program, which is used to implement the data instruction processing method according to the first aspect when the computer program is executed by a computer.

According to the data instruction processing method, the storage chip, the storage system and the movable platform provided by the embodiment of the invention, the data instruction is generated; writing a data command into a storage unit in the memory chip, and sending indication information to a first memory outside the memory chip; wherein the indication information comprises a memory address of the data instruction, and then the first memory fetches the data instruction from a memory location within the memory chip according to the memory address. In the embodiment of the invention, because the access delay of the storage unit in the storage chip is relatively small and the performance is not influenced by address switching, the time for writing the data command can be shortened by writing the generated data command into the storage unit in the storage chip, and the first memory directly acquires the data command from the storage unit in the storage chip.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

FIG. 1 is a schematic architectural diagram of an unmanned flight system according to an embodiment of the invention;

FIG. 2 is a flowchart of a data instruction processing method according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a memory chip according to an embodiment of the invention;

FIG. 4 is a schematic structural diagram of a memory system according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a movable platform according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

The embodiment of the invention provides a data instruction processing method, a storage chip, a storage system and a movable platform. The movable platform may be, for example, a drone automobile, a robot, a handheld electronic device, or the like. Where the drone may be, for example, a rotorcraft (rotorcraft), such as a multi-rotor aircraft propelled through air by a plurality of propulsion devices, embodiments of the invention are not limited in this regard.

FIG. 1 is a schematic architectural diagram of an unmanned flight system according to an embodiment of the invention. The present embodiment is described by taking a rotor unmanned aerial vehicle as an example.

The unmanned flight system 100 can include a drone 110, a display device 130, and a control terminal 140. The drone 110 may include, among other things, a power system 150, a flight control system 160, a frame, and a pan-tilt 120 carried on the frame. The drone 110 may be in wireless communication with the control terminal 140 and the display device 130.

The airframe may include a fuselage and a foot rest (also referred to as a landing gear). The fuselage may include a central frame and one or more arms connected to the central frame, the one or more arms extending radially from the central frame. The foot rest is connected with the fuselage for play the supporting role when unmanned aerial vehicle 110 lands.

The power system 150 may include one or more electronic governors (abbreviated as electric governors) 151, one or more propellers 153, and one or more motors 152 corresponding to the one or more propellers 153, wherein the motors 152 are connected between the electronic governors 151 and the propellers 153, the motors 152 and the propellers 153 are disposed on the horn of the drone 110; the electronic governor 151 is configured to receive a drive signal generated by the flight control system 160 and provide a drive current to the motor 152 based on the drive signal to control the rotational speed of the motor 152. The motor 152 is used to drive the propeller in rotation, thereby providing power for the flight of the drone 110, which power enables the drone 110 to achieve one or more degrees of freedom of motion. In certain embodiments, the drone 110 may rotate about one or more axes of rotation. For example, the above-mentioned rotation axes may include a Roll axis (Roll), a Yaw axis (Yaw) and a pitch axis (pitch). It should be understood that the motor 152 may be a dc motor or an ac motor. The motor 152 may be a brushless motor or a brush motor.

Flight control system 160 may include a flight controller 161 and a sensing system 162. The sensing system 162 is used to measure attitude information of the drone, i.e., position information and status information of the drone 110 in space, such as three-dimensional position, three-dimensional angle, three-dimensional velocity, three-dimensional acceleration, three-dimensional angular velocity, and the like. The sensing system 162 may include, for example, at least one of a gyroscope, an ultrasonic sensor, an electronic compass, an Inertial Measurement Unit (IMU), a vision sensor, a global navigation satellite system, and a barometer. For example, the Global navigation satellite System may be a Global Positioning System (GPS). The flight controller 161 is used to control the flight of the drone 110, for example, the flight of the drone 110 may be controlled according to attitude information measured by the sensing system 162. It should be understood that the flight controller 161 may control the drone 110 according to preprogrammed instructions, or may control the drone 110 in response to one or more control instructions from the control terminal 140.

The pan/tilt head 120 may include a motor 122. The pan/tilt head is used to carry the photographing device 123. Flight controller 161 may control the movement of pan/tilt head 120 via motor 122. Optionally, as another embodiment, the pan/tilt head 120 may further include a controller for controlling the movement of the pan/tilt head 120 by controlling the motor 122. It should be understood that the pan/tilt head 120 may be separate from the drone 110, or may be part of the drone 110. It should be understood that the motor 122 may be a dc motor or an ac motor. The motor 122 may be a brushless motor or a brush motor. It should also be understood that the pan/tilt head may be located at the top of the drone, as well as at the bottom of the drone.

The photographing device 123 may be, for example, a device for capturing an image such as a camera or a video camera, and the photographing device 123 may communicate with the flight controller and perform photographing under the control of the flight controller. The image capturing Device 123 of this embodiment at least includes a photosensitive element, such as a Complementary Metal Oxide Semiconductor (CMOS) sensor or a Charge-coupled Device (CCD) sensor. It can be understood that the camera 123 may also be directly fixed to the drone 110, such that the pan/tilt head 120 may be omitted.

The display device 130 is located at the ground end of the unmanned aerial vehicle system 100, can communicate with the unmanned aerial vehicle 110 in a wireless manner, and can be used for displaying attitude information of the unmanned aerial vehicle 110. In addition, an image taken by the imaging device may also be displayed on the display apparatus 130. It should be understood that the display device 130 may be a stand-alone device or may be integrated into the control terminal 140.

The control terminal 140 is located at the ground end of the unmanned aerial vehicle system 100, and can communicate with the unmanned aerial vehicle 110 in a wireless manner, so as to remotely control the unmanned aerial vehicle 110.

In addition, the unmanned aerial vehicle 110 may also have a speaker (not shown in the figure) mounted thereon, and the speaker is used for playing audio files, and the speaker may be directly fixed on the unmanned aerial vehicle 110, or may be mounted on the cradle head 120.

It should be understood that the above-mentioned nomenclature for the components of the unmanned flight system is for identification purposes only, and should not be construed as limiting embodiments of the present invention. The memory chip described in the following embodiments may be disposed in the above-described photographing device 123, for example.

Fig. 2 is a flowchart of a data instruction processing method according to an embodiment of the present invention, and as shown in fig. 2, the method according to the embodiment may include:

s201, generating a data instruction by the storage chip.

The memory chip of the present embodiment may generate data instructions. For example: which may be a processor in a memory chip, such as a Central Processing Unit (CPU), generates data instructions. The data instruction may be, for example, an instruction to process data, which may include reading data or writing data, and so on. The data instruction may also be, for example, an Identify (Identify) instruction.

Alternatively, the generated data instruction may be an instruction based on image data, for example, the processing of data includes processing image data.

Optionally, the data command may be a data command based on a Non-volatile memory host controller interface specification (NVME) protocol. Data instructions based on the NVME protocol may include, for example, Input/Output (I/O) instructions and admin (admin) instructions. The I/O instructions may include, for example, data read instructions and data write instructions. Of course, the data command may also be a data command based on Serial ATA Advanced Host Controller Interface (Serial ATA Advanced Host Controller Interface) protocol.

S202, the memory chip writes the data command into a memory unit in the memory chip.

The memory chip in this embodiment may write the generated data command into a memory cell of the memory chip.

Optionally, the memory chip may be a Field-Programmable Gate Array (FPGA) chip. The FPGA Chip may be, for example, an FPGA Chip with a System on a Chip (SOC).

S203, the memory chip sends indication information to a first memory outside the memory chip, wherein the indication information comprises a memory address of the data instruction.

The memory chip in this embodiment transmits the instruction information to the first memory outside the memory chip after writing the data instruction to the memory cell inside the memory chip.

Optionally, the memory chip in this embodiment may also send the indication information to the first memory outside the memory chip after determining the memory address of the data instruction, where the indication information includes the memory address of the data instruction. The indication information may include, for example, a starting address of the data instruction in a memory location inside the memory chip and a size of the data instruction.

In this embodiment, the execution sequence of S202 and S203 may be adjusted as needed in addition to the above description, and the execution sequence of S202 and S203 is not limited herein.

Optionally, the first memory may be a non-volatile memory, for example, a Solid State Drive (SSD). If the storage chip is an FPGA chip, the FPGA chip and the SSD may communicate via a Peripheral Component Interconnect Express (PCIE) standard.

S204, the first memory acquires the data instruction from the memory unit in the memory chip according to the memory address of the data instruction.

In this embodiment, the first memory receives indication information sent by the memory chip, where the indication information includes a memory address of the data instruction. When the first memory needs to acquire the data instruction, the data instruction is acquired from a storage unit in the memory chip according to the storage address of the data instruction.

In the data instruction processing method provided by this embodiment, a data instruction is generated, the data instruction is written into a storage unit in a memory chip, and indication information is sent to a first memory outside the memory chip, where the indication information includes a storage address of the data instruction, and then the first memory acquires the data instruction from the storage unit in the memory chip according to the storage address. In this embodiment, since access latency of the memory cell in the memory chip is relatively small and performance is not affected by address switching, by writing the generated data command into the memory cell in the memory chip, the time for writing the data command can be shortened, and the first memory directly obtains the data command from the memory cell in the memory chip.

In some embodiments, since the memory resources inside the memory chip are at a premium, the memory chip of the present embodiment can selectively write the generated data commands to the memory cells inside the memory chip.

Optionally, the memory chip further determines an instruction type of the data instruction before writing the data instruction into a memory location within the memory chip. Accordingly, one implementation manner of the memory chip writing the data instruction into the memory cell in the memory chip may be: and if the instruction type of the data instruction belongs to the first instruction type, the memory chip writes the data instruction into a memory unit in the memory chip.

Optionally, if the instruction type of the data instruction belongs to the second instruction type, the memory chip writes the data instruction into a second memory outside the memory chip. Optionally, the first memory is a nonvolatile memory, and the second memory is a volatile memory. For example: the first memory is an SSD, and the second memory is a DDR memory.

Therefore, the present embodiment ensures that the data command belonging to the first command type is written into the memory cell of the memory chip as much as possible.

In some embodiments, the memory chip may divide the generated data instruction into a first instruction type and a second instruction type according to a preset rule. The preset rules can be flexibly set by a user according to actual needs, and data instructions can be conveniently written into the storage units in the storage chip in a targeted manner. The preset rule may include, for example, a mapping relationship between the data instruction and the type of the instruction. The preset rule can provide that the A instruction, the B instruction and the C instruction belong to a first instruction type, and the D instruction and the E instruction belong to a second instruction type, wherein the A instruction, the B instruction, the C instruction, the D instruction and the E instruction represent different data instructions.

In some embodiments, the memory chip may divide the generated data instructions into two classes (a first instruction type and a second instruction type) according to the fetched frequency of the data instructions. The first instruction type is an instruction with the acquired frequency being greater than the preset frequency, and the second instruction type is an instruction with the acquired frequency being less than or equal to the preset frequency. Optionally, the acquired frequency of the data command may be preset, or may be obtained statistically and updated at a preset period.

In some embodiments, the memory chip may write the data command with the acquired frequency greater than the preset frequency into a memory unit in the memory chip, and the memory chip may write the data command with the acquired frequency less than or equal to the preset frequency into a second memory outside the memory chip.

Therefore, by writing the data command with high acquisition frequency into the storage unit in the storage chip, the data command with low acquisition frequency can be prevented from occupying the storage resource in the storage chip, the storage unit in the storage chip can be ensured to have enough storage resource for storing the data command with higher acquisition frequency as far as possible, the utilization efficiency of the storage unit in the storage chip is also improved, and the overall storage efficiency is further improved. Meanwhile, the data instruction with high acquisition frequency is written into the storage unit in the storage chip, so that the time for acquiring the data instruction of the type can be reduced, the execution efficiency of the data instruction is improved, and particularly when the data instruction is frequently acquired, the execution efficiency of the data instruction can be obviously improved.

In some embodiments, according to the acquired frequency of the data instructions or the preset rule, the memory chip may divide the data read instruction and the data write instruction in the generated data instructions into a first instruction type, and divide some instructions (e.g., admin command) except the data read instruction and the data write instruction in the data instructions into a second instruction type. It should be noted that the data instruction of the first instruction type is not limited to only include a data read instruction and a data write instruction.

In some embodiments, the data instruction generated by the memory chip may be a data read instruction for controlling writing of data in the first memory to a second memory external to the memory chip. After the memory chip generates the data read instruction, the memory chip may write the data read instruction into a memory cell inside the memory chip, and send the indication information to a first memory outside the memory chip, where the indication information includes a memory address of the data read instruction. After the first memory receives the indication information, the data reading instruction can be read from the storage unit in the memory chip as required, and then the data stored in the first memory is written into a second memory outside the memory chip according to the data reading instruction.

In some embodiments, the data instruction generated by the memory chip is a data write instruction for controlling writing of data in a second memory external to the memory chip to a third memory external to the memory chip. After the memory chip generates the data write command, the memory chip may write the data write command into a memory cell inside the memory chip, and send indication information to a first memory outside the memory chip, where the indication information includes a memory address of the data write command. And after receiving the indication information, the first memory reads the data writing instruction from the storage unit in the storage chip, then reads the data stored in the second memory outside the storage chip according to the data writing instruction, and writes the data into the third memory outside the storage chip. Optionally, the third memory may include the first memory, that is, the first memory may read data stored in the second memory outside the memory chip according to the data writing instruction and write the data into the first memory.

Alternatively, the data stored in the second memory may include image data acquired by the image sensor, i.e., the image sensor stores the acquired image data in the second memory in real time. Therefore, the data writing instruction is stored in the storage unit in the storage chip, the first storage can quickly acquire the data writing instruction, the execution efficiency of the data writing instruction is improved, the image data stored in the second storage can be written into the first storage in time, the phenomenon of image data loss is avoided, and especially when the image sensor collects video image data, the risk of video frame loss can be effectively avoided.

Optionally, the first memory is a nonvolatile memory, the second memory is a volatile memory, and the third memory is a nonvolatile memory. For example: the first memory is an SSD, and the second memory is a DDR memory.

In some embodiments, the Memory unit in the Memory Chip (i.e., the FPGA Chip) may include an On Chip Memory (OCM) and/or a CACHE Memory (CACHE). That is, the memory chip writes the generated data instruction to the OCM. Or the memory chip writes the generated data instruction into CACHE. Alternatively, the memory chips may write some data instructions to the OCM and some other data instructions to the CACHE.

Optionally, the OCM may be generated by a Memory Block (Block Memory) on the FPGA chip, and the OCM may be packaged as an Advanced eXtensible Interface (AXI) peripheral, and may communicate with the processor of the Memory chip through an AXI bus.

The FPGA chip may be used to perform image signal processing ISP on image data, and the OCM and CACHE in the FPGA chip may be used for line caching of video, for example. Compared with DDR, OCM and CACHE have small read-write delay, and random access does not have the problem of address activation. Therefore, the time required for writing the data instruction into the OCM or CACHE is short, and the time required for reading the data instruction from the OCM or CACHE is short, thereby reducing the execution time of the data instruction.

Taking the first memory as the SSD, the memory chip as the FPGA chip, the generated data instruction as the data instruction based on the NVME protocol, and writing the generated data instruction into the OCM, as an example. In the prior art, a data instruction based on the NVME protocol is written into a DDR memory outside the FPGA chip by the FPGA chip, the SSD outside the FPGA chip acquires the data instruction from the DDR memory through the FPGA chip, each data instruction based on the NVME protocol has a process of entering and exiting the DDR memory, because the access delay of the DDR memory is large, the read-write delay of the data instruction is increased, and if the data instruction based on the NVME protocol is frequently taken from the DDR, the address switching frequency of the DDR is increased, the bandwidth of the DDR is reduced, and the performance of the entire storage system is affected. In the embodiment of the invention, the FPGA chip writes the generated data instruction based on the NVME protocol into the OCM inside the FPGA chip and sends the indication information to the SSD outside the FPGA chip, the indication information comprises the storage address of the data instruction, and the SSD acquires the data instruction from the OCM according to the storage address. Therefore, the read-write delay of the data instruction is small, the problem of address switching does not exist, the storage efficiency is improved, and the performance of the whole storage system can be improved. Particularly, the write bandwidth fluctuation of the SSD can be smaller, the SSD writing speed is favorably improved, and compared with the access delay of a DDR memory, the risk of video frame loss can be effectively reduced by storing a data instruction in the OCM.

In some embodiments, the number of OCMs inside the memory chip may be multiple.

For a plurality of OCMs, the memory chip in this embodiment writes the data instruction into one of the plurality of OCMs according to a preset storage rule.

In a possible implementation manner, the preset storage rule indicates to write a data instruction into the OCM with the largest free capacity, and accordingly, after the memory chip generates the data instruction, the memory chip determines the OCM with the largest free capacity from the plurality of OCMs, and writes the generated data instruction into the OCM with the largest free capacity. The spare capacity indicates the remaining available storage resources in the OCM, and the OCM with the larger spare capacity responds to the writing and reading of the data instruction faster, so that the storage efficiency is further improved.

In a possible implementation manner, the preset storage rule indicates that the data instruction is written into the OCM with the smallest number of accesses, accordingly, after the memory chip generates the data instruction, the OCM with the smallest number of accesses is determined from the plurality of OCMs, and the generated data instruction is written into the OCM with the smallest number of accesses. For example, the number of times each OCM is accessed may be counted periodically. The number of accesses reflects to some extent the condition that resources in the OCM are seized by other instructions. Therefore, in the present embodiment, the data instruction is written into the OCM with the minimum number of accesses, and the influence on the writing process of other instructions into the OCM can be avoided as much as possible.

In a possible implementation manner, the preset storage rule indicates that the data instruction is written into the OCM with the smallest number of accessed times and the largest free capacity, accordingly, after the memory chip generates the data instruction, according to the sequence of the number of accessed times from high to low, M OCMs with the later number of accessed times are determined from the plurality of OCMs, where M is a positive integer not less than 1, and then the data instruction is written into the OCM with the largest free capacity among the M OCMs. Therefore, the process of writing other instructions into the OCM is prevented from being influenced as much as possible, and the faster the writing and reading response of the data instruction is, the storage efficiency is further improved.

Fig. 3 is a schematic structural diagram of a memory chip according to an embodiment of the present invention, and as shown in fig. 3, the memory chip 300 according to the embodiment may include: a processor 301 and a memory unit 302. The processor 301 and the memory unit 302 are communicatively connected by a bus, for example, may be connected by an AXI bus. The processor 301 may be a Central Processing Unit (CPU), and the processor 301 may also be other general-purpose processors. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

A processor 301, configured to generate a data instruction, write the data instruction into a storage unit 302 in the memory chip 300, and send instruction information to a first memory outside the memory chip 300; the indication information includes a memory address of the data instruction, so that the first memory fetches the data instruction from the memory unit 302 of the memory chip 300 according to the memory address.

A storage unit 302 for storing data instructions.

Optionally, the data instruction is a data instruction based on NVME protocol.

Optionally, the memory chip 300 is an FPGA chip.

Optionally, memory unit 302 may include an OCM and/or CACHE.

Optionally, the number of OCMs is plural. The processor 301 is specifically configured to: and writing the data instruction into one OCM of the plurality of OCMs according to a preset storage rule.

Optionally, the processor 301 is specifically configured to: and writing the data instruction into the OCM with the largest idle capacity in the plurality of OCMs. Or, the data instruction is written into the OCM with the minimum access time in the plurality of OCMs. Or according to the sequence of the accessed times from high to low, determining M OCMs with the later accessed times from the plurality of OCMs, wherein M is a positive integer not less than 1, and writing the data instruction into the OCM with the largest idle capacity in the M OCMs.

Optionally, the data instruction includes a data read instruction or a data write instruction.

Optionally, when the data instruction is a data read instruction, the data read instruction is used to control writing of data in the first memory into a second memory outside the memory chip 300. Or, when the data command is a data write command, the data write command is used to control writing of data in a second memory outside the memory chip 300 into a third memory outside the memory chip 300.

Optionally, the third memory comprises the first memory.

Optionally, the processor 301 is further configured to determine an instruction type of the data instruction before writing the data instruction into the memory unit 302 in the memory chip 300.

When writing the data instruction into the memory unit 302 in the memory chip 300, the processor 301 is specifically configured to: if the instruction type of the data instruction is of the first instruction type, the data instruction is written into the memory unit 302 in the memory chip 300.

Optionally, the processor 301 is further configured to: if the instruction type of the data instruction belongs to the second instruction type, the data instruction is written into a second memory outside the memory chip 300.

Optionally, the first instruction type is an instruction whose acquired frequency is greater than a preset frequency, and the second instruction type is an instruction whose acquired frequency is less than or equal to the preset frequency.

Optionally, the first memory is a nonvolatile memory, and the second memory is a volatile memory.

Optionally, the second memory is a DDR memory.

Optionally, the first memory is an SSD.

Optionally, the data instruction is an instruction based on image data.

The memory chip provided in this embodiment may be used to implement the technical solutions of the memory chip in the above method embodiments of the present invention, and the implementation principles and technical effects are similar, and are not described herein again.

Fig. 4 is a schematic structural diagram of a memory system according to an embodiment of the present invention, and as shown in fig. 4, a memory system 400 according to this embodiment may include a memory chip 401 and a first memory 402 outside the memory chip. The memory chip 401 and the first memory 402 outside the memory chip are communicatively connected by a bus. Optionally, the memory system 400 provided in this embodiment may further include a second memory 403 outside the memory chip, and the second memory 403 may be communicatively connected to the above devices through a bus. Optionally, the storage system 400 provided in this embodiment may further include an image sensor 404, and the image sensor 404 may be communicatively connected to the above devices through a bus.

The memory chip 401 is configured to generate a data command and write the data command into a memory location in the memory chip, and send indication information to the first memory 402, where the indication information includes a memory address of the data command.

A first memory 402 for fetching data instructions from memory locations within the memory chip according to the memory address.

Optionally, the data instruction is a data instruction based on NVME protocol.

Optionally, the memory chip is an FPGA chip.

Optionally, the memory unit may include an OCM and/or a CACHE.

Optionally, the number of OCMs is plural. The memory chip 401 is specifically configured to: and writing the data instruction into one OCM of the plurality of OCMs according to a preset storage rule.

Optionally, the memory chip 401 is specifically configured to: and writing the data instruction into the OCM with the largest idle capacity in the plurality of OCMs. Or, the data instruction is written into the OCM with the minimum access time in the plurality of OCMs. Or according to the sequence of the accessed times from high to low, determining M OCMs with the later accessed times from the plurality of OCMs, wherein M is a positive integer not less than 1, and writing the data instruction into the OCM with the largest idle capacity in the M OCMs.

Optionally, when the data instruction is a data read instruction, the data read instruction is used to control writing of data in the first memory 402 into the second memory 403 outside the memory chip. Or, optionally, the memory system 400 may further include a third memory (not shown in the figure) outside the memory chip, where the data instruction is a data write instruction, and the data write instruction is used to control writing of data in the second memory 403 outside the memory chip into the third memory outside the memory chip.

Optionally, the third memory may include the first memory 402.

Optionally, the memory chip 401 is further configured to determine an instruction type of the data instruction before writing the data instruction into a memory location in the memory chip.

When the memory chip 401 writes a data command into a memory cell in the memory chip, it is specifically configured to: and if the instruction type of the data instruction belongs to the first instruction type, writing the data instruction into a storage unit in the storage chip.

Optionally, the memory chip 401 is further configured to: if the instruction type of the data instruction belongs to the second instruction type, the data instruction is written into the second memory 403.

Optionally, the first memory 402 is a non-volatile memory, and the second memory 403 is a volatile memory.

Optionally, the second memory 403 is a DDR memory.

Optionally, the first memory 402 is an SSD.

Alternatively, the storage system 400 may be an imaging system.

Optionally, the image sensor 404 is configured to acquire image data, and the second memory 403 is configured to store the image data acquired by the image sensor.

Alternatively, the data instructions may be instructions based on image data.

The memory chip 401 may adopt the structure of the embodiment shown in fig. 3, and accordingly, the technical solutions of the memory chip in the above method embodiments may be implemented, which have similar implementation principles and technical effects, and are not described herein again.

When the storage system 400 provided in the present embodiment is an imaging system, the data stored in the second memory may include image data acquired by the image sensor, that is, the image sensor stores the acquired image data in the second memory in real time. The data writing instruction is stored in the storage unit in the storage chip, and the first storage can quickly acquire the data writing instruction, so that the execution efficiency of the data writing instruction is improved, the image data stored in the second storage can be written into the first storage in time, the phenomenon of image data loss is avoided, and particularly, when the image sensor collects video image data, the risk of video frame loss can be effectively reduced.

Fig. 5 is a schematic structural diagram of a movable platform according to an embodiment of the present invention, and as shown in fig. 5, the movable platform 500 according to the embodiment may include: the device comprises a body 501 and a storage system 502, wherein the storage system 502 is arranged on the body 501. The storage system 502 may adopt the structure of the embodiment shown in fig. 4, and accordingly, the technical solutions in the above method embodiments may be executed, which have similar implementation principles and technical effects, and are not described herein again.

Alternatively, the movable platform 500 may be an aircraft.

Specifically, when the aircraft is used for taking photo by plane or utilizes the aircraft to shoot the image data that acquires and carry out the place environment to the aircraft and judge, need to shoot the image data that acquires to the aircraft and carry out corresponding processing, then the control end on ground is given in image data transmission after will handling, so that the control end shows the picture that the aircraft was shot, thereby show in real time through image data, can satisfy user's the demand of taking photo by plane, and simultaneously, the aircraft is as remote control thing, through image data's real-time display, can judge in real time whether the place environment of aircraft does benefit to unmanned aerial vehicle's flight, and can control the aircraft through the judged result better. In practical application, if there is a delay or frame loss in the transmission of image data from the aircraft to the control end, it is not favorable for controlling the aircraft and for improving the aerial photography experience.

According to the scheme, the image data acquired by shooting of the aircraft can be transmitted to the control end in time by improving the execution efficiency of the data instruction, so that the phenomenon that the control end loses the shooting picture of the unmanned aerial vehicle is avoided, the flight of the unmanned aerial vehicle is controlled more favorably, the flight safety is ensured, and the real-time performance of the shooting picture display is improved favorably.

Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: various media capable of storing program codes, such as a Read-only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, and an optical disk.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data instruction processing method is applied to a memory chip and comprises the following steps:

generating a data instruction;

writing the data command into a storage unit in a storage chip, and sending indication information to a first memory outside the storage chip;

wherein the indication information includes a memory address of the data instruction, so that the first memory fetches the data instruction from a memory location within the memory chip according to the memory address.

2. The method of claim 1, wherein the data command is a data command based on the NVME protocol.

3. The method of claim 1 or 2, wherein the memory chip is a Field Programmable Gate Array (FPGA) chip.

4. The method according to claim 3, wherein the memory unit comprises an on-chip memory OCM and/or a CACHE memory CACHE.

5. The method of claim 4, wherein the number of OCMs is plural;

the writing the data command into a memory cell in a memory chip includes:

and writing the data instruction into one of the OCMs according to a preset storage rule.

6. The method of claim 5, wherein writing the data instruction to one of the OCMs according to a preset storage rule comprises:

writing the data instruction into an OCM with the largest idle capacity in a plurality of OCMs; or the like, or, alternatively,

writing the data instruction into the OCM with the minimum access time in the plurality of OCMs; or the like, or, alternatively,

determining M OCMs with later accessed times from a plurality of OCMs according to the sequence of the accessed times from high to low, wherein M is a positive integer not less than 1;

and writing the data instruction into the OCM with the maximum idle capacity in M OCMs.

7. The method of claim 3, wherein the data instruction comprises a data read instruction or a data write instruction.

8. The method according to claim 7, wherein when the data instruction is a data read instruction, the data read instruction is used to control writing of data in the first memory into a second memory external to the memory chip; alternatively, the first and second electrodes may be,

and when the data instruction is a data writing instruction, the data writing instruction is used for controlling the data in the second memory outside the memory chip to be written into the third memory outside the memory chip.

9. The method of claim 8, wherein the third memory comprises the first memory.

10. The method of claim 3, wherein prior to writing the data command to the memory location within the memory chip, further comprising:

determining an instruction type of the data instruction;

the writing the data command into a memory cell in a memory chip includes:

and if the instruction type of the data instruction belongs to the first instruction type, writing the data instruction into a storage unit in the storage chip.

11. The method of claim 10, further comprising:

and if the instruction type of the data instruction belongs to a second instruction type, writing the data instruction into a second memory outside the memory chip.

12. The method of claim 11, wherein the first instruction type is an instruction with a captured frequency greater than a preset frequency, and the second instruction type is an instruction with a captured frequency less than or equal to the preset frequency.

13. The method of claim 8, 9, 11 or 12, wherein the first memory is a non-volatile memory and the second memory is a volatile memory.

14. The method of claim 13, wherein the second memory is a Double Data Rate (DDR) memory.

15. The method of claim 13, wherein the first memory is a Solid State Disk (SSD).

16. A method according to claim 1 or 2, wherein the data instructions are instructions based on image data.

17. A memory chip, comprising: a processor and a memory unit;

the processor is used for generating a data instruction, writing the data instruction into the storage unit in the storage chip and sending indication information to a first memory outside the storage chip; the indication information comprises a storage address of the data instruction, so that the first memory acquires the data instruction from a storage unit of the memory chip according to the storage address;

the storage unit is used for storing the data instruction.

18. The memory chip of claim 17, wherein the data command is a data command based on the NVME protocol.

19. The memory chip of claim 17 or 18, wherein the memory chip is a Field Programmable Gate Array (FPGA) chip.

20. The memory chip of claim 19, wherein the memory unit comprises an on-chip memory (OCM) and/or a CACHE memory (CACHE).

21. The memory chip of claim 20, wherein the number of OCMs is plural;

the processor is specifically configured to: and writing the data instruction into one of the OCMs according to a preset storage rule.

22. The memory chip of claim 21, wherein the processor is specifically configured to:

23. The memory chip of any one of claims 17-22, wherein the data instruction comprises a data read instruction or a data write instruction.

24. The memory chip of claim 23, wherein when the data command is a data read command, the data read command is used to control writing of data in the first memory into a second memory external to the memory chip; alternatively, the first and second electrodes may be,

25. The memory chip of claim 24, in which the third memory comprises the first memory.

26. The memory chip of any one of claims 17-19, wherein the processor, prior to writing the data instruction to the memory location within the memory chip, is further configured to determine an instruction type of the data instruction;

when the processor writes the data instruction into the memory cell in the memory chip, the processor is specifically configured to: and if the instruction type of the data instruction belongs to a first instruction type, writing the data instruction into a storage unit in the storage chip.

27. The memory chip of claim 26, wherein the processor is further configured to: and if the instruction type of the data instruction belongs to a second instruction type, writing the data instruction into a second memory outside the memory chip.

28. The memory chip of claim 27, wherein the first instruction type is an instruction with a captured frequency greater than a preset frequency, and the second instruction type is an instruction with a captured frequency less than or equal to the preset frequency.

29. The memory chip of claim 24 or 25 or 27 or 28, wherein the first memory is a non-volatile memory and the second memory is a volatile memory.

30. The memory chip of claim 29, wherein the second memory is a Double Data Rate (DDR) memory.

31. The memory chip of claim 29, wherein the first memory is a Solid State Disk (SSD).

32. The memory chip of claim 17 or 18, wherein the data instructions are instructions based on image data.

33. A storage system, comprising: a memory chip and a first memory external to the memory chip;

the memory chip is used for generating a data instruction and writing the data instruction into a memory unit in the memory chip; sending indication information to the first memory, wherein the indication information comprises a storage address of the data instruction;

the first memory is used for acquiring the data instruction from a storage unit in the storage chip according to the storage address.

34. The system of claim 33, wherein the data command is a data command based on the NVME protocol.

35. The system of claim 33 or 34, wherein the memory chip is a Field Programmable Gate Array (FPGA) chip.

36. The system according to any of claims 33-35, wherein said memory unit comprises an on-chip memory OCM and/or a CACHE memory CACHE.

37. The system of claim 36, wherein the number of OCMs is plural;

the memory chip is specifically configured to: and writing the data instruction into one of the OCMs according to a preset storage rule.

38. The system of claim 37, wherein the memory chip is specifically configured to:

39. The system of any of claims 33-38, wherein the data instruction comprises a data read instruction or a data write instruction.

40. The system of claim 39, further comprising a second memory external to the memory chip, wherein when the data command is a data read command, the data read command is used to control writing of data in the first memory into the second memory external to the memory chip; alternatively, the first and second electrodes may be,

the system further comprises a second memory and a third memory which are outside the memory chip, and when the data instruction is a data writing instruction, the data writing instruction is used for controlling the data in the second memory which is outside the memory chip to be written into the third memory which is outside the memory chip.

41. The system of claim 40, wherein the third memory comprises the first memory.

42. The system according to any of claims 33-35, wherein said memory chip is further configured to determine an instruction type of said data instruction prior to writing said data instruction to a memory location within said memory chip;

when the memory chip writes the data command into a memory cell in the memory chip, the memory chip is specifically configured to: and if the instruction type of the data instruction belongs to the first instruction type, writing the data instruction into a storage unit in the storage chip.

43. The system of claim 42, further comprising a second memory external to the memory chip;

the memory chip is further configured to: and if the instruction type of the data instruction belongs to a second instruction type, writing the data instruction into the second memory.

44. The system according to claim 43, wherein the first instruction type is an instruction with a captured frequency greater than a preset frequency, and the second instruction type is an instruction with a captured frequency less than or equal to a preset frequency.

45. The system of claim 40 or 41 or 43 or 44, wherein the first memory is a non-volatile memory and the second memory is a volatile memory.

46. The system of claim 45, wherein the second memory is a Double Data Rate (DDR) memory.

47. The system of claim 45, wherein the first memory is a Solid State Disk (SSD).

48. The system of claim 40 or 41 or 43 or 44, wherein the storage system is an imaging system.

49. The system of claim 48, further comprising: an image sensor;

the image sensor is used for acquiring image data;

the second memory is used for storing the image data collected by the image sensor.

50. The system of claim 33 or 34, wherein the data instructions are image data based instructions.

51. A movable platform comprising a fuselage and a storage system as claimed in any one of claims 33 to 50 provided on the fuselage.

52. The movable platform of claim 51, wherein the movable platform is an aircraft.