CN110767664A - Display substrate, manufacturing method thereof and display device - Google Patents
Display substrate, manufacturing method thereof and display device Download PDFInfo
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- CN110767664A CN110767664A CN201911053837.1A CN201911053837A CN110767664A CN 110767664 A CN110767664 A CN 110767664A CN 201911053837 A CN201911053837 A CN 201911053837A CN 110767664 A CN110767664 A CN 110767664A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides a display substrate, a manufacturing method thereof and a display device, relates to the technical field of display, and aims to solve the problem that a crack generated at the edge of the display substrate is easy to expand towards the interior of the display substrate, so that the packaging of the display substrate is invalid. The display substrate includes: the display area is in with the setting peripheral barricade structure of display area, barricade structure is in orthographic projection on the basement of display substrates is latticed. The display substrate provided by the invention is used for displaying pictures.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display substrate, a manufacturing method of the display substrate and a display device.
Background
At present, in order to improve the production efficiency and reduce the production cost of the Display device, such as a Thin Film Transistor Liquid Crystal Display (TFT-LCD) device or an Organic Light Emitting Diode Display (OLED) device, is manufactured by an integral process on a motherboard and then cut and separated, thereby further completing the rear module process.
Taking manufacturing of a flexible display substrate comprising a flexible substrate as an example, firstly forming the flexible substrate on a carrier plate, then simultaneously manufacturing a plurality of display devices on the flexible substrate in a high-utilization-rate arrangement mode to form a flexible display substrate mother plate, then separating the flexible substrate from the carrier plate by adopting a laser stripping technology, attaching a bottom film on the surface of the flexible substrate, which is back to the display devices, and finally cutting and separating in a cutting area between two adjacent display devices in the flexible display substrate mother plate by adopting a laser cutting technology to form a plurality of independent flexible display substrates. However, since the inorganic layer at the edge of the flexible display substrate is brittle, cracks are easily generated in the inorganic layer at the edge during a cutting operation, and the cracks are easily propagated into the flexible display substrate during transportation and subsequent process operations of the cut flexible display substrate, thereby causing a package failure.
Disclosure of Invention
The invention aims to provide a display substrate, a manufacturing method thereof and a display device, which are used for solving the problem that a crack generated at the edge of the display substrate is easy to expand towards the interior of the display substrate, so that the packaging of the display substrate is invalid.
In order to achieve the above purpose, the invention provides the following technical scheme:
a first aspect of the present invention provides a display substrate comprising: the display area is in with the setting peripheral barricade structure of display area, barricade structure is in orthographic projection on the basement of display substrates is latticed.
Optionally, the retaining wall structure includes a retaining wall body, and the retaining wall body can limit a plurality of latticed spaces, the retaining wall body includes first retaining wall strip at least, the extending direction of first retaining wall strip, with the extending direction on the border that is closest to this first retaining wall strip in the display area has first contained angle between them, first contained angle is less than 90 degrees.
Optionally, the retaining wall body further includes:
a second included angle is formed between the extending direction of the second wall blocking strip and the extending direction of the boundary, closest to the second wall blocking strip, in the display area, and the second included angle is equal to 90 degrees;
the outer frame body surrounds the first retaining wall strips and the second retaining wall strips, and the first retaining wall strips, the second retaining wall strips and the outer frame body define a plurality of grid-shaped spaces in an area surrounded by the outer frame body;
at most only one of both ends of the second barrier rib in its own extending direction can be directly coupled to the outer frame.
Optionally, a thin film transistor array layer is disposed in a display area of the display substrate, the thin film transistor array layer includes a plurality of sub-pixel driving circuits distributed in an array, and each sub-pixel driving circuit includes a plurality of thin film transistors and at least one capacitor unit; the thin film transistor comprises an active layer, a grid electrode and a source drain electrode layer which are arranged in a stacked mode; the capacitor unit comprises a first polar plate and a second polar plate which are oppositely arranged, and the first polar plate and the grid are arranged on the same layer and made of the same material;
the retaining wall structure comprises a plurality of retaining wall graphs which are stacked, the retaining wall graphs at least comprise a first retaining wall graph, a second retaining wall graph and a third retaining wall graph, the first retaining wall graph and the grid are arranged with the same layer and the same material, the second retaining wall graph and the second grid are arranged with the same layer and the same material, and the third retaining wall graph and the source drain electrode layer are arranged with the same layer and the same material.
Optionally, the display area further includes:
a blocking layer disposed between the substrate and the active layer, the blocking layer extending between the first dam pattern and the substrate;
a first insulating layer disposed between the active layer and the gate electrode, the first insulating layer extending between the first bank pattern and the substrate;
a second insulating layer disposed between the gate and the second plate, the second insulating layer extending between the first barrier pattern and the second barrier pattern;
and the third insulating layer is arranged between the second electrode plate and the source drain electrode layer and extends to a position between the second barrier wall pattern and the third barrier wall pattern.
Optionally, the bottom of each of the lattice-like spaces exposes a surface of the substrate, or,
the bottom of each of the lattice-like spaces exposes a surface of the barrier layer facing away from the substrate, or,
the bottom of each lattice-like space exposes the surface of the first insulating layer facing away from the substrate, or,
the bottom of each lattice-like space exposes the surface of the second insulating layer facing away from the substrate, or,
the bottom of each lattice-like space exposes the surface of the third insulating layer facing away from the substrate.
Optionally, the substrate is exposed at an edge region of the display substrate, and the edge region is located at a side of the retaining wall structure far away from the display region.
Optionally, the orthographic projection of the lattice-shaped space on the substrate is a polygon, and corners of the polygon are rounded corners.
Based on the technical solution of the display substrate, a second aspect of the invention provides a display device, which includes the display substrate.
Based on the technical solution of the display substrate, a third aspect of the present invention provides a method for manufacturing a display substrate, for manufacturing the display substrate, the method including:
manufacturing a retaining wall structure at the periphery of a display area of the display substrate, wherein the orthographic projection of the retaining wall structure on the substrate of the display substrate is in a grid shape;
when the display substrate further includes a barrier layer, a first insulating layer, a second insulating layer, and a third insulating layer, the step of fabricating the dam structure in the peripheral region of the display substrate specifically includes:
manufacturing a barrier layer on the substrate, wherein the barrier layer covers the display area and an area located on the periphery of the display area;
manufacturing an active layer included by a thin film transistor in the display substrate on one side of the barrier layer, which is opposite to the substrate;
manufacturing a first insulating layer on one side of the active layer, which is opposite to the substrate, wherein the first insulating layer covers the display area and an area located at the periphery of the display area;
manufacturing a grid electrode included by the thin film transistor, a first polar plate included by a capacitor unit in the display substrate and a first retaining wall graph included by the retaining wall structure on one side, opposite to the substrate, of the first insulating layer through a one-step composition process;
manufacturing a second insulating layer on one side of the grid electrode, which is opposite to the substrate, wherein the second insulating layer covers the display area and an area around the display area;
manufacturing a second polar plate included by the capacitor unit and a second retaining wall pattern included by the retaining wall structure on one side, back to the substrate, of the second insulating layer through a one-step composition process;
manufacturing a third insulating layer on one side of the second plate, which is opposite to the substrate, wherein the third insulating layer covers the display area and an area around the display area;
manufacturing a source drain electrode layer included by the thin film transistor and a third barrier wall pattern included by the barrier wall structure on one side, opposite to the substrate, of the third insulating layer through a one-step composition process;
removing the barrier layer, the first insulating layer, the second insulating layer and the third insulating layer in the lattice-shaped spaces and the edge regions to expose the substrate in the lattice-shaped spaces and the edge regions;
the retaining wall body of the retaining wall structure limits the grid-shaped space; the edge region is positioned on one side of the retaining wall structure far away from the display region.
In the technical scheme provided by the invention, the retaining wall structure is arranged at the periphery of the display area and can comprise retaining wall strips extending along different directions, so that the orthographic projection of the retaining wall structure on the substrate of the display substrate is in a grid shape, when cracks are generated at the edge of the display substrate, the stress generated by the cracks extending towards the display area direction can be better released by the retaining wall strips extending along different directions in the process of extending the cracks towards the display area, and the cracks are effectively prevented from continuing to extend towards the display area.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic top view of a display substrate according to an embodiment of the invention;
FIG. 2 is an enlarged view of portion A of FIG. 1;
fig. 3 is a first schematic top view of a retaining wall structure according to an embodiment of the present invention;
fig. 4 is a second schematic top view of the retaining wall structure according to the embodiment of the present invention;
fig. 5 is a third schematic top view of a retaining wall structure according to an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view of a display area of a display substrate according to an embodiment of the invention;
fig. 7 is a schematic cross-sectional view of a retaining wall structure according to an embodiment of the invention.
Detailed Description
In order to further explain the display substrate, the manufacturing method thereof and the display device provided by the embodiment of the invention, the following detailed description is made with reference to the accompanying drawings.
Referring to fig. 1, fig. 2 and fig. 7, an embodiment of the invention provides a display substrate, including: the display device comprises a display area 30 and a retaining wall structure 20 arranged on the periphery of the display area 30, wherein the orthographic projection of the retaining wall structure 20 on a substrate 100 of the display substrate is in a grid shape.
Specifically, the specific structure of the retaining wall structure 20 is various, for example, the display area 30 of the display substrate is rectangular, and the retaining wall structure is located at the periphery of the display area 30 and surrounds at least three edges of the display area 30.
When the display substrate is packaged, the package structure 150 completely covers the display region 30, and covers at least a partial region between the display region 30 and the retaining wall structure 20, specifically, referring to fig. 1, a package boundary 40 of the package structure 150 is shown in fig. 1, which is more beneficial to ensuring the lateral reliability of the package. The specific structure of the encapsulation structure 150 may be set according to actual needs, for example, as shown in fig. 6, the encapsulation structure 150 includes a first inorganic encapsulation layer 151, an organic encapsulation layer 152, and a second inorganic encapsulation layer 153, which are stacked, and a side of the organic encapsulation layer 152 is to be wrapped in a boundary of the first inorganic encapsulation layer 151 and the second inorganic encapsulation layer 153. It is noted that the inorganic encapsulation layer is made by a chemical vapor deposition device or an atomic layer deposition device, and is patterned by using a mask. In the film forming process, due to the penetration of the reaction gas and the plasma, an inorganic film can be deposited at a certain distance under the mask.
The retaining wall structure 20 may include a plurality of retaining wall strips extending in different directions, and the plurality of retaining wall strips are arranged in a cross manner so that an orthographic projection of the retaining wall structure 20 on the substrate of the display substrate is in a grid shape; it should be noted that the extending direction of the retaining wall strips can be set according to actual needs, and for example, a preset angle is formed between the extending direction of the retaining wall strips and the extending direction of the boundary closest to the retaining wall strips in the display area 30, and the preset angle is between 0 degree and 90 degrees, including 0 degree and 90 degrees.
As can be seen from the specific structure of the display substrate, in the display substrate provided in the embodiment of the present invention, the retaining wall structures 20 are disposed at the periphery of the display region 30, and the retaining wall structures 20 can include retaining wall bars extending along different directions, so that the orthographic projection of the retaining wall structures 20 on the substrate of the display substrate is in a grid shape, so that when cracks are generated at the edge of the display substrate, in the process that the cracks extend towards the display region 30, the retaining wall bars extending along different directions included in the retaining wall structures 20 can better release the stress generated by the cracks extending towards the display region 30, thereby effectively preventing the cracks from continuing to extend towards the display region 30.
In addition, the retaining wall structure 20 with the above structure is arranged on the display substrate, so that the mechanical strength of the edge of the display substrate can be enhanced, and the edge of the display substrate is prevented from being curled and deformed.
As shown in fig. 2 to 5, in some embodiments, the retaining wall structure 20 includes a retaining wall body, the retaining wall body can define a plurality of grid-like spaces 50, the retaining wall body at least includes a first retaining wall strip C, a first included angle is formed between an extending direction of the first retaining wall strip C and an extending direction of a boundary closest to the first retaining wall strip C in the display area 30, and the first included angle is smaller than 90 degrees.
Specifically, the retaining wall structure 20 may include a retaining wall body, which can define a plurality of cellular spaces 50, and the specific distribution of the cellular spaces 50 may be set according to actual needs, for example, the cellular spaces 50 are distributed in an array.
The retaining wall body has various specific structures, and exemplarily, the retaining wall body at least includes a first retaining wall strip C, as shown in fig. 2 to 5, the first retaining wall strip C extends along a direction of a dotted-line double-headed arrow, a first included angle is formed between an extending direction of the first retaining wall strip C and an extending direction of a boundary (e.g., a boundary 301 in fig. 2) closest to the first retaining wall strip C in the display region 30, and the first included angle is smaller than 90 degrees; more preferably, the first included angle may be set to be less than 85 degrees.
In the display substrate provided in the above embodiment, the retaining wall body at least includes the first retaining wall strip C, so that when a crack is generated at the edge of the display substrate, the crack is in the process of extending to the display area 30, and the first retaining wall strip C can better release the stress generated by the crack extending to the display area 30, so as to effectively prevent the crack from continuing to extend to the display area 30.
In some embodiments, the retaining wall body further comprises:
a second included angle is formed between the extending direction of the second barrier rib B and the extending direction of the boundary closest to the second barrier rib B in the display area 30, and the second included angle is equal to 90 degrees; and the number of the first and second groups,
an outer frame body surrounding the first wall strips C and the second wall strips B, the first wall strips C, the second wall strips B, and the outer frame body defining the plurality of lattice-like spaces 50 in a region surrounded by the outer frame body; of both ends of the second barrier rib B in its own extending direction, at most only one end can be directly coupled with the outer frame.
Specifically, as shown in fig. 3 and 5, the second barrier rib B extends along the direction of the solid double-headed arrow, and a second included angle is formed between the extending direction of the second barrier rib B and the extending direction of the closest boundary to the second barrier rib B in the display area 30, and the second included angle is equal to 90 degrees.
The outer frame body that the barricade body includes can be for sealing the figure, just the profile of outer frame body can set up to regular figure or irregular figure as actual need. The first retaining wall strips C and the second retaining wall strips B can be all arranged in the region surrounded by the outer frame body, and the first retaining wall strips C, the second retaining wall strips B and the outer frame body can define the plurality of cellular spaces 50 in the region surrounded by the outer frame body.
In addition, at most one of the two ends of the second retaining wall strip B along the extending direction thereof may be directly coupled to the outer frame, and this structure enables at least one of the two ends of the second retaining wall strip B along the extending direction thereof to be directly coupled to the first retaining wall strip C, so that only one of the two ends of the second retaining wall strip B along the extending direction thereof is prevented from being directly overlapped with the other end of the outer frame by one second retaining wall strip B, and a passage extending along the second retaining wall strip B is prevented from being provided for a crack, thereby effectively preventing the crack from extending toward the display area 30.
It should be noted that the specific shape of the lattice-shaped spaces 50 may be set according to actual needs, for example, as shown in fig. 2, the orthographic projection of the lattice-shaped spaces 50 on the substrate 100 is triangular, as shown in fig. 3, the orthographic projection of the lattice-shaped spaces 50 on the substrate 100 is hexagonal, as shown in fig. 4, the orthographic projection of the lattice-shaped spaces 50 on the substrate 100 is quadrilateral, and as shown in fig. 5, the orthographic projection of the lattice-shaped spaces 50 on the substrate 100 is pentagonal.
In addition, when the orthographic projection of the lattice-like spaces 50 on the base 100 is a polygon, corners of the polygon may be rounded, which may better prevent cracks from being generated due to stress at the corners inside the lattice-like spaces 50.
As shown in fig. 6, in some embodiments, the display area 30 of the display substrate is provided with a thin film transistor array layer, the thin film transistor array layer includes a plurality of sub-pixel driving circuits distributed in an array, each sub-pixel driving circuit includes a plurality of thin film transistors and at least one capacitor unit; the thin film transistor comprises an active layer 110, a grid electrode 112 and a source drain electrode layer which are arranged in a stacked mode; the capacitor unit comprises a first polar plate 116 and a second polar plate 114 which are oppositely arranged, and the first polar plate 116 and the grid 112 are arranged in the same layer and the same material;
the retaining wall structure 20 includes a plurality of retaining wall patterns stacked on top of each other, the retaining wall patterns at least include a first retaining wall pattern 201, a second retaining wall pattern 202 and a third retaining wall pattern 203, the first retaining wall pattern 201 and the gate 112 are arranged with the same layer and the same material, the second retaining wall pattern 202 and the second diode 114 are arranged with the same layer and the same material, and the third retaining wall pattern 203 and the source drain electrode layer are arranged with the same layer and the same material.
Specifically, the display region 30 is provided with a thin film transistor array layer, and a plurality of anodes 132 and a plurality of light emitting units 140 located on a side of the thin film transistor array layer facing away from the substrate 100, the thin film transistor array layer includes a plurality of sub-pixel driving circuits distributed in an array, each sub-pixel driving circuit includes a plurality of thin film transistors and at least one capacitor unit; the anodes 132 correspond to the sub-pixel driving circuits one to one, and the anodes 132 are coupled to output electrodes (such as drain electrodes 122) of thin film transistors for outputting driving signals in the corresponding sub-pixel driving circuits; the light emitting units 140 correspond to the anodes 132 one by one, and the light emitting units 140 include organic light emitting material layers 141, a common transport layer 142, and cathodes 143, which are sequentially stacked on the corresponding anodes 132 in a direction away from the substrate 100.
Note that the thin film transistor includes an active layer 110, a gate electrode 112, a source electrode 121, and a drain electrode 122. The specific structure of the thin film transistor can comprise a top gate structure, a bottom gate structure or a double gate structure.
The display area 30 is further provided with a flat layer 131, a pixel defining layer 133 and spacers 134; the opening positions of the pixel defining layer 133 correspond to the positions of the anodes 132, the spacers can be formed on the non-opening areas of the pixel defining layer 133, the spacers can support a mask plate in an evaporation process, and the pixel defining layer 133 and the spacers 134 can be formed in the same patterning process by a half-tone mask technology.
In addition, the number of the capacitor units can be determined according to the actual circuit structure, and the capacitor units are generally used as storage capacitors, but not limited thereto; the capacitor unit may include a first plate 116 and a second plate 114 disposed opposite to each other, the first plate 116 may be disposed on the same layer as the gate 112, and the second plate 114 may be disposed on a side of the first plate 116 facing away from the substrate 100.
The retaining wall structure 20 may be formed by stacking a plurality of retaining wall patterns, and the number of the retaining wall patterns and the thickness of the retaining wall patterns in the direction perpendicular to the substrate 100 may be set according to actual requirements. The material of barricade figure also can select according to actual need, and is exemplary, the barricade figure adopts metal material preparation, and the barricade figure of metal material has better hardness, can form more effective the stopping to the crackle.
When the display area 30 is configured to include the above structure, it may be configured that the retaining wall structure 20 includes a plurality of retaining wall patterns stacked on top of each other, the retaining wall patterns at least include a first retaining wall pattern 201, a second retaining wall pattern 202, and a third retaining wall pattern 203, the first retaining wall pattern 201 and the gate 112 are disposed on the same layer and the same material, the second retaining wall pattern 202 and the second electrode 114 are disposed on the same layer and the same material, and the third retaining wall pattern 203 and the source and drain electrode layers (i.e., the source electrode 121 and the drain electrode 122 in the thin film transistor) are disposed on the same layer and the same material.
By the arrangement, the first retaining wall pattern 201 and the gate 112 can be formed in the same composition process, the second retaining wall pattern 202 and the second electrode plate 114 can be formed in the same composition process, and the third retaining wall pattern 203 and the source/drain electrode layer can be formed in the same composition process, so that the manufacturing process flow of the retaining wall structure 20 is effectively simplified, and the manufacturing cost of the display substrate is reduced.
As shown in fig. 6 and 7, in some embodiments, the display area 30 further includes: a barrier layer 101 disposed between the substrate 100 and the active layer 110, the barrier layer 101 extending between the first wall pattern 201 and the substrate 100; a first insulating layer 111 disposed between the active layer 110 and the gate electrode 112, the first insulating layer 111 extending between the first bank pattern 201 and the substrate 100; a second insulating layer 113 disposed between the gate electrode 112 and the second plate 114, the second insulating layer 113 extending between the first barrier wall pattern 201 and the second barrier wall pattern 202; and a third insulating layer 115 disposed between the second electrode plate 114 and the source/drain electrode layer, wherein the third insulating layer 115 extends between the second barrier pattern 202 and the third barrier pattern 203.
Specifically, the barrier layer 101, the first insulating layer 111, the second insulating layer 113, and the third insulating layer 115 may be further disposed in the display area 30 of the display substrate, and the specific distribution positions of these film layers may be set according to actual needs, and for example, these film layers may each cover the entire area of the display substrate, including the display area 30, and the entire peripheral area located at the periphery of the display area 30.
In more detail, when the first wall pattern 201 is disposed in the same material as the gate electrode 112 at the same layer, when the second barrier pattern 202 and the second electrode layer 114 are formed of the same material in the same layer, and the third barrier pattern 203 and the source/drain electrode layer are formed of the same material in the same layer, the barrier layer 101 may be further disposed to extend between the first wall pattern 201 and the substrate 100, the first insulating layer 111 extends between the first wall pattern 201 and the substrate 100, the second insulating layer 113 extends between the first barrier wall pattern 201 and the second barrier wall pattern 202, the third insulating layer 115 extends to between the second barrier pattern 202 and the third barrier pattern 203, this increases the height of the retaining wall structure 20 in the direction perpendicular to the base 100, which is more favorable for improving the crack-blocking capability of the retaining wall structure 20.
As shown in fig. 7, when the barrier layer 101, the first insulating layer 111, the second insulating layer 113, and the third insulating layer 115 are provided to extend to the peripheral region of the display substrate, the bottom of each lattice-shaped space 50 may be further provided to expose the surface of the substrate 100, or the bottom of each lattice-shaped space 50 may be provided to expose the surface of the barrier layer 101 facing away from the substrate 100, or the bottom of each lattice-shaped space 50 may be provided to expose the surface of the first insulating layer 111 facing away from the substrate 100, or the bottom of each lattice-shaped space 50 may be provided to expose the surface of the second insulating layer 113 facing away from the substrate 100, or the bottom of each lattice-shaped space 50 may be provided to expose the surface of the third insulating layer 115 facing away from the substrate 100.
Specifically, in the course of manufacturing the retaining wall structure 20, or after the completion of the manufacture of the retaining wall structure 20, one or more of the barrier layer 101 located in each lattice-shaped space 50, the first insulating layer 111 located in each lattice-shaped space 50, the second insulating layer 113 located in each lattice-shaped space 50, and the third insulating layer 115 located in each lattice-shaped space 50 may be removed, or the barrier layer 101 located in each lattice-shaped space 50, the first insulating layer 111 located in each lattice-shaped space 50, the second insulating layer 113 located in each lattice-shaped space 50, and the third insulating layer 115 located in each lattice-shaped space 50 may be left.
It is noted that in fig. 7, at the grid-like space 50, the portions between adjacent dotted lines are the respective film layers that are removed correspondingly.
One or more of barrier layer 101 in each lattice-like space 50, first insulating layer 111 in each lattice-like space 50, second insulating layer 113 in each lattice-like space 50, and third insulating layer 115 in each lattice-like space 50 are removed as described above, so that a path along barrier layer 101, first insulating layer 111, second insulating layer 113, and/or third insulating layer 115 to display region 30 for cracks is blocked at each lattice-like space 50, thereby further facilitating the barrier ability against cracks.
In some embodiments, an edge region 60 of the display substrate may be further disposed to expose the substrate 100, and the edge region 60 is located on a side of the retaining wall structure 20 away from the display region 30.
Specifically, in the process of manufacturing the display substrate, all the film layers (including the barrier layer 101, the first insulating layer 111, the second insulating layer 113, the third insulating layer 115, and the like) located in the edge region 60 may be removed to expose the substrate 100 located in the edge region 60, so that not only can the source of crack generation be effectively reduced, but also, when a crack is generated at the edge of the display substrate, the path of the crack extending to the display region 30 along each film layer located in the edge region 60 can be blocked at the edge region 60, thereby being more beneficial to improving the crack blocking capability.
The embodiment of the invention also provides a display device which comprises the display substrate provided by the embodiment.
Because the display substrate provided by the embodiment can effectively prevent the edge crack from extending towards the inside of the display substrate, the display device provided by the embodiment of the invention has the beneficial effects when the display device comprises the display substrate, and the description is omitted here.
The display device may be: any product or component with a display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer and the like.
In addition, the display device can be selected as a flexible organic electroluminescent display device, and the display device comprises a display substrate, wherein the substrate can be selected from a flexible substrate.
The embodiment of the invention also provides a manufacturing method of the display substrate, which is used for manufacturing the display substrate provided by the embodiment, and the manufacturing method comprises the following steps:
the retaining wall structure 20 is manufactured at the periphery of the display area 30 of the display substrate, and the orthographic projection of the retaining wall structure 20 on the substrate 100 of the display substrate is in a grid shape.
Specifically, the specific structure of the retaining wall structure 20 is various, and exemplarily, the display area 30 of the display substrate is rectangular, and the retaining wall structure 20 is located at the periphery of the display area 30 and surrounds at least three edges of the display area 30.
The retaining wall structure 20 may include a plurality of retaining wall bars extending along different directions, and the plurality of retaining wall bars are arranged in a cross manner so that an orthographic projection of the retaining wall structure 20 on the substrate 100 of the display substrate is in a grid shape; it should be noted that the extending direction of the retaining wall strips can be set according to actual needs, and for example, a preset angle is formed between the extending direction of the retaining wall strips and the extending direction of the boundary closest to the retaining wall strips in the display area 30, and the preset angle is between 0 degree and 90 degrees, including 0 degree and 90 degrees.
In the display substrate manufactured by the manufacturing method provided by the embodiment of the invention, the retaining wall structure 20 is arranged on the periphery of the display area 30, and the retaining wall structure 20 can include retaining wall bars extending along different directions, so that the orthographic projection of the retaining wall structure 20 on the substrate 100 of the display substrate is in a grid shape, when cracks are generated at the edge of the display substrate, in the process that the cracks extend towards the display area 30, the retaining wall bars extending along different directions, which are included in the retaining wall structure 20, can better release the stress generated by the cracks extending towards the display area 30, thereby effectively preventing the cracks from continuing to extend towards the display area 30.
In some embodiments, when the display substrate further includes a barrier layer 101, a first insulating layer 111, a second insulating layer 113, and a third insulating layer 115, the step of fabricating the retaining wall structure 20 in the peripheral region of the display substrate specifically includes:
manufacturing a barrier layer 101 on the substrate 100, wherein the barrier layer 101 covers the display area 30 and an area located at the periphery of the display area 30; specifically, before the tft array layer is formed, a barrier layer 101 may be formed on the substrate 100, where the barrier layer 101 may cover the entire area of the substrate 100, and the barrier layer may be formed of multiple layers of inorganic materials, but is not limited thereto.
Manufacturing an active layer 110 included in a thin film transistor in the display substrate on one side of the barrier layer 101, which faces away from the substrate 100; specifically, after the barrier layer 101 is fabricated, the active layer 110 included in each thin film transistor may be fabricated on a side of the barrier layer 101 opposite to the substrate 100.
Manufacturing a first insulating layer 111 on a side of the active layer 110 opposite to the substrate 100, wherein the first insulating layer 111 covers the display region 30 and a region around the display region 30; specifically, after the active layer 110 is fabricated, a first insulating layer 111 may be fabricated on a side of the active layer 110 facing away from the substrate 100, and the first insulating layer 111 may cover the entire area of the substrate 100.
Through a one-step patterning process, a gate 112 included in the thin film transistor, a first plate 116 included in a capacitor unit in the display substrate, and a first retaining wall pattern 201 included in the retaining wall structure 20 are formed on a side of the first insulating layer 111 opposite to the substrate 100; specifically, after the first insulating layer 111 is fabricated, a first metal layer may be formed on the surface of the first insulating layer 111 opposite to the substrate 100, and a first barrier pattern 201 included in the barrier structure 20 and a first plate 116 included in the capacitor unit in the display substrate may be formed at the same time by performing a patterning process on the first metal layer.
Manufacturing a second insulating layer 113 on a side of the gate 112 facing away from the substrate 100, wherein the second insulating layer 113 covers the display area 30 and an area around the display area 30; specifically, after the patterning of the first metal layer is completed, the second insulating layer 113 covering the entire area of the substrate 100 is continuously formed.
Through a one-step patterning process, a second plate 114 included in the capacitor unit and a second barrier pattern 202 included in the barrier structure 20 are formed on a side of the second insulating layer 113 facing away from the substrate 100; specifically, after the second insulating layer 113 is fabricated, a second metal layer may be formed on a surface of the second insulating layer 113 opposite to the substrate 100, and a second plate 114 included in the capacitor unit and a second barrier pattern 202 included in the barrier structure 20 are simultaneously formed by performing a patterning process on the second metal layer.
A third insulating layer 115 is formed on a side of the second plate 114 facing away from the substrate 100, and the third insulating layer 115 covers the display area 30 and an area around the display area 30; specifically, after the patterning of the second metal layer is completed, the formation of the third insulating layer 115 covering the entire area of the substrate 100 is continued.
Through a one-step composition process, a source/drain electrode layer included in the thin film transistor and a third barrier pattern 203 included in the barrier structure 20 are formed on a side of the third insulating layer 115 facing away from the substrate 100; specifically, after the third insulating layer 115 is fabricated, a third metal layer may be formed on a surface of the third insulating layer 115 opposite to the substrate 100, and a source/drain electrode layer included in the thin film transistor and a third blocking wall pattern 203 included in the blocking wall structure 20 are simultaneously formed by performing a patterning process on the third metal layer.
It is to be noted that, before the third metal layer is formed, the first insulating layer 111, the second insulating layer 113, and the second insulating layer 113 in the display region 30 may be etched to form two via holes, where the two via holes can expose portions of the active layer 110 for coupling with the source electrode 121 and the drain electrode 122, so that after the source and drain electrode layers are formed, the source electrode 121 in the source and drain electrode layers can be coupled with one exposed portion of the active layer 110 through one via hole, and the drain electrode 122 in the source and drain electrode layers can be coupled with another exposed portion of the active layer 110 through another via hole.
In addition, during the process of forming the two via holes by etching, the barrier layer 101, the first insulating layer 111, the second insulating layer 113, and the third insulating layer 115 in the lattice-shaped spaces 50 and the edge region 60 may be simultaneously removed by etching, so as to expose the substrate 100 in the lattice-shaped spaces 50 and the edge region 60. The retaining wall structure 20 includes retaining wall bodies defining the lattice-like spaces 50; the edge region 60 is located on a side of the retaining wall structure 20 away from the display region 30.
When the manufacturing method provided by the above embodiment is adopted to manufacture the display substrate, the first retaining wall pattern 201 and the gate 112 can be formed in the same composition process, the second retaining wall pattern 202 and the second diode 114 can be formed in the same composition process, and the third retaining wall pattern 203 and the source/drain electrode layer can be formed in the same composition process, so that the manufacturing process flow of the retaining wall structure 20 is effectively simplified, and the manufacturing cost of the display substrate is reduced.
Moreover, in the process of manufacturing the display substrate, each film layer (including the barrier layer 101, the first insulating layer 111, the second insulating layer 113, the third insulating layer 115, and the like) located in each lattice-shaped space 50 and the edge region 60 can be removed to expose the substrate 100 located in each lattice-shaped space 50 and the edge region 60, so that when a crack is generated at the edge of the display substrate, the path of the crack extending to the display region 30 along each film layer located in each lattice-shaped space 50 and the edge region 60 can be blocked in each lattice-shaped space 50 and the edge region 60, thereby further facilitating the increase of the crack blocking capability.
It should be noted that, in the present specification, all the embodiments are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the method embodiments, since they are substantially similar to the product embodiments, they are described simply, and reference may be made to the partial description of the product embodiments for relevant points.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected," "coupled," or "connected," and the like, are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.
In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A display substrate, comprising: the display area is in with the setting peripheral barricade structure of display area, barricade structure is in orthographic projection on the basement of display substrates is latticed.
2. The display substrate of claim 1, wherein the retaining wall structure comprises a retaining wall body, the retaining wall body can define a plurality of grid-like spaces, the retaining wall body at least comprises a first retaining wall strip, a first included angle is formed between the extending direction of the first retaining wall strip and the extending direction of the boundary closest to the first retaining wall strip in the display area, and the first included angle is smaller than 90 degrees.
3. The display substrate of claim 2, wherein the retaining wall body further comprises:
a second included angle is formed between the extending direction of the second wall blocking strip and the extending direction of the boundary, closest to the second wall blocking strip, in the display area, and the second included angle is equal to 90 degrees;
the outer frame body surrounds the first retaining wall strips and the second retaining wall strips, and the first retaining wall strips, the second retaining wall strips and the outer frame body define a plurality of grid-shaped spaces in an area surrounded by the outer frame body;
at most only one of both ends of the second barrier rib in its own extending direction can be directly coupled to the outer frame.
4. The display substrate according to claim 3, wherein the display area of the display substrate is provided with a thin film transistor array layer, the thin film transistor array layer comprises a plurality of sub-pixel driving circuits distributed in an array, and each sub-pixel driving circuit comprises a plurality of thin film transistors and at least one capacitor unit; the thin film transistor comprises an active layer, a grid electrode and a source drain electrode layer which are arranged in a stacked mode; the capacitor unit comprises a first polar plate and a second polar plate which are oppositely arranged, and the first polar plate and the grid are arranged on the same layer and made of the same material;
the retaining wall structure comprises a plurality of retaining wall graphs which are stacked, the retaining wall graphs at least comprise a first retaining wall graph, a second retaining wall graph and a third retaining wall graph, the first retaining wall graph and the grid are arranged with the same layer and the same material, the second retaining wall graph and the second grid are arranged with the same layer and the same material, and the third retaining wall graph and the source drain electrode layer are arranged with the same layer and the same material.
5. The display substrate of claim 4, wherein the display area further comprises:
a blocking layer disposed between the substrate and the active layer, the blocking layer extending between the first dam pattern and the substrate;
a first insulating layer disposed between the active layer and the gate electrode, the first insulating layer extending between the first bank pattern and the substrate;
a second insulating layer disposed between the gate and the second plate, the second insulating layer extending between the first barrier pattern and the second barrier pattern;
and the third insulating layer is arranged between the second electrode plate and the source drain electrode layer and extends to a position between the second barrier wall pattern and the third barrier wall pattern.
6. The display substrate of claim 5,
the bottom of each of the lattice-like spaces exposes the surface of the substrate, or,
the bottom of each of the lattice-like spaces exposes a surface of the barrier layer facing away from the substrate, or,
the bottom of each lattice-like space exposes the surface of the first insulating layer facing away from the substrate, or,
the bottom of each lattice-like space exposes the surface of the second insulating layer facing away from the substrate, or,
the bottom of each lattice-like space exposes the surface of the third insulating layer facing away from the substrate.
7. The display substrate of claim 5, wherein an edge region of the display substrate exposes the substrate, and the edge region is located on a side of the retaining wall structure away from the display region.
8. The display substrate of claim 2, wherein the orthographic projection of the grid space on the base is a polygon, and the corners of the polygon are rounded corners.
9. A display device comprising the display substrate according to any one of claims 1 to 8.
10. A method for manufacturing a display substrate, the method being used for manufacturing the display substrate according to any one of claims 1 to 8, the method comprising:
manufacturing a retaining wall structure at the periphery of a display area of the display substrate, wherein the orthographic projection of the retaining wall structure on the substrate of the display substrate is in a grid shape;
when the display substrate further includes a barrier layer, a first insulating layer, a second insulating layer, and a third insulating layer, the step of fabricating the dam structure in the peripheral region of the display substrate specifically includes:
manufacturing a barrier layer on the substrate, wherein the barrier layer covers the display area and an area located on the periphery of the display area;
manufacturing an active layer included by a thin film transistor in the display substrate on one side of the barrier layer, which is opposite to the substrate;
manufacturing a first insulating layer on one side of the active layer, which is opposite to the substrate, wherein the first insulating layer covers the display area and an area located at the periphery of the display area;
manufacturing a grid electrode included by the thin film transistor, a first polar plate included by a capacitor unit in the display substrate and a first retaining wall graph included by the retaining wall structure on one side, opposite to the substrate, of the first insulating layer through a one-step composition process;
manufacturing a second insulating layer on one side of the grid electrode, which is opposite to the substrate, wherein the second insulating layer covers the display area and an area around the display area;
manufacturing a second polar plate included by the capacitor unit and a second retaining wall pattern included by the retaining wall structure on one side, back to the substrate, of the second insulating layer through a one-step composition process;
manufacturing a third insulating layer on one side of the second plate, which is opposite to the substrate, wherein the third insulating layer covers the display area and an area around the display area;
manufacturing a source drain electrode layer included by the thin film transistor and a third barrier wall pattern included by the barrier wall structure on one side, opposite to the substrate, of the third insulating layer through a one-step composition process;
removing the barrier layer, the first insulating layer, the second insulating layer and the third insulating layer in the lattice-shaped spaces and the edge regions to expose the substrate in the lattice-shaped spaces and the edge regions;
the retaining wall body of the retaining wall structure limits the grid-shaped space; the edge region is positioned on one side of the retaining wall structure far away from the display region.
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| CN114114762A (en) * | 2020-08-25 | 2022-03-01 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
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