CN110767257A - Microprocessor platform-oriented memory verification system - Google Patents
Microprocessor platform-oriented memory verification system Download PDFInfo
- Publication number
- CN110767257A CN110767257A CN201911057007.6A CN201911057007A CN110767257A CN 110767257 A CN110767257 A CN 110767257A CN 201911057007 A CN201911057007 A CN 201911057007A CN 110767257 A CN110767257 A CN 110767257A
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- Prior art keywords
- microprocessor
- verification
- microprocessor platform
- platform
- control software
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3452—Performance evaluation by statistical analysis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
Abstract
The invention discloses a microprocessor platform-oriented memory verification system, which comprises a verification system, a control software unit, a verification jig and a test host, wherein the verification system is respectively connected with the control software unit, the verification jig and the test host, the verification host is connected with a plurality of microprocessor platforms, and the plurality of microprocessor platforms are connected with a memory.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a memory verification system facing a microprocessor platform.
Background
In the current verification system, different microprocessor manufacturers have different instruction calling modes due to different architectures, and multiple verification software and tools are required under a multi-architecture environment, and the verification software and tools cannot be shared, so that the waste and redundancy of resources are caused. In view of the situation, the developed verification system can be compatible with the memory verification of the microprocessor platforms of many brands as much as possible, so that the manpower development cost can be reduced, the risk of misuse in the verification process is avoided, and the manpower cost can be saved.
The traditional microprocessor platform uses a universal serial bus communication protocol for communication, but has an unstable phenomenon in practical use, communication based on a transmission control protocol/internet protocol is added, a serial port communication mode is integrated, multiple microprocessor communication modes are compatible, and the problem of protocol incompatibility among microprocessors is solved.
Disclosure of Invention
The present invention is directed to a memory verification system for a microprocessor platform, so as to solve the problems of the background art mentioned above.
In order to achieve the purpose, the invention provides the following technical scheme: a memory verification system facing a microprocessor platform comprises a verification system, a control software unit, a verification jig and a test host, wherein the verification system is respectively connected with the control software unit, the verification jig and the test host, the verification host is connected with a plurality of microprocessor platforms, and the microprocessor platforms are connected with a memory.
Preferably, the verification jig comprises a single-chip microcomputer, a power supply module, a relay control module and a microprocessor platform, the single-chip microcomputer is respectively connected with the power supply module and the relay control module, the power supply module is electrically connected with the relay control module and the microprocessor platform, the relay control module is connected with the microprocessor platform, the single-chip microcomputer is connected with the microprocessor platform through a communication module, and the microprocessor platform is connected with a universal serial bus communication protocol module.
Preferably, the plurality of microprocessor platforms include a first microprocessor platform, a second microprocessor platform, a third microprocessor platform, and an nth microprocessor platform, where N is an integer greater than 3.
Preferably, the using method comprises the following steps:
A. when the user uses the system, the verification host carries out project setting/specific parameter setting from the control software, then the microprocessor platform is controlled by the jig, and the interconnection is carried out by adopting a plurality of protocol communication modes, so that the compatibility of a plurality of protocol microprocessor communication protocols is realized, and the condition of protocol incompatibility among the microprocessors is solved;
B. then the microprocessor carries out power on-off verification, aging verification, functional verification, reliability verification and performance test verification on the memory;
C. when the command is issued, the control software firstly judges through the characteristic judgment that the microprocessor platform is an operating system such as Microsoft/Eunism/Linux/android and the like, then uses the corresponding language to carry out the command on the microprocessor platform, and the microprocessor platform returns to the execution state after the execution is finished, and is integrated and counted by the control software.
Compared with the prior art, the invention has the beneficial effects that: the invention can realize power-on and power-off verification, aging verification, functional verification, reliability verification and performance verification, multiple long-time verification is carried out on a single verification item, the execution data returned by the microprocessor every time is recorded and counted by the control software, the verification is sequentially completed according to the preset verification flow, and the verification can also be carried out in a mixed mode.
Drawings
FIG. 1 is a schematic block diagram of the system of the present invention;
fig. 2 is a diagram of a structure of a verification fixture according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-2, the present invention provides a technical solution: a memory verification system facing a microprocessor platform comprises a verification system 1, a control software unit 2, a verification jig 3 and a test host 4, wherein the verification system 1 is respectively connected with the control software unit 2, the verification jig 3 and the test host 4, the verification host 4 is connected with a plurality of microprocessor platforms 5, and the microprocessor platforms 5 are connected with a memory 6; the plurality of microprocessor platforms 5 include a first microprocessor platform, a second microprocessor platform, a third microprocessor platform, and an nth microprocessor platform, where N is an integer greater than 3.
In the invention, the verification jig 3 comprises a single-chip microcomputer 7, a power supply module 8, a relay control module 9 and a microprocessor platform 5, wherein the single-chip microcomputer 7 is respectively connected with the power supply module 8 and the relay control module 9, the power supply module 8 is electrically connected with the relay control module 9 and the microprocessor platform 5, the relay control module 9 is connected with the microprocessor platform 5, the single-chip microcomputer 7 is connected with the microprocessor platform 5 through a communication module 10, and the microprocessor platform 5 is connected with a universal serial bus communication protocol module 11. The verification jig is controlled by a microcomputer of a single chip microcomputer in a programming mode, is controlled by a relay and is interconnected in a multi-protocol communication mode, multiple communication protocols of the microprocessors are compatible, and the problem of protocol incompatibility among the microprocessors is solved.
The using method of the invention comprises the following steps:
A. when the user uses the system, the verification host carries out project setting/specific parameter setting from the control software, then the microprocessor platform is controlled by the jig, and the interconnection is carried out by adopting a plurality of protocol communication modes, so that the compatibility of a plurality of protocol microprocessor communication protocols is realized, and the condition of protocol incompatibility among the microprocessors is solved;
B. then the microprocessor carries out power on-off verification, aging verification, functional verification, reliability verification and performance test verification on the memory;
C. when the command is issued, the control software firstly judges through the characteristic judgment that the microprocessor platform is an operating system such as Microsoft/Eunism/Linux/android and the like, then uses the corresponding language to carry out the command on the microprocessor platform, and the microprocessor platform returns to the execution state after the execution is finished, and is integrated and counted by the control software.
In summary, the present invention can realize power-on/power-off verification, aging verification, functionality verification, reliability verification, and performance verification, and perform multiple long-time verification on a single verification item, and each time the microprocessor returns execution data, the microprocessor records and counts by the control software, and completes the verification in sequence according to a preset verification flow, or performs verification in a mixed manner.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (4)
1. A microprocessor platform oriented memory validation system, comprising: the device comprises a verification system (1), a control software unit (2), a verification jig (3) and a test host (4), wherein the verification system (1) is respectively connected with the control software unit (2), the verification jig (3) and the test host (4), the verification host (4) is connected with a plurality of microprocessor platforms (5), and the microprocessor platforms (5) are connected with a memory (6).
2. The microprocessor platform oriented memory validation system of claim 1, wherein: verify tool (3) and include single chip microcomputer (7), power module (8), relay control module (9) and microprocessor platform (5), power module (8), relay control module (9) are connected respectively in single chip microcomputer (7), power module (8) electric connection relay control module (9) and microprocessor platform (5), microprocessor platform (5) are connected in relay control module (9), single chip microcomputer (7) are through communication module (10) connection microprocessor platform (5), universal serial bus communication protocol module (11) is connected in microprocessor platform (5).
3. The microprocessor platform oriented memory validation system of claim 1, wherein: the plurality of microprocessor platforms (5) comprise a first microprocessor platform, a second microprocessor platform, a third microprocessor platform and an Nth microprocessor platform, wherein N is an integer larger than 3.
4. Use of a microprocessor platform oriented memory validation system according to claim 1, characterized in that: the using method comprises the following steps:
A. when the user uses the system, the verification host carries out project setting/specific parameter setting from the control software, then the microprocessor platform is controlled by the jig, and the interconnection is carried out by adopting a plurality of protocol communication modes, so that the compatibility of a plurality of protocol microprocessor communication protocols is realized, and the condition of protocol incompatibility among the microprocessors is solved;
B. then the microprocessor carries out power on-off verification, aging verification, functional verification, reliability verification and performance test verification on the memory;
C. when the command is issued, the control software firstly judges through the characteristic judgment that the microprocessor platform is an operating system such as Microsoft/Eunism/Linux/android and the like, then uses the corresponding language to carry out the command on the microprocessor platform, and the microprocessor platform returns to the execution state after the execution is finished, and is integrated and counted by the control software.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911057007.6A CN110767257A (en) | 2019-10-31 | 2019-10-31 | Microprocessor platform-oriented memory verification system |
| PCT/CN2019/119835 WO2021082114A1 (en) | 2019-10-31 | 2019-11-21 | Microprocessor platform-oriented memory verification system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911057007.6A CN110767257A (en) | 2019-10-31 | 2019-10-31 | Microprocessor platform-oriented memory verification system |
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| CN110767257A true CN110767257A (en) | 2020-02-07 |
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| CN201911057007.6A Pending CN110767257A (en) | 2019-10-31 | 2019-10-31 | Microprocessor platform-oriented memory verification system |
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| CN (1) | CN110767257A (en) |
| WO (1) | WO2021082114A1 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103038751A (en) * | 2010-05-28 | 2013-04-10 | 爱德万测试公司 | Flexible storage interface tester with variable parallelism and firmware upgradeability |
| US20150058685A1 (en) * | 2013-08-21 | 2015-02-26 | Samsung Electronics Co., Ltd. | Method and system of testing semiconductor memory |
| CN105144114A (en) * | 2013-02-21 | 2015-12-09 | 爱德万测试公司 | A tester with mixed protocol engine in a FPGA block |
| CN105378494A (en) * | 2013-02-21 | 2016-03-02 | 爱德万测试公司 | Test architecture having multiple fpga based hardware accelerator blocks for testing multiple duts independently |
| US20160239666A1 (en) * | 2013-01-23 | 2016-08-18 | Seagate Technology Llc | Non-deterministic encryption |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013074107A1 (en) * | 2011-11-17 | 2013-05-23 | Intel Corporation | Method, apparatus and system for memory validation |
| EP2875431A4 (en) * | 2012-07-17 | 2016-04-13 | Hewlett Packard Development Co | System and method for operating system agnostic hardware validation |
| US9712406B2 (en) * | 2013-03-15 | 2017-07-18 | Netgear, Inc. | Method and apparatus for analyzing and verifying functionality of multiple network devices |
| CN205484607U (en) * | 2016-03-18 | 2016-08-17 | 深圳长城开发科技股份有限公司 | Electron product aging automatic testing platform |
| CN107515803A (en) * | 2017-08-25 | 2017-12-26 | 郑州云海信息技术有限公司 | A kind of storing performance testing method and device |
-
2019
- 2019-10-31 CN CN201911057007.6A patent/CN110767257A/en active Pending
- 2019-11-21 WO PCT/CN2019/119835 patent/WO2021082114A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103038751A (en) * | 2010-05-28 | 2013-04-10 | 爱德万测试公司 | Flexible storage interface tester with variable parallelism and firmware upgradeability |
| US20160239666A1 (en) * | 2013-01-23 | 2016-08-18 | Seagate Technology Llc | Non-deterministic encryption |
| CN105144114A (en) * | 2013-02-21 | 2015-12-09 | 爱德万测试公司 | A tester with mixed protocol engine in a FPGA block |
| CN105378494A (en) * | 2013-02-21 | 2016-03-02 | 爱德万测试公司 | Test architecture having multiple fpga based hardware accelerator blocks for testing multiple duts independently |
| US20150058685A1 (en) * | 2013-08-21 | 2015-02-26 | Samsung Electronics Co., Ltd. | Method and system of testing semiconductor memory |
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| WO2021082114A1 (en) | 2021-05-06 |
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Application publication date: 20200207 |