CN110765041A - Adaptive Nand Flash read-write speed adjusting system - Google Patents

Adaptive Nand Flash read-write speed adjusting system Download PDF

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Publication number
CN110765041A
CN110765041A CN201911005374.1A CN201911005374A CN110765041A CN 110765041 A CN110765041 A CN 110765041A CN 201911005374 A CN201911005374 A CN 201911005374A CN 110765041 A CN110765041 A CN 110765041A
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read
speed
write
control module
temperature
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CN110765041B (en
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刘慧婕
仇旭东
赵斌
李岩
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Tianjin Jinhang Computing Technology Research Institute
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Tianjin Jinhang Computing Technology Research Institute
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3003Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3037Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3058Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention belongs to the technical field of memories, and particularly relates to a self-adaptive Nand Flash read-write speed adjusting system. Compared with the prior art, compared with the commonly adopted Nand-flash reading and writing with single set rate, the system can adjust the reading and writing rate according to the external environment, furthest ensures the reading and writing speed and correctness, and is more suitable for the application in severe environment with large temperature change. Therefore, the invention provides a system for dynamically adjusting the read-write speed of the Nand-flash along with the temperature change, which can ensure the correctness of data and the read-write efficiency to a certain extent.

Description

Adaptive Nand Flash read-write speed adjusting system
Technical Field
The invention belongs to the technical field of memories, and particularly relates to a self-adaptive Nand Flash read-write speed adjusting system.
Background
The Nand-Flash memory is one of Flash memories, adopts a nonlinear macro-unit mode inside the Nand-Flash memory, and provides a cheap and effective solution for realizing a solid-state large-capacity memory. The Nand-flash memory has the advantages of large capacity, high rewriting speed and the like, is suitable for storing a large amount of data, and is widely applied to the civil and military fields.
In some engineering test projects, besides the severe test environment, the test cost is very high, so that in order to save the test cost, the requirements on the reliability of test equipment are severe, and particularly, the requirements on the integrity and the correctness of test data are very high. The Nand-flash is the best choice for such applications due to its advantages of high speed, high storage density, shock resistance, etc. However, due to the structural characteristics and the manufacturing process limitations, errors exist in the Nand-flash application, and the data of the whole block or page is generally not invalid when an error occurs, but a single-bit or multi-bit error occurs in one page. In addition, the read-write performance of the Nand-flash is affected by environmental factors, the response speed of the Nand-flash after operation becomes slow along with the increase or decrease of the temperature, and if the Nand-flash is still read and written at a high speed, large-scale data errors may occur. Data of a single bit or a plurality of bits can be corrected through a corresponding error correction algorithm, but large-scale errors cannot be reasonably processed. Therefore, under the condition of high temperature or low temperature, in order to ensure the correctness of reading and writing, the corresponding reading and writing speed must be reduced. That is, in a relatively severe environment, the temperature change is relatively large, and the corresponding read-write speed needs to be adjusted according to the external temperature to ensure the correctness of data.
At the present stage, in order to maintain the correctness of data reading and writing under the conditions of low temperature and high temperature, when the Nand-flash reading and writing speed is set, a lower reading and writing speed which does not make mistakes under the high and low temperature environment is generally selected to ensure the correctness of reading and writing. However, the speed adopted at this time is only the speed under the ideal experiment condition, and the experiment condition and the environment condition in the practical application have a certain difference, and there is still a possibility that an error occurs when the actual reading and writing is performed under the speed condition.
Disclosure of Invention
Technical problem to be solved
The technical problem to be solved by the invention is as follows: how to provide a self-adaptive Nand Flash read-write speed adjusting system.
(II) technical scheme
In order to solve the technical problem, the invention provides a self-adaptive Nand Flash read-write speed adjusting system, which comprises: the device comprises a core control module, a read-write control module and a speed adjusting module; the core control module is used for sensing temperature change and detecting and correcting errors; the read-write control module is used for completing read-write control; the speed adjusting module is used for completing the adjusting function of the reading and writing speed along with the temperature change;
in particular, the method of manufacturing a semiconductor device,
(1) firstly, a read-write control module controls to read and write the Nand-flash at a conventional speed, and if the core control module detects that an error occurs, the current temperature is obtained through a temperature sensing device of the core control module;
(2) if the temperature is unchanged, the core control module uses an error correction algorithm to correct data with a single bit or a plurality of bits;
(3) if the temperature is changed indeed, the speed adjusting module adjusts the corresponding read-write speed of the read-write control module, so that large-scale data errors are avoided;
(4) if the core control module still detects that a large-scale error occurs after the speed is adjusted, the speed adjusting module continuously reduces the reading and writing speed of the reading and writing control module;
(5) after a block of data is read/written, the core control module acquires the current temperature again to see whether the normal temperature is recovered, if the normal temperature is recovered, the speed adjusting module adjusts the read-write speed of the read-write control module to be the conventional speed, and if the normal temperature is still in the high-temperature or low-temperature environment, the current read-write speed is kept unchanged.
The plurality of modules are matched with each other, the read-write speed of the Nand-flash is adjusted according to the change of the external temperature, and correct and efficient read-write is guaranteed.
The method comprises the following steps that firstly, a read-write control module controls to read and write the Nand-flash at a conventional speed, if the core control module detects that an error occurs, a temperature sensing device of the core control module is used for acquiring the current temperature:
after reading/writing a page, the core control module performs error detection on corresponding data.
If the temperature changes indeed, the speed adjusting module adjusts the corresponding read-write speed of the read-write control module, wherein:
and the regulation rule of the speed regulation module correspondingly reduces the speed by 0.5M/S according to the temperature increase or decrease by ten degrees.
If the core control module still detects that a large-scale error occurs after the speed is adjusted, the speed adjusting module continues to reduce the read-write speed of the read-write control module:
after the speed adjustment is finished, the read-write control module starts to read and write according to the adjusted speed, after one page of read-write is finished, the core control module detects whether large-scale errors still occur again, and if the large-scale errors occur, the speed is continuously reduced by the error adjusting module.
Wherein the continuing to decrease by the fault adjustment module decreases at intervals of 0.5M/S.
If the current read-write speed is still in the high-temperature or low-temperature environment, keeping the current read-write speed unchanged:
and if the temperature is still high or low, continuing to read and write at the adjusted current speed, and re-detecting the temperature by the core control module after reading/writing one block of data each time.
(III) advantageous effects
Compared with the prior art, compared with the usually adopted Nand-flash read-write system with single set rate, the system can adjust the read-write rate according to the external environment, furthest ensures the read-write speed and the correctness, and is more suitable for the application in severe environment with large temperature change. Therefore, the invention provides a system for dynamically adjusting the read-write speed of the Nand-flash along with the temperature change, which can ensure the correctness of data and the read-write efficiency to a certain extent.
Drawings
FIG. 1 is a flow chart of the technical solution of the present invention.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
In order to solve the technical problem, the invention provides a self-adaptive Nand Flash read-write speed adjusting system, which comprises: the device comprises a core control module, a read-write control module and a speed adjusting module; the core control module is used for sensing temperature change and detecting and correcting errors; the read-write control module is used for completing read-write control; the speed adjusting module is used for completing the adjusting function of the reading and writing speed along with the temperature change;
in particular, the method of manufacturing a semiconductor device,
(1) firstly, a read-write control module controls to read and write the Nand-flash at a conventional speed, and if the core control module detects that an error occurs, the current temperature is obtained through a temperature sensing device of the core control module;
(2) if the temperature is unchanged, the core control module uses an error correction algorithm to correct data with a single bit or a plurality of bits;
(3) if the temperature is changed indeed, the speed adjusting module adjusts the corresponding read-write speed of the read-write control module, so that large-scale data errors are avoided;
(4) if the core control module still detects that a large-scale error occurs after the speed is adjusted, the speed adjusting module continuously reduces the reading and writing speed of the reading and writing control module;
(5) after a block of data is read/written, the core control module acquires the current temperature again to see whether the normal temperature is recovered, if the normal temperature is recovered, the speed adjusting module adjusts the read-write speed of the read-write control module to be the conventional speed, and if the normal temperature is still in the high-temperature or low-temperature environment, the current read-write speed is kept unchanged.
The plurality of modules are matched with each other, the read-write speed of the Nand-flash is adjusted according to the change of the external temperature, and correct and efficient read-write is guaranteed.
The method comprises the following steps that firstly, a read-write control module controls to read and write the Nand-flash at a conventional speed, if the core control module detects that an error occurs, a temperature sensing device of the core control module is used for acquiring the current temperature:
after reading/writing a page, the core control module performs error detection on corresponding data.
If the temperature changes indeed, the speed adjusting module adjusts the corresponding read-write speed of the read-write control module, wherein:
and the regulation rule of the speed regulation module correspondingly reduces the speed by 0.5M/S according to the temperature increase or decrease by ten degrees.
If the core control module still detects that a large-scale error occurs after the speed is adjusted, the speed adjusting module continues to reduce the read-write speed of the read-write control module:
after the speed adjustment is finished, the read-write control module starts to read and write according to the adjusted speed, after one page of read-write is finished, the core control module detects whether large-scale errors still occur again, and if the large-scale errors occur, the speed is continuously reduced by the error adjusting module.
Wherein the continuing to decrease by the fault adjustment module decreases at intervals of 0.5M/S.
If the current read-write speed is still in the high-temperature or low-temperature environment, keeping the current read-write speed unchanged:
and if the temperature is still high or low, continuing to read and write at the adjusted current speed, and re-detecting the temperature by the core control module after reading/writing one block of data each time.
In addition, the invention also provides a self-adaptive Nand Flash read-write speed adjusting method, which is implemented based on a read-write speed adjusting system, wherein the read-write speed adjusting system comprises: the device comprises a core control module, a read-write control module and a speed adjusting module; the read-write speed adjusting method comprises the following steps:
step 1: the read-write control module controls the Nand-flash to be read and written according to a conventional speed, and if the core control module detects that an error occurs, the current temperature is obtained through a temperature sensing device of the core control module;
step 2: if the temperature is unchanged, error correction algorithm is used for correcting data of single bit or a plurality of bits;
and step 3: if the temperature is changed indeed, the speed adjusting module adjusts the corresponding reading and writing speed to avoid large-scale data errors;
and 4, step 4: if the core control module still detects that a large-scale error occurs after the speed is adjusted, the speed adjusting module continues to reduce the reading and writing speed;
and 5: after a block of data is read/written, the core control module acquires the current temperature again to see whether the normal temperature is recovered, if the normal temperature is recovered, the speed is adjusted to be the conventional speed by the speed adjusting module, and if the normal temperature is still in the high-temperature or low-temperature environment, the current reading and writing speed is kept unchanged.
The core control module is used for sensing temperature change and detecting and correcting errors.
The read-write control module is used for completing normal read-write control.
The speed adjusting module is used for completing the adjusting function of the reading and writing speed along with the temperature change.
The plurality of modules are matched with each other, the read-write speed of the Nand-flash is adjusted according to the change of the external temperature, and correct and efficient read-write is guaranteed.
In step 1, after a page is read/written, the core control module performs error detection on corresponding data.
In the step 3, the speed is correspondingly reduced by 0.5M/S according to the regulation rule of the speed regulation module when the temperature is increased or reduced by ten degrees.
In step 4, after the speed adjustment is completed, the read-write control module starts to read and write according to the adjusted speed, after one page of read and write is completed, the core control module detects whether a large-scale error still occurs again, and if the large-scale error occurs, the speed is continuously reduced by the error adjustment module.
Wherein the continuing to decrease by the fault adjustment module decreases at intervals of 0.5M/S.
In step 5, if the temperature is still at a high temperature or a low temperature, the reading and writing are continued at the adjusted current speed, and the core control module performs the re-detection of the temperature after reading/writing one block of data each time.
Example 1
As shown in fig. 1, the embodiment of the present embodiment is as follows:
(1) after starting, firstly, the read-write control module reads and writes the Nand-flash at a conventional speed;
(2) after reading/writing one page, the core control module detects the error of the corresponding data;
(3) if the error occurs, the current temperature is obtained by a temperature sensing device of the core control module;
(4) if the temperature does not change, the core control module adopts an error correction algorithm to correct the error of a single bit or a plurality of bits;
(5) if the temperature changes, the reading and writing speed is adjusted by the speed adjusting module, and the speed is correspondingly reduced by 0.5M/S according to the adjusting rule when the temperature is increased or reduced by ten degrees;
(6) after the speed adjustment is finished, the read-write control module starts to read and write according to the adjusted speed, after one page of read-write is finished, the core control module detects whether large-scale errors still occur again, if the large-scale errors occur, the speed is continuously reduced by the error adjustment module, and the speed is reduced at an interval of 0.5M/S;
(7) if no error exists, reading and writing are carried out according to the current speed, if only single bit or a plurality of bit errors occur, error correction is carried out by the core control module, and reading and writing are carried out according to the current speed;
(8) after a block of data is read/written, the core control module detects the current temperature;
(9) if the temperature is recovered, the speed adjusting module changes the reading and writing speed to the conventional speed again for reading and writing;
(10) if the temperature is still at high temperature or low temperature, reading and writing are continuously carried out according to the speed, and the core control module carries out temperature re-detection after reading/writing one block of data each time.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims (7)

1. A self-adaptive Nand Flash read-write speed adjusting system is characterized by comprising: the device comprises a core control module, a read-write control module and a speed adjusting module; the core control module is used for sensing temperature change and detecting and correcting errors; the read-write control module is used for completing read-write control; the speed adjusting module is used for completing the adjusting function of the reading and writing speed along with the temperature change;
in particular, the method of manufacturing a semiconductor device,
(1) firstly, a read-write control module controls to read and write the Nand-flash at a conventional speed, and if the core control module detects that an error occurs, the current temperature is obtained through a temperature sensing device of the core control module;
(2) if the temperature is unchanged, the core control module uses an error correction algorithm to correct data with a single bit or a plurality of bits;
(3) if the temperature is changed indeed, the speed adjusting module adjusts the corresponding read-write speed of the read-write control module, so that large-scale data errors are avoided;
(4) if the core control module still detects that a large-scale error occurs after the speed is adjusted, the speed adjusting module continuously reduces the reading and writing speed of the reading and writing control module;
(5) after a block of data is read/written, the core control module acquires the current temperature again to see whether the normal temperature is recovered, if the normal temperature is recovered, the speed adjusting module adjusts the read-write speed of the read-write control module to be the conventional speed, and if the normal temperature is still in the high-temperature or low-temperature environment, the current read-write speed is kept unchanged.
2. The adaptive Nand Flash read-write speed adjustment system as claimed in claim 1, wherein the modules cooperate with each other to adjust the Nand-Flash read-write speed according to the change of the external temperature, so as to ensure correct and efficient read-write.
3. The adaptive Nand Flash read-write speed adjustment system as claimed in claim 1, wherein the read-write control module controls to read and write the Nand-Flash at a regular speed, and if the core control module detects that an error occurs, the temperature sensing device of the core control module obtains the current temperature:
after reading/writing a page, the core control module performs error detection on corresponding data.
4. The adaptive Nand Flash read-write speed adjustment system as claimed in claim 1, wherein if the temperature does change, the speed adjustment module adjusts the corresponding read-write speed of the read-write control module by:
and the regulation rule of the speed regulation module correspondingly reduces the speed by 0.5M/S according to the temperature increase or decrease by ten degrees.
5. The adaptive Nand Flash read-write speed adjustment system as claimed in claim 1, wherein if the core control module still detects a large-scale error after the speed adjustment, the speed adjustment module continues to reduce the read-write speed of the read-write control module:
after the speed adjustment is finished, the read-write control module starts to read and write according to the adjusted speed, after one page of read-write is finished, the core control module detects whether large-scale errors still occur again, and if the large-scale errors occur, the speed is continuously reduced by the error adjusting module.
6. The adaptive Nand Flash read-write speed adjustment system of claim 5, wherein the continue to be slowed down by the error adjustment module is slowed down at 0.5M/S intervals.
7. The adaptive Nand Flash read-write speed adjustment system as claimed in claim 1, wherein if it is still in a high temperature or low temperature environment, then keeping the current read-write speed unchanged:
and if the temperature is still high or low, continuing to read and write at the adjusted current speed, and re-detecting the temperature by the core control module after reading/writing one block of data each time.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113867629A (en) * 2021-09-08 2021-12-31 长沙市致存科技有限责任公司 Data read-write method and system of memory, terminal device and storage medium
CN114880164A (en) * 2022-07-12 2022-08-09 合肥康芯威存储技术有限公司 Method and device for managing storage pages

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101067968A (en) * 2007-04-29 2007-11-07 北京中星微电子有限公司 Apparatus and method for adaptive controlling flash storage interface reading and writing speed
US20100023678A1 (en) * 2007-01-30 2010-01-28 Masahiro Nakanishi Nonvolatile memory device, nonvolatile memory system, and access device
CN101777013A (en) * 2009-01-12 2010-07-14 成都市华为赛门铁克科技有限公司 Solid state disk and data read-write method
CN102141943A (en) * 2010-01-28 2011-08-03 建兴电子科技股份有限公司 Flash memory device and data protection method thereof
CN108052414A (en) * 2017-12-28 2018-05-18 湖南国科微电子股份有限公司 A kind of method and system for promoting SSD operating temperature ranges
CN109446019A (en) * 2018-09-17 2019-03-08 至誉科技(武汉)有限公司 The method for carrying out chip power-consumption adjusting based on environment temperature

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100023678A1 (en) * 2007-01-30 2010-01-28 Masahiro Nakanishi Nonvolatile memory device, nonvolatile memory system, and access device
CN101067968A (en) * 2007-04-29 2007-11-07 北京中星微电子有限公司 Apparatus and method for adaptive controlling flash storage interface reading and writing speed
CN101777013A (en) * 2009-01-12 2010-07-14 成都市华为赛门铁克科技有限公司 Solid state disk and data read-write method
CN102141943A (en) * 2010-01-28 2011-08-03 建兴电子科技股份有限公司 Flash memory device and data protection method thereof
CN108052414A (en) * 2017-12-28 2018-05-18 湖南国科微电子股份有限公司 A kind of method and system for promoting SSD operating temperature ranges
CN109446019A (en) * 2018-09-17 2019-03-08 至誉科技(武汉)有限公司 The method for carrying out chip power-consumption adjusting based on environment temperature

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113867629A (en) * 2021-09-08 2021-12-31 长沙市致存科技有限责任公司 Data read-write method and system of memory, terminal device and storage medium
CN113867629B (en) * 2021-09-08 2024-02-09 长沙市致存科技有限责任公司 Data read-write method and system for memory, terminal equipment and storage medium
CN114880164A (en) * 2022-07-12 2022-08-09 合肥康芯威存储技术有限公司 Method and device for managing storage pages
CN114880164B (en) * 2022-07-12 2022-09-20 合肥康芯威存储技术有限公司 Method and device for managing storage pages

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