CN110752155A - Fin-shaped structure and preparation method of semiconductor device - Google Patents
Fin-shaped structure and preparation method of semiconductor device Download PDFInfo
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- CN110752155A CN110752155A CN201911032062.XA CN201911032062A CN110752155A CN 110752155 A CN110752155 A CN 110752155A CN 201911032062 A CN201911032062 A CN 201911032062A CN 110752155 A CN110752155 A CN 110752155A
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
Abstract
The invention discloses a preparation method of a fin-shaped structure, which comprises the following steps: providing a substrate, and forming a plurality of fins on the substrate; depositing shallow trench isolation between the fins; sequentially performing first flattening treatment and first corrosion treatment on the shallow slot isolation; performing second corrosion treatment on the plurality of fins; filling a material layer on the formed structure, and carrying out back etching treatment on the material layer; removing residues on the top of the shallow trench isolation with a high selectivity ratio, and removing the material layer in the second etching processing area; epitaxially growing a high-mobility material in the second etching treatment area to form a lead-in structure; and performing second flattening treatment on the lead-in structure; and carrying out third corrosion treatment on the shallow trench isolation to form a fin-shaped structure. The preparation method of the fin-shaped structure provided by the invention can not form corresponding 'particle defects' when a high-mobility material is epitaxially grown, and can not influence the efficiency and quality of epitaxial growth. The invention also provides a preparation method of the semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductor preparation, in particular to a fin-shaped structure and a preparation method of a semiconductor device.
Background
As the characteristic size of the device enters a 5 nanometer technology node, mobility degradation is caused by small-scale quantum effect, and strain engineering caused by continuous device scaling has saturation effect, so that the performance of the device is gradually degraded along with the scaling of the device size; SiGe or Ge high mobility materials have higher carrier mobility, and become a hotspot for research on novel three-dimensional devices.
However, in the STI first integration scheme, when bulk silicon is subjected to etching removal and other processes and an STI is formed, Si residue exists on the surface of the STI, so that when selective epitaxy is performed on SiGe or Ge high-mobility materials, a lot of 'grain defects' are formed on the surface of the STI after the epitaxy, and the 'grain defects' influence the subsequent processes; the existing method for removing the 'grain defects' is to weaken and even remove the 'grain defects' formed on the STI surface by increasing the content of HCl in the epitaxy process, but the efficiency and the quality of the epitaxy are affected.
Disclosure of Invention
The invention provides a fin-shaped structure and a preparation method of a semiconductor device, aiming at overcoming the technical problem that the efficiency and the quality of high-mobility material epitaxy are influenced while the particle defects formed on the surface of STI (shallow trench isolation) are weakened or even removed by the conventional method.
The preparation method of the fin-shaped structure comprises the following steps:
providing a substrate, and forming a plurality of fins on the substrate;
depositing shallow trench isolation between the fins; sequentially performing first planarization treatment and first corrosion treatment on the shallow trench isolation to expose the tops of the fins;
performing second corrosion treatment on the fins to remove the fins in the second corrosion treatment area;
filling a material layer on the formed structure, and carrying out back etching treatment on the material layer to expose residues on the top of the shallow trench isolation;
removing residues on the top of the shallow trench isolation with a high selectivity ratio, and removing the material layer in the second etching processing area;
epitaxially growing a high-mobility material in the second etching treatment area to form a lead-in structure; performing second planarization treatment on the lead-in structure to form an epitaxial structure;
and carrying out third etching treatment on the shallow trench isolation to expose the top of the epitaxial structure and form the fin-shaped structure.
Preferably, the substrate is a silicon substrate or an SOI substrate; the residue is silicon or silicon atoms.
Preferably, the shallow trench isolation is subjected to a first etching process using a DHF solution or a BOE (buffered oxide etchant) solution.
Preferably, TMAH (tetramethylammonium hydroxide) solution is adopted to remove a plurality of fins in the second etching treatment area; wherein the height of the second etching processing area is less than or equal to the height of the fin.
Preferably, the material layer is photoresist or amorphous carbon.
Preferably, the material layer is etched back by a dry etching process.
Preferably, HBr (hydrogen bromide) or HBr/Cl is used2(chlorine) based gas, high selectivity ratio to remove residue on top of shallow trench isolation; wherein, HBr/Cl2The volume ratio of the mixed gas of the base is as follows: 1:3 to 4: 1.
Preferably, O is used2(oxygen) or O2/N2(nitrogen) gas plasma removing the material layer in the second etch treatment region; wherein, O2/N2The volume ratio of the mixed gas is as follows: 1:10 to 10: 1.
Preferably, H is used2SO4/H2O2Removing the photoresist in the second etching treatment area by using a mixed solution (sulfuric acid/hydrogen peroxide); wherein H2SO4Solution and H2O2The volume ratio of the solution is: 2:1 to 1: 2.
Preferably, the high mobility material is Si1-xGexOr, Si1-yGeyWith Si1-zGezA laminate of (a); wherein x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 0.75, and z is more than or equal to 0.25 and less than or equal to 1.
Meanwhile, the invention also provides a preparation method of the semiconductor device, which is characterized by comprising the following steps:
preparing a plurality of fin-shaped structures along a first direction by adopting any one of the preparation methods of the fin-shaped structures;
forming a dummy gate on the fin-shaped structures along a second direction; forming side walls of the dummy gate on two sides of the dummy gate;
etching and growing a source-drain epitaxial layer on the fin-shaped structures on the two sides of the side wall to form a source/drain region;
depositing an oxidation dielectric layer on the formed structure, and carrying out third planarization treatment on the oxidation dielectric layer to expose the top of the dummy gate;
removing the false gate; and sequentially forming a gate dielectric layer and a gate in the gate region.
In summary, according to the method for manufacturing a fin-shaped structure provided by the present invention, after the second etching process is performed on the plurality of fins and before the high mobility material is epitaxially grown in the second etching process region, the material layer is filled and etched back on the formed structure, so that the residues of silicon or silicon atoms at the top of the shallow trench isolation are exposed, and the residues remaining at the top of the shallow trench isolation are completely removed in advance, so that after the formed material layer is completely removed, when the high mobility material is epitaxially grown in the second etching process region, the residues remaining at the top of the shallow trench isolation do not form corresponding "particle defects" together, and the subsequent high mobility material does not affect the efficiency and quality of the epitaxial growth.
Drawings
Fig. 1 is a flow chart of a method for fabricating a fin structure according to the present invention;
FIG. 2 is a schematic diagram of a structure after fin and shallow trench isolations are formed on a substrate and a first planarization process and a first etching process are performed;
FIG. 3 is a schematic diagram of the structure after a second etching process to remove a portion of the fins in the second etch process region;
FIG. 4 is a schematic structural view after a high mobility material is epitaxially grown using a conventional method;
figure 5 is a schematic diagram illustrating a structure after depositing a material layer by a method for fabricating a fin structure according to the present invention;
FIG. 6 is a schematic diagram of a fin structure after etching back by a method for fabricating the fin structure according to the present invention;
figure 7 is a schematic diagram of a fin structure having a high selectivity for removing residue from the top of the shallow trench isolation using a fin formation process according to the present invention;
FIG. 8 is a schematic diagram illustrating a fin structure after removing a remaining material layer in a second etching treatment region according to a method for fabricating the fin structure of the present invention;
FIG. 9 is a schematic diagram illustrating a fin structure after epitaxially growing a high mobility material using a method for fabricating a fin structure according to the present invention;
fig. 10 is a schematic structural diagram of a fin structure formed by the fin structure manufacturing method according to the present invention.
Wherein, 1 is a substrate, 2 is a fin, 3 is a shallow trench isolation, 4 is a material layer, 5 is a residue, 6 is an introduced structure, 7 is a fin structure, and 8 is a particle defect.
Detailed Description
The following describes an embodiment according to the present invention with reference to the drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As the characteristic size of the device enters a 5 nanometer technology node, mobility degradation is caused by small-scale quantum effect, and strain engineering caused by continuous device scaling has saturation effect, so that the performance of the device is gradually degraded along with the scaling of the device size; SiGe or Ge high mobility materials have higher carrier mobility, and become a hotspot for research on novel three-dimensional devices.
However, when the STI first integration scheme is adopted to perform Fin replacement of a high-mobility channel, specifically, as shown in fig. 3, when bulk silicon is subjected to etching removal and the like, and an STI is formed, Si residues exist on the STI surface, and the deeper the etching depth is, the more Si remains on the STI surface, so that when selective epitaxy is performed on SiGe or Ge high-mobility materials, a lot of "grain defects" are formed on the STI surface after epitaxy, and the specific structure is shown in fig. 4, and the "grain defects" can affect the subsequent processes; the existing method for removing the 'grain defects' is to weaken and even remove the 'grain defects' formed on the STI surface by increasing the content of HCl in the epitaxy process, but the processing mode can affect the efficiency and the quality of epitaxy.
In order to overcome the technical problem that the efficiency and the quality of the epitaxy of a high-mobility material are influenced when the particle defect formed on the surface of STI is weakened or even removed by the conventional method, the invention provides a preparation method of a fin-shaped structure; by adopting the method of removing residues such as silicon or silicon atoms and the like remained on the top of the shallow trench isolation in advance with high selection ratio, after the formed material layer is completely removed, when a high-mobility material is epitaxially grown in the second corrosion treatment area, corresponding 'particle defects' cannot be formed together due to the residues remained on the top of the shallow trench isolation, the follow-up effect cannot be generated, and the efficiency and the quality of epitaxial growth cannot be influenced.
Specifically, the method for manufacturing a fin structure according to the present invention, as shown in fig. 1, includes the following steps:
s11, providing a substrate 1, and forming a plurality of fins 2 on the substrate 1;
in this step, the substrate 1 is a silicon substrate or an SOI substrate; the substrate 1 may be anisotropically etched to form a plurality of fins 2 extending in the same direction; alternatively, the fin 2 is also formed on the substrate 1 in any one of the existing ways.
S12, depositing shallow trench isolation 3 among the plurality of fins 2; performing first planarization treatment and first corrosion treatment on the shallow trench isolation 3 to expose the tops of the plurality of fins 2, wherein the specific structure is shown in fig. 2;
in this step, several fins are formedAfter 2, depositing a shallow trench isolation 3 in the trench between the plurality of fins 2, wherein the material of the shallow trench isolation 3 may be SiN, Si3N4、SiO2Or SiCO, deposited to a thickness sufficient to bury the protruding fins 2; in order to facilitate subsequent operation, before the first corrosion treatment is carried out on the shallow trench isolation 3, the first planarization treatment is carried out on the shallow trench isolation 3 by adopting the processes of chemical mechanical polishing and the like, so that when the first corrosion treatment is carried out on the shallow trench isolation 3 subsequently, the corrosion depths corresponding to the shallow trench isolation 3 in all areas are the same, namely the heights of the tops of all exposed fins 2 are the same; specifically, the first etching treatment may be performed on the shallow trench isolation 3 by using a DHF solution or a BOE solution, and the height of the top of each exposed fin 2 may be set according to specific conditions.
S13, as shown in fig. 3, performing a second etching process on the plurality of fins 2 to remove the plurality of fins 2 in the second etching process area;
in this step, TMAH solution is used to perform a second etching process on the plurality of fins 2 to remove the fins 2 in the second etching process area; the height of the second etching area is less than or equal to the height of the fins 2, that is, in the second etching process of the plurality of fins 2 by using the TMAH solution, the fins 2 with the whole height may be removed, or the fins 2 with the partial height may be removed, and the height for specifically removing the fins 2 may be set according to specific conditions, which is not specifically limited herein.
S14, filling the material layer 4 on the formed structure, and performing etching back process on the material layer 4 to expose the residue 5 on the top of the shallow trench isolation 3, the formed structure is shown in fig. 6;
in this step, as shown in fig. 5, a material layer 4 is deposited on the formed structure, specifically, the material layer 4 may be photoresist or amorphous carbon, and the thickness of the material layer 4 should be higher than the top of the shallow trench isolation 3, so as to prevent the second etching processing region in the substrate 1 from being damaged when the residue 5 on the top of the shallow trench isolation 3 is subsequently removed, thereby causing the finally formed fin-shaped structure 7 not to meet the working requirement; after deposition, carrying out back etching treatment on the material layer 4 by adopting a dry etching process until residues 5 at the top of the shallow trench isolation 3 are exposed; wherein, in particular, the material layer 4 may be brought back with an F-based gasIn the etching process, preferably, the F-based gas may be CF4(carbon tetrafluoride) gas, SF6(sulfur hexafluoride) gas, or, volume ratio: 10:1 CF4/O2The mixed gas of (3); specifically, the residue 5 on top of the shallow trench isolation 3 includes: after the second etching treatment removes part or all of the fins 2 in the second etching treatment area, silicon remained on the top of the shallow trench isolation 3; and/or, the forming material is SiO2Silicon atoms remaining on the top of the shallow trench isolation 3.
S15, removing residues 5 on the top of the shallow trench isolation 3 with a high selectivity ratio, and removing the material layer 4 in the second etching processing area;
in this step, HBr gas or HBr/Cl at a volume ratio of 1:3 to 4:1 is used as shown in FIG. 72Removing residues 5 such as silicon and silicon atoms on the top of the shallow trench isolation 3 by using the mixed gas with high selectivity ratio so as to prevent the formation of 'particle defects 8' in the corresponding position of the residues 5 on the top of the shallow trench isolation 3 in an epitaxial manner during the epitaxial growth of the high-mobility material in the later period and influence the preparation of devices in the later period; meanwhile, the efficiency and the quality of the subsequent normal epitaxy high-mobility material cannot be influenced; as shown in fig. 8, after removing the residue 5 remaining on top of the shallow trench isolation 3, the material layer 4 in the second etching treatment region is removed to prepare for the subsequent epitaxy of the high mobility material in the second etching treatment region; specifically, O may be used2Or O2/N2The gas plasma completely removes the photoresist or amorphous carbon in the second etching treatment area; alternatively, if the material layer 4 is a photoresist, H can be used2SO4/H2O2The mixed solution completely removes the photoresist in the second etching treatment area; wherein, O2/N2The volume ratio of the mixed gas is as follows: 1:10 to 10: 1; h2SO4Solution and H2O2The volume ratio of the solution is: 2:1 to 1: 2.
S16, epitaxially growing a high-mobility material in the second etching area to form a lead-in structure 6; and performing second planarization treatment on the lead-in structure 6 to form an epitaxial structure, wherein the top of the epitaxial structure is flush with the top of the shallow trench isolation 3.
In this step, as shown in fig. 9, a high mobility material may be epitaxially grown in the second etching treatment region by using a process such as reduced pressure epitaxial growth; wherein the high mobility material is Si1-xGexOr, Si1-yGeyWith Si1-zGezA laminate of (a); wherein x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 0.75, and z is more than or equal to 0.25 and less than or equal to 1; specific Si1-yGeyWith Si1-zGezIn the stack of (2), Si1-yGeyWith Si1-zGezThe respective layer thicknesses are set as the case may be.
It should be noted that, in the process of extending the high mobility material, when the high mobility material is epitaxially grown in and out of the trench between the shallow trench isolations 3, because of the limitation of the shallow trench isolations 3 on both sides, the high mobility material will grow regularly in the trench, when the growth height of the high mobility material is higher than the depth of the trench, the high mobility material will continue to grow, at this time, there is no limitation on both sides, which may result in irregular growth shape, and for facilitating subsequent operations, processes such as chemical mechanical polishing are required to be adopted, and the high mobility material outside the formed trench is subjected to second planarization treatment according to the working requirements until the top of the shallow trench isolations 3; so as to form an epitaxial structure with high mobility and regular shape in the second etching treatment region.
And S17, performing a third etching treatment on the shallow trench isolation 3 to expose the top of the epitaxial structure and form a fin-shaped structure 7, wherein the specific structure is shown in FIG. 10.
In this step, DHF solution or BOE solution may be used to perform the third etching process on the shallow trench isolation 3 to expose the top of the epitaxial structure with high mobility, which is convenient for the later device fabrication.
Meanwhile, the invention also provides a preparation method of the semiconductor device, which is characterized by comprising the following steps:
s21, preparing and forming a plurality of fin structures 7 along a first direction by adopting the fin structure preparation method from the step S11 to the step S17;
s22, forming a dummy gate over the fin structures 7 along the second direction; forming side walls of the dummy gate on two sides of the dummy gate;
in this step, the second direction may be perpendicular to the first direction, and an included angle between the first direction and the second direction may also be set according to an actual working condition; specifically, a gate material of a dummy gate is deposited on the fin structures 7 along the second direction, wherein the gate material may be polysilicon; then, a wet etching process or a dry etching process can be adopted to etch the grid material to form a false grid; and then depositing a side wall material of the side wall, and etching the side wall material to form the side wall by adopting a wet etching or dry etching process.
S23, etching and growing a source-drain epitaxial layer on the fin-shaped structures 7 on the two sides of the side wall to form a source/drain region;
in the step, the fin-shaped structures 7 on two sides of the dummy gate are etched to form a depressed area; and then growing source and drain region materials in the recessed region of the fin-shaped structure 7 to form a source/drain region.
S24, depositing an oxide dielectric layer on the formed structure, and carrying out third planarization treatment on the oxide dielectric layer to expose the top of the dummy gate;
in this step, an oxide dielectric layer is deposited on the formed structure, wherein the oxide dielectric layer may be SiO2It is deposited to a thickness sufficient to embed the protruding dummy gate; and then, flattening the oxidation dielectric layer by adopting the processes of chemical mechanical polishing and the like so as to expose the top of the false gate.
S25, removing the false gate; and sequentially forming a gate dielectric layer and a gate in the gate region.
In this step, the dummy gate may be removed by a dry or wet etching process, and after the dummy gate is removed, a gate dielectric layer is deposited in the gate region, wherein preferably, the gate dielectric layer is a high-dielectric-constant layer, and specifically, the high-dielectric-constant layer may be HfO2(hafnium oxide) ZrO2(zirconium dioxide), TiO2(titanium dioxide) or Al2O3Depositing materials with high dielectric constant (such as aluminum oxide), and forming a gate on the gate dielectric layer, wherein the gate can be TaN (tantalum nitride),A lamination layer of any one or more substances such as TiN (titanium nitride), TiAlC (carbon aluminum titanium) and the like which meet the requirements; the thicknesses of the gate dielectric layer and the gate can be set according to specific conditions.
It should be noted that steps S22 to S25 may be implemented in various ways. How to implement steps S22 through S25 is not a main feature of the present invention, and thus in the present specification, it is only briefly described so that those skilled in the art can easily implement the present invention. It is fully contemplated by one of ordinary skill in the art that the above-described structures may be otherwise made.
A specific example of a method of fabricating a fin structure according to the present invention is given below:
etching the silicon substrate to form a plurality of fins 2 on the silicon substrate;
depositing a material of SiO between the fins 22The shallow trench isolation 3 is deposited to a height sufficient to bury the protruding fins 2; and adopting a chemical mechanical polishing process to carry out planarization treatment on the shallow trench isolation 3, and then adopting a BOE solution to carry out first corrosion treatment on the shallow trench isolation 3 so as to expose the tops of the plurality of fins 2.
Performing second corrosion treatment on the plurality of fins 2 by adopting a TMAH solution, and removing all the plurality of fins 2 in a second corrosion treatment area; after removal, a layer of photoresist is deposited on the formed structure, the thickness of the deposited photoresist is higher than the top of the protruding shallow trench isolation 3, and CF is adopted4The base gas etchback the photoresist to expose the residue 5 on top of the shallow trench isolation 3.
HBr-based gas high selectivity is used to remove residue 5 on top of shallow trench isolation 3 and O is used2The plasma completely removes the photoresist in the second etch processing region.
And epitaxially growing a high-mobility material of SiGe in the second etching processing region by adopting reduced pressure epitaxial growth to form a lead-in structure 6, and flattening the high-mobility material outside the groove between the shallow groove isolations 3 by adopting chemical mechanical polishing after the epitaxial growth to form an epitaxial structure.
And carrying out third corrosion treatment on the shallow trench isolation 3 by adopting BOE solution to expose the top of the epitaxial structure, thus forming the fin-shaped structure 7 with the characteristic of high mobility.
In summary, according to the method for manufacturing a fin-shaped structure provided by the present invention, after the second etching process is performed on the plurality of fins 2 and before the high mobility material is epitaxially grown in the second etching process region, the material layer 4 is filled and etched back on the formed structure to expose the residue 5 on the top of the shallow trench isolation 3, and the residue 5 remaining on the top of the shallow trench isolation 3 is removed in advance, so that after the formed material layer 4 is completely removed, when the high mobility material is epitaxially grown in the second etching process region, the residue 5 remaining on the top of the shallow trench isolation 3 does not form the corresponding "grain defect 8" together, and the efficiency and quality of epitaxial growth are not affected while the subsequent high mobility material is not affected.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (11)
1. A preparation method of a fin-shaped structure is characterized by comprising the following steps:
providing a substrate, and forming a plurality of fins on the substrate;
depositing shallow trench isolation between a plurality of the fins; sequentially performing first planarization treatment and first corrosion treatment on the shallow trench isolation to expose the tops of the fins;
performing second corrosion treatment on the fins to remove the fins in a second corrosion treatment area;
filling a material layer on the formed structure, and carrying out back etching treatment on the material layer to expose the residue on the top of the shallow trench isolation;
removing residues on the top of the shallow trench isolation with a high selectivity ratio, and removing the material layer in the second etching treatment area;
epitaxially growing a high-mobility material in the second etching treatment area to form a lead-in structure; performing second planarization treatment on the lead-in structure to form an epitaxial structure;
and carrying out third corrosion treatment on the shallow trench isolation to expose the top of the epitaxial structure and form a fin-shaped structure.
2. The method of manufacturing a fin-shaped structure according to claim 1, wherein the substrate is a silicon substrate or an SOI substrate; the residue is silicon or a silicon atom.
3. The method of manufacturing a fin structure according to claim 1, wherein the shallow trench isolation is subjected to a first etching treatment using a DHF solution or a BOE solution.
4. The method of claim 1, wherein TMAH solution is used to remove some of the fins in the second etching area; wherein the height of the second etching processing area is less than or equal to the height of the fin.
5. The method of claim 1, wherein the material layer is photoresist or amorphous carbon.
6. The method of claim 6, wherein the material layer is etched back by a dry etching process.
7. The method of claim 1, wherein HBr or HBr/Cl is used to form the fin structure2Removing residues on the top of the shallow trench isolation by using a base gas with a high selectivity ratio; wherein, the HBr/Cl2The volume ratio of the mixed gas of the base is as follows: 1:3 to 4: 1.
8. Preparation of the fin structure of claim 6Method, characterized in that O is used2Or O2/N2Gas plasma removing the material layer within the second etching treatment; wherein, said O is2/N2The volume ratio of the mixed gas is as follows: 1:10 to 10: 1.
9. The method of claim 6, wherein H is used2SO4/H2O2Removing the photoresist in the second etching treatment by using the mixed solution; wherein, the H2SO4Solution and H2O2The volume ratio of the solution is: 2:1 to 1: 2.
10. The method of fabricating the fin structure of claim 1, wherein the high mobility material is Si1-xGexOr, Si1-yGeyWith Si1-zGezA laminate of (a); wherein x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 0.75, and z is more than or equal to 0.25 and less than or equal to 1.
11. A method for manufacturing a semiconductor device, comprising the steps of:
preparing a plurality of fin structures along a first direction by using the method for preparing the fin structure as claimed in any one of claims 1 to 10;
forming a dummy gate over a number of the fin structures along a second direction; forming side walls of the dummy gate on two sides of the dummy gate;
etching and growing a source-drain epitaxial layer on the fin-shaped structures on the two sides of the side wall to form a source/drain region;
depositing an oxidation dielectric layer on the formed structure, and carrying out third planarization treatment on the oxidation dielectric layer to expose the top of the dummy gate;
removing the false gate; and sequentially forming a gate dielectric layer and a gate in the gate region.
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