CN110751964A - Multi-bit signal transmission method for integrated circuit storage - Google Patents
Multi-bit signal transmission method for integrated circuit storage Download PDFInfo
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- CN110751964A CN110751964A CN201810821376.7A CN201810821376A CN110751964A CN 110751964 A CN110751964 A CN 110751964A CN 201810821376 A CN201810821376 A CN 201810821376A CN 110751964 A CN110751964 A CN 110751964A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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Abstract
The invention provides a multi-bit signal transmission method of an integrated circuit memory. Because the combined storage unit of the integrated circuit memory has a plurality of storage sub-units (including the first storage sub-unit and the second storage sub-unit) which are mutually compensated, when the combined storage unit is read, the bit lines which are commonly connected can be charged by the plurality of storage sub-units, so that the level value of the bit lines can reach the required read level value, and the stored data can be successfully read from the combined storage unit. That is, the integrated circuit memory provided by the invention has the self-compensation function of the combined memory cell, can realize multi-bit signal transmission (for example, double-bit signal transmission), and is beneficial to ensuring the reading performance of the combined memory cell.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a multi-bit signal transmission method of an integrated circuit storage.
Background
In a conventional integrated circuit memory, such as a Dynamic Random Access Memory (DRAM), a memory cell usually stores data by using a storage capacitor. And, during operation of the integrated circuit memory (e.g., write operation and read operation), each memory cell independently performs a corresponding operation, e.g., during read operation of the memory, each memory cell independently reads out stored data from the corresponding storage capacitor.
However, in the development, design and manufacturing process of the memory, a defective memory cell inevitably exists, and since the related operations are performed independently and independently in each memory cell in the conventional memory, when the defective memory cell exists, the defective memory cell is difficult to be replaced, thereby causing the memory cell to fail to operate normally (for example, the stored data cannot be successfully read).
Disclosure of Invention
The present invention provides a multi-bit signal transmission method for an integrated circuit memory, so as to solve the problem that a single memory cell in the conventional integrated circuit memory cannot successfully read the stored data due to abnormal performance.
To solve the above technical problem, the present invention provides a multi-bit signal transmission method for an integrated circuit memory, comprising:
providing an integrated circuit memory, wherein the integrated circuit memory comprises at least one combined memory cell, each combined memory cell comprises a first memory sub-cell and a second memory sub-cell, the first memory sub-cell and the second memory sub-cell are connected to the same bit line, and the read level value of the bit line is set;
charging the bit line to a first level value, including sensing stored data in the first memory subcell of the combinational memory cell via the bit line for a first time period;
reading the stored data in the combined memory cell when the first level value reaches the read level value; and the number of the first and second groups,
when the first level value does not reach the read level value, continuing to charge the bit line to a second level value, including reading out the stored data of the second memory sub-cell in the combined memory cell via the bit line for a second time period, wherein the second time period is later than the first time period, to perform the transfer of the read signal of the integrated circuit memory.
Optionally, the method for transferring signals of multiple bits of the integrated circuit memory further includes: and simultaneously starting the first storage sub-unit and the second storage sub-unit in the combined storage unit, and writing storage data into the first storage sub-unit and the second storage sub-unit through the bit line so as to increase the level values in the first storage sub-unit and the second storage sub-unit to perform the transfer of the writing signal of the integrated circuit storage.
Optionally, the method for transferring signals of multiple bits of the integrated circuit memory further includes:
starting the first storage subunit in the combined storage unit, and writing storage data into the first storage subunit through the bit line so as to improve the level value of the first storage subunit; and the number of the first and second groups,
and starting the second storage subunit in the combined storage unit, and writing storage data into the second storage subunit through the bit line so as to enable the level value of the second storage subunit to be increased, wherein the write level value of the second storage subunit is greater than the write level value of the first storage subunit, so that the transfer of a write signal of the integrated circuit storage is executed.
Optionally, the integrated circuit memory further includes:
the first word lines and the second word lines extend along a first direction, the first memory sub-cells in the combined memory cells intersect with the first word lines, and the second memory sub-cells intersect with the second word lines, so that the first word lines and the second word lines are used for controlling the on states of the first memory sub-cells and the second memory sub-cells respectively.
Optionally, the first storage subunit includes a first storage capacitor, the first storage capacitor is connected to a drain region of a first storage transistor, the bit line is connected to a source region of the first storage transistor, and the first word line is connected to a gate of the first storage transistor;
and the second storage sub-unit comprises a second storage capacitor, the second storage capacitor is connected with a drain region of a second storage transistor, the bit line is connected with a source region of the second storage transistor, and the second word line is connected with a grid electrode of the second storage transistor.
Optionally, the method for transferring signals of multiple bits of the integrated circuit memory includes:
applying a word line voltage to the first word line to turn on the first storage transistor of the first storage sub-unit and write storage data into the first storage capacitor of the first storage sub-unit; and the number of the first and second groups,
and applying a word line voltage to the second word line to turn on the second storage transistor of the second storage sub-unit and write storage data into the second storage capacitor of the second storage sub-unit so as to transfer a write signal of the integrated circuit storage.
Optionally, in the process of performing the transfer of the read signal of the integrated circuit memory, the method includes:
applying a word line voltage to the first word line for a first period of time to turn on the first storage transistor of the first storage sub-unit and reading stored data from the first storage capacitor to the bit line to charge the bit line to a first level value; and the number of the first and second groups,
and when the first level value does not reach the reading level value, applying word line voltage to the second word line in a second time period to enable the second storage transistor of the second storage subunit to be turned on, and reading storage data from the second storage capacitor to the bit line so as to charge the bit line to a second level value.
Optionally, the time range from the start node to the end node in the first time period is 10ns to 20 ns; and the time range from the starting node to the ending node in the second time period is between 10ns and 20 ns.
Optionally, a time range from the end node of the first time period to the start node of the second time period is 1ns to 5 ns.
Optionally, the first storage sub-unit and the second storage sub-unit in the combined storage unit share the same bit line node, and are connected to the same bit line through the bit line node.
Optionally, the combined memory cell further includes an active region, the bit line node is disposed at a central position of the active region, and the first memory sub-cell and the second memory sub-cell in the combined memory cell are both formed on the active region and are symmetrically disposed with respect to the bit line node.
Optionally, the integrated circuit memory further includes a plurality of active regions, and the first memory sub-cell and the second memory sub-cell in the combined memory cell are respectively formed on adjacent active regions connected to the same bit line and in different rows.
Optionally, the first storage sub-unit has a first bit line node, the second storage sub-unit has a second bit line node, and the first storage sub-unit and the second storage sub-unit are respectively connected to the same bit line through the first bit line node and the second bit line node.
In the multi-bit signal transmission method of the integrated circuit memory, especially for the transmission of the read signal in the read operation, the bit line is charged by utilizing a plurality of mutually compensated memory sub-units in the combined memory unit (namely, the combined memory unit has the self-compensation function) so as to ensure that the level value of the bit line can reach the required read level value, and the stored data can be successfully read from the combined memory unit. That is, in the integrated circuit memory provided by the present invention, the whole combination of the plurality of memory sub-units is used as an operation unit, so that the combined memory unit has a self-compensation function, and can realize "double-bit signal transmission" or "multi-bit signal transmission" to improve the success rate of reading the stored data of the combined memory unit.
In addition, when the peripheral circuit of the integrated circuit memory provided by the invention is researched and designed, the influence and interference of the defects of each combined memory cell on the verification test of the peripheral circuit can be eliminated based on the structure of the combined memory cell and the multi-bit signal transmission mode of the combined memory cell, and the peripheral circuit can be verified and debugged more accurately.
Drawings
FIG. 1 is a timing diagram of a memory cell of an integrated circuit memory performing read signal propagation;
FIG. 2 is a diagram illustrating an integrated circuit memory according to a first embodiment of the present invention;
FIG. 3 is a timing diagram of the bit line nodes during signal propagation of the integrated circuit memory according to one embodiment of the present invention;
FIG. 4 is a timing diagram of a combined memory cell of the integrated circuit memory during a read operation according to one embodiment of the present invention;
FIG. 5 is a diagram illustrating an integrated circuit memory according to a second embodiment of the present invention.
Wherein the reference numbers are as follows:
100-combined memory cells;
110-a first storage subunit; 120-a second storage subunit;
130-an active region;
WL1 — first word line; WL2 — second word line;
NB-bit line node; BL-bit line;
NC1 — first storage capacitor; NC2 — second storage capacitor;
v1 — first level value; v2 — second level value;
VH1 — first high value; VH2 — second high value;
VL1 — first low value; VL2 — second low value;
T1/T3-start node; T2/T4-termination node.
Detailed Description
As described in the background, in the conventional memory, each memory cell performs related signal transmission (for example, transmission of a write signal and transmission of a read signal) independently. The memory cell can be controlled to be turned on or off by a word line, so that the stored data can be read out from the storage capacitor to a bit line, or the stored data can be stored in the storage capacitor from the bit line. The following explains a transfer process of a read signal performed by a memory cell of a memory.
FIG. 1 is a timing diagram of a memory cell of an integrated circuit memory during a read signal transfer. As shown in fig. 1, by applying a word line voltage to the word line WL corresponding to the selected memory cell to turn on the memory cell, the memory data in the memory capacitor NC is read to the bit line BL. That is, at this time, the storage capacitor NC discharges and charges the bit line BL, so that the level value of the bit line BL is increased. When the level value at the bit line BL can reach the required read level value (e.g., the second level value V2), then the reading of the stored data can be made successful.
However, as shown in fig. 1, since the memory cells of the memory may have defects, the bit line BL can only reach the first level value V1 and cannot reach the required read level value (e.g., the second level value V2) during the reading process, thereby causing the data reading failure. At this time, since the respective memory cells are independently performing the transfer of the correlation signal, they cannot be compensated when the memory cells fail.
To this end, the invention provides a multi-bit signal transmission method of an integrated circuit memory. In particular, for the transfer of the read signal of the combined memory cell, since the combined memory cell has a plurality of memory sub-cells which compensate each other, the bit line commonly connected to the combined memory cell can be charged by a part of the memory sub-cells or all the memory sub-cells, so as to ensure that the level value of the bit line reaches the required read level value. That is, the combined memory cell of the present invention has a self-compensation function, and can realize multi-bit signal transmission (e.g., dual-bit signal transmission), which is beneficial to ensuring the reading performance of the combined memory cell.
The multi-bit signal transmission method of the integrated circuit memory proposed by the present invention is further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
In this embodiment, the method for transferring signals of multiple bits of an integrated circuit memory includes: an integrated circuit memory is provided.
Fig. 2 is a schematic structural diagram of an integrated circuit memory according to a first embodiment of the present invention, and as shown in fig. 2, the integrated circuit memory includes at least one combinational memory cell 100, the combinational memory cell 100 includes a plurality of memory sub-cells, and the plurality of memory sub-cells are connected to the same bit line. In this embodiment, the combined memory cell 100 includes a first memory sub-cell 110 and a second memory sub-cell 120, and the first memory sub-cell 110 and the second memory sub-cell 120 share a bit line node NB and are connected to the same bit line BL through the bit line node NB.
The multi-bit signal transmission method of the integrated circuit storage further comprises the following steps: a write operation is performed on the combined memory cell 100 to effect the transfer of a write signal. Specifically, the transferring process of the write signal includes: meanwhile, each of the memory sub-cells in the combinational memory cell 100 is turned on, and the storage data is written into each of the memory sub-cells of the combinational memory cell 100 through the bit line BL and further via the bit line node NB, so that the level value of each memory sub-cell reaches a predetermined level value, thereby performing the transfer of the write signal to the combinational memory cell 100.
That is, during the writing process of the combined memory cell 100, the plurality of memory sub-cells may all be turned on, so that the plurality of memory sub-cells have the memory data written therein, and the written memory data are all the same. For example, a plurality of memory sub-units each perform a write "0" process, or a plurality of memory sub-units each perform a write "1" process. In this way, when a failure occurs in one of the memory sub-units and the level value of the bit line BL cannot be raised to the read level value during the read operation, the other memory sub-units storing the same memory data can be used for compensation, thereby ensuring the accuracy of reading the memory data.
In this embodiment, when performing a write operation, the first memory sub-unit 110 and the second memory sub-unit 120 of the combined memory cell 100 are simultaneously turned on, and the stored data is written into the first memory sub-unit 110 and the second memory sub-unit 120 through the bit line BL, so that the level values in the first memory sub-unit 110 and the second memory sub-unit 120 reach the second level value, for example.
In addition, the method of performing the write operation on the combined memory cell may also be to perform the write operation on different memory sub-cells at different time periods. For example, performing a write operation on the combined memory cell to implement the passing of the write signal includes:
firstly, the first memory sub-unit 110 in the combined memory cell 100 is turned on, and the stored data is written into the first memory sub-unit 110 through the bit line BL and further through the bit line node BL, so that the level value of the first memory sub-unit 110 is increased;
then, the second memory sub-unit 120 in the combinational memory cell 100 is turned on, and the stored data is written into the second memory sub-unit 120 through the bit line BL and further through the bit line node BL, so that the level value of the second memory sub-unit 120 is increased, and the write level value of the second memory sub-unit is greater than the write level value of the first memory sub-unit, so as to perform the transfer of the write signal to the combinational memory cell.
At this time, the level value corresponding to the data stored in the first storage subunit 110 is lower than the level value corresponding to the data stored in the second storage subunit 120. Therefore, when the level value of the data stored in the first memory sub-unit 110 cannot satisfy the read level value in the subsequent read operation, the charging process can be continued by using the data stored in the second memory sub-unit 120 with a higher level value, so as to complete the transmission of the read signal of the combined memory cell 100.
Namely, the multi-bit signal transfer method of the integrated circuit memory further comprises: a read operation is performed on the combined memory cell 100 to complete the transfer of the read signal. Specifically, the method for transferring the read signal of the combined memory cell 100 includes:
charging the bit line BL to a first level value, including reading out the stored data in one of the memory sub-cells of the combined memory cell 100 via the bit line for a first period of time (in this embodiment, the bit line node BN accordingly has the first level value);
determining whether the first level value of the bit line BL reaches a read level value (in this embodiment, it is equivalent to determining whether the first level value of the shared bit line node BN reaches a read level value); and the number of the first and second groups,
when the first level value reaches the reading level value, successfully reading the storage data in the combined storage unit;
when the first level value does not reach the read level value, the bit line BL is continuously charged to a second level value, which includes reading the storage data of another storage sub-unit in the combinational memory cell 100 via the bit line in a second time period (in this embodiment, the storage data are all read to the shared bit line node NB, and the corresponding pair of bit line nodes NB are continuously charged to the second level value). It should be appreciated that the second time period is later than the first time period.
It is considered that the combinational memory cell 100 may integrally form a unit capable of independently performing the transmission of the related signals, and the plurality of memory sub-cells may form a compensation circuit to compensate the level value at the bit line node, so as to ensure that the level value of the bit line BL (i.e., the bit line node NB) can reach the required read level value during the reading process of the combinational memory cell 100, so that the combinational memory cell 100 of the memory can smoothly complete the reading process of the stored data.
FIG. 3 is a timing diagram of the bit line nodes during signal transmission of the integrated circuit memory according to the first embodiment of the present invention. A method for performing a read operation on the combined memory cell 100 to perform a read signal transfer in the present embodiment is explained below with reference to fig. 3.
First, in a first period, the storage data in the first memory sub-unit 110 of the combination memory cell 100 is read out to the bit line node NB to charge the bit line node NB to a first level value. For example, when a read "1" operation is performed on the combinational memory cell 100, the bit line node NB may be charged to the first high level value VH 1; alternatively, when a read "0" operation is performed on the combined memory cell 100, the bit line node NB may be charged to the first low level value VL 1.
Next, it is determined whether the first level value of the bit line node NB reaches a read level value. If the first level value reaches the read level value, the stored data in the combinational memory cell 100 is successfully read. In this embodiment, the first level value of the bit line node NB does not reach the read level value, and thus the following steps are continuously performed.
Next, in a second time period, the storage data of the second storage sub-unit 120 in the combined storage unit 100 is read out to the bit line node NB to continue charging the bit line node NB so that the level value at the bit line node NB reaches a second level value (i.e., a required read level value). When the combined memory cell 100 performs a read "1" operation, the bit line node NB is continuously charged to the second high level value VH 2; alternatively, when the combinational memory cell 100 performs a read "0" operation, the bit line node NB may be charged to the second low level value VL 2.
It is understood that, in this embodiment, in one reading operation of the combined memory cell 100, the bit line node NB is charged (for example, twice charged) for a plurality of times respectively, so that the level value (absolute value of the level value) of the bit line node NB is increased in stages, and thus, this reading mode may be referred to as multi-bit signaling (for example, double-bit signaling).
Further, the integrated circuit memory further includes a plurality of active regions 130, and the first memory sub-cell 110 and the second memory sub-cell 120 of the combined memory cell 100 are formed on the same active region 130. Further, a bit line node NB common to the first memory sub-unit 110 and the second memory sub-unit 120 is disposed on the active region 130. The bit line node NB is preferably disposed at a center position of the active region 130, such that the first memory sub-cell 110 and the second memory sub-cell 120 of the combined memory cell are symmetrically disposed with respect to the bit line node NB.
In this embodiment, the active region 130 of the combined memory cell 100 extends along a third direction (Z direction), and the first memory sub-cell 110 and the second memory sub-cell 120 are sequentially formed on the active region 130 along the extending direction of the active region 130, respectively.
With continued reference to fig. 2, the integrated circuit memory further includes a plurality of first word lines WL1 and a plurality of second word lines WL2, the first word lines WL1 and the second word lines WL2 each extending along a first direction (Y-direction). And the first memory sub-cell 110 in the combined memory cell 100 intersects the first word line WL1 and the second memory sub-cell 120 intersects the second word line WL2 to control the on-states of the first memory sub-cell 110 and the second memory sub-cell 120 with the first word line WL1 and the second word line WL2, respectively. Specifically, when a word line voltage is applied to a predetermined word line, the memory sub-cells connected to the predetermined word line are turned on, thereby implementing writing or reading of stored data.
Further, the first storage sub-unit 110 includes a first storage capacitor NC1, the first storage capacitor NC1 is connected to a drain region of a first storage transistor, the bit line BL is connected to a source region of the first storage transistor, and the first word line WL1 is connected to a gate of the first storage transistor. And the second storage sub-unit 120 comprises a second storage capacitor NC2, the second storage capacitor NC2 is connected with a drain region of a second storage transistor, the bit line BL is connected with a source region of the second storage transistor, and the second word line WL2 is connected with a gate of the second storage transistor. The first storage capacitor NC1 and the second storage capacitor NC2 are both used for storing data information, and the first word line WL1 and the second word line WL2 are respectively used for controlling the first storage transistor and the second storage transistor to be turned on and off so as to enable current to flow between a source region and a drain region of each of the first storage transistor and the second storage transistor, so that stored data stored in the first storage capacitor NC1 and the second storage capacitor NC2 can be read out, or stored data can be stored from the bit line node NB1 and the second storage capacitor NC 2.
Further, the first memory transistor of the first memory sub-cell 110 and the second memory transistor of the second memory sub-cell 120 share a source region, and the bit line node NB in common is formed on the shared source region.
When a write operation is performed on the combined memory cell 100 to perform the transfer of a write signal to the combined memory cell, a word line voltage is applied to each of the first word line WL1 and the second word line WL2 connected correspondingly in the same combined memory cell 100, so that the memory transistors of the plurality of memory sub-cells in the combined memory cell 100 are all turned on.
In this embodiment, the method for performing a write operation includes: applying a word line voltage to the first word line WL1 to turn on the first storage transistor of the first storage sub-unit 110 and write storage data into the first storage capacitor NC1 of the first storage sub-unit 110; and applying a word line voltage to the second word line WL2 to turn on the second storage transistor of the second storage sub-unit 120 and write storage data into the second storage capacitor NC2 of the second storage sub-unit 120.
As described above, the word line voltage may be simultaneously applied to the first word line WL1 and the second word line WL2 in the same time period to simultaneously turn on the first storage transistor and the second storage transistor, so that the stored data is simultaneously written to the first storage capacitor NC1 and the second storage capacitor NC2 by the bit line node NB; of course, it is also possible to sequentially apply the word line voltages to the first word line WL1 and the second word line WL2, respectively, at different time periods, so that the storage data corresponding to different level values can be written to the first storage capacitor NC1 and the second storage capacitor NC2, respectively.
FIG. 4 is a timing diagram of the reading of the combined memory cells of the integrated circuit memory according to the first embodiment of the present invention. The reading process of the combined memory cell 100 in the present embodiment will be described in detail below with reference to fig. 4.
Step one, in a first time period (T1-T2), a word line voltage is applied to the first word line WL1 to turn on the first storage transistor of the first storage subunit 110, and stored data is read from the first storage capacitor NC1 to the bit line node NB (correspondingly, to the bit line BL), so as to charge the bit line node NB to a first level value V1. At this time, the first storage capacitor NC1 performs a discharging process to lower its level value, and the level value of the bit line node NB is raised to have the first level value V1.
Further, in the first period, a time ranging from a start node T1 at which the word line voltage starts to be applied to the first word line WL1 to a termination node T2 at which the word line voltage ends to be applied to the first word line WL1 is, for example, 10ns to 20 ns.
Step two, judging whether the first level value V1 reaches a reading level value; in this embodiment, since the first level value V1 still does not reach the read level value, the following steps are still required to be performed.
Step three, in a second time period (T3-T4), a word line voltage is applied to the second word line WL2 to turn on the second storage transistor of the second storage subunit 120, and the storage data is read from the second storage capacitor NC2 to the bit line node NB (correspondingly, to the bit line BL), so as to continuously charge the bit line node NB to the second level value. At this time, the second storage capacitor NC2 performs a discharging process to lower the level value thereof, and the level value of the bit line node NB is continuously raised from the first level value V1 and may reach the second level value V2 (equal to the read level value), at which time the level value at the bit line node NB may reach the read level value.
Further, in the second period, a time ranging from a start node T3 at which the word line voltage starts to be applied to the second word line WL2 to a termination node T4 at which the word line voltage ends to be applied to the second word line WL2 is between 10ns and 20 ns.
In addition, the time range from the termination node T2 of the first period to the start node T3 of the second period is, for example, 1ns to 5 ns. In this way, the turn-on phases of the first memory sub-unit 110 and the second memory sub-unit 120 are staggered from each other, so as to avoid mutual influence in different read phases.
It can be seen that even if either or both of the first and second memory sub-units 110 and 120 are defective, the first and second memory sub-units 110 and 120 can compensate for each other, and therefore, successful reading of the memory data from the combined memory cell 100 can still be ensured.
With continued reference to fig. 2, the integrated circuit memory includes a plurality of combinational memory cells 100, wherein the combinational memory cells 100 are arranged in an array. The bit line nodes NB corresponding to the plurality of combination memory cells 100 are aligned in the second direction (X direction).
Further, the integrated circuit memory has a plurality of bit lines BL extending along a second direction (X direction) and connected to the bit line nodes NB of the combined memory cells 100 for transferring the memory data, wherein the plurality of bit line nodes NB aligned in the same line in the second direction are connected to the same bit line BL. It is to be understood that, during the writing process, the storage data is transmitted to the bit line node NB through the bit line BL to further write the storage data through the bit line node NB; and, during reading, the memory data is read out from the bit line node NB and transferred to the bit line BL to transfer the memory data through the bit line BL.
It should be noted that the extending of the bit line BL along the second direction includes: the bit lines BL extend straight along the second direction, or the bit lines BL extend in a wave shape along the second direction. The extending manner of the bit lines BL may be specifically set according to the structure of the combinational memory 100 and the arrangement manner of the combinational memory cells 100.
In this embodiment, the active region 130 of the combined memory cell 100 extends along the third direction (Z direction), the bit line node NB is disposed at the center of the active region 130, the first memory sub-cell 110 and the second memory sub-cell 120 are sequentially arranged along the extending direction of the active region 130, and the first storage capacitor NC1 of the first memory sub-cell 110 and the second storage capacitor NC2 of the second memory sub-cell 120 are respectively formed at both ends of the active region 130 in the extending direction thereof and are symmetrical with respect to the bit line node NB. Wherein the first direction (Y direction) is perpendicular to the second direction (X direction), and the third direction (Z direction) is inclined with respect to the first direction (Y direction).
With continued reference to fig. 2, the plurality of combined memory cells 100 are arranged in a plurality of columns, the plurality of combined memory cells 100 in each column are aligned along the first direction (Y direction), and the plurality of columns of combined memory cells 100 are sequentially arranged along the second direction (X direction). Therefore, in this embodiment, the bit line BL may extend in a wave shape in the second direction to connect the plurality of bit line nodes NB arranged in the same line in the second direction, and avoid an influence on the first storage capacitor NC1 and the second storage capacitor NC 2.
Of course, in other embodiments, the plurality of combinational memory cells 100 may also be alternately arranged in the first direction (Y direction), and the plurality of bit line nodes NB arranged in alignment in the second direction (X direction) may not have corresponding storage capacitors in the linear direction, and at this time, the bit lines may extend linearly in the second direction.
Example two
The difference from the first embodiment is that the plurality of memory sub-cells of the combined memory cell in the present embodiment are respectively formed in different active regions.
FIG. 5 is a diagram illustrating an integrated circuit memory according to a second embodiment of the present invention. As shown in fig. 5, the integrated circuit memory includes a plurality of active regions 130, and a plurality of memory sub-cells of the combined memory cell 100 are respectively formed on different active regions 130. In the present embodiment, the first memory sub-unit 110 and the second memory sub-unit 120 of the combined memory cell 100 are respectively formed in two adjacent active regions 130. And, the active region 130 corresponding to the first memory sub-cell and the active region 130 corresponding to the second memory sub-cell both intersect the same bit line BL, so that the first memory sub-cell 110 and the second memory sub-cell 120 are both connected to the same bit line BL.
Further, the first storage sub-unit 110 has a first bit line node NB1, the second storage sub-unit 120 has a second bit line node NB2, and the first storage sub-unit 110 and the second storage sub-unit 120 are respectively connected to the same bit line BL through the first bit line node NB1 and the second bit line node NB 2. The first bit line node NB1 and the second bit line node NB2 are respectively formed on different active regions 130, that is, in the embodiment, the first storage sub-unit 110 and the second storage sub-unit 120 do not share a bit line node.
In addition, in the present embodiment, two memory sub-cells may be formed in the same active region 130, and bit line nodes of the two memory sub-cells in the same active region 130 are shared, and the two memory sub-cells may be symmetrically disposed with respect to the shared bit line node. However, two memory sub-cells in the same active region 130 are used to form two different combined memory cells 100, respectively.
With continued reference to fig. 5, in the present embodiment, the first word line WL1 and the second word line WL2 intersect the first memory sub-cell 110 and the second memory sub-cell 120, respectively, and accordingly the first word line WL1 and the second word line WL2 intersect the two different active regions 130, respectively.
Similar to the embodiment shown in fig. 4 and 5, the method for performing a read operation on the combined memory cell 100 to perform passing of a read signal of the combined memory cell includes:
applying a word line voltage to the first word line WL1 to turn on the first memory sub-unit 110 and read out the stored data in the first memory sub-unit 110 from the first storage voltage NC1 to the first bit line node NB1 and further conduct to the bit line BL to charge the bit line BL to a first level value for a first period of time (T1-T2);
determining whether the first level value of the bit line reaches a read level value; and the number of the first and second groups,
reading the stored data in the combined memory cell when the first level value reaches the read level value; and the number of the first and second groups,
when the first level value does not reach the read level value, a word line voltage is applied to the second word line WL2 to turn on the second memory sub-unit 120 and read out the stored data in the second memory sub-unit 120 from the second storage voltage NC2 to the second bit line node NB2 and further conducted to the bit line BL to continue charging the bit line BL to the second level value for a second time period (T3-T4).
In addition, it should be noted that, in the integrated circuit memory provided in this embodiment, the combined storage unit includes a plurality of storage sub-units that compensate each other, and during the process of performing the read operation, some or all of the storage sub-units sequentially charge the bit lines, so as to ensure that the stored data can be successfully read out. It should be appreciated that the combined memory cell in the present embodiment constitutes an independent unit as a whole, and a plurality of storage capacitors and a plurality of storage transistors are disposed in one combined memory cell, so that the combined memory cell has a self-compensation function, and can realize "multi-bit signal transmission", which has a larger difference in structure, operation mode, and signal transmission mode compared with a conventional memory in which only one storage capacitor and one storage transistor are disposed in one memory cell.
In summary, in the multi-bit transferring method of the integrated circuit memory provided by the present invention, specifically for the reading operation of the combined memory cell, the bit lines of the memory sub-cells are charged together by using the mutually compensated memory sub-cells, so as to ensure that the stored data in the combined memory cell can be successfully read.
In addition, as the semiconductor technology is developed, the size of the semiconductor device is also continuously reduced, and therefore, the development and design of the semiconductor device correspondingly take longer time and more effort to debug to improve the yield of the product. Particularly, in the initial stage of development, the semiconductor device has not yet reached the design requirements, and it is difficult to identify specific process defects, so that the design of the peripheral circuit of the semiconductor device cannot be effectively adjusted.
In particular, when peripheral circuits in integrated circuit memories are developed and designed, the effects and disturbances caused by defects of memory cells need to be shielded. For example, in verifying the performance of peripheral circuits during a read operation, it is necessary to ensure that stored data can be successfully read from the memory cells. The integrated circuit memory provided by the invention has the advantages that the combined storage unit has the self-compensation function and can realize the transmission of the double-bit signals, so that the stored data can be effectively ensured to be successfully read from the storage unit, the debugging of the peripheral circuit of the integrated circuit memory is facilitated, and the improvement of the yield of products is facilitated.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (14)
1. A method for multi-bit signaling in an integrated circuit memory, comprising:
providing an integrated circuit memory, wherein the integrated circuit memory comprises at least one combined memory cell, each combined memory cell comprises a first memory sub-cell and a second memory sub-cell, the first memory sub-cell and the second memory sub-cell are connected to the same bit line, and the read level value of the bit line is set;
charging the bit line to a first level value, including sensing stored data in the first memory subcell of the combinational memory cell via the bit line for a first time period;
reading the stored data in the combined memory cell when the first level value reaches the read level value; and the number of the first and second groups,
when the first level value does not reach the read level value, continuing to charge the bit line to a second level value, including reading out the stored data of the second memory sub-cell in the combinational memory cell via the bit line for a second time period, wherein the second time period is later than the first time period, to perform the transfer of the read signal of the combinational memory cell.
2. The method of multi-bit signaling in an integrated circuit memory of claim 1, further comprising: and simultaneously starting the first storage sub-unit and the second storage sub-unit in the combined storage unit, writing storage data into the first storage sub-unit and the second storage sub-unit through the bit line, and increasing the level values in the first storage sub-unit and the second storage sub-unit so as to transmit a writing signal to the combined storage unit.
3. The method of multi-bit signaling in an integrated circuit memory of claim 1, further comprising:
starting the first storage subunit in the combined storage unit, and writing storage data into the first storage subunit through the bit line so as to improve the level value of the first storage subunit; and the number of the first and second groups,
and starting the second storage subunit in the combined storage unit, and writing storage data into the second storage subunit through the bit line so as to enable the level value of the second storage subunit to be increased, wherein the write level value of the second storage subunit is greater than the write level value of the first storage subunit, so that the transfer of a write signal is performed on the combined storage unit.
4. The method of multi-bit signaling in an integrated circuit memory of claim 1, wherein said integrated circuit memory further comprises:
the first word lines and the second word lines extend along a first direction, the first memory sub-cells in the combined memory cells intersect with the first word lines, and the second memory sub-cells intersect with the second word lines, so that the first word lines and the second word lines are used for controlling the on states of the first memory sub-cells and the second memory sub-cells respectively.
5. The method of claim 4, wherein said first memory sub-cell comprises a first storage capacitor, said first storage capacitor is connected to a drain region of a first memory transistor, said bit line is connected to a source region of said first memory transistor, and said first word line is connected to a gate of said first memory transistor;
and the second storage sub-unit comprises a second storage capacitor, the second storage capacitor is connected with a drain region of a second storage transistor, the bit line is connected with a source region of the second storage transistor, and the second word line is connected with a grid electrode of the second storage transistor.
6. The method of multi-bit signaling in an integrated circuit memory of claim 5, further comprising:
applying a word line voltage to the first word line to turn on the first storage transistor of the first storage sub-unit and write storage data into the first storage capacitor of the first storage sub-unit; and the number of the first and second groups,
and applying a word line voltage to the second word line to turn on the second storage transistor of the second storage sub-unit, and writing storage data into the second storage capacitor of the second storage sub-unit to perform transfer of a write signal to the combined storage unit.
7. The method of multi-bit signaling in an integrated circuit memory of claim 5, wherein in performing the transferring of the read signals for the combined memory cells, further comprising:
applying a word line voltage to the first word line to turn on the first storage transistor of the first storage sub-unit and read storage data from the first storage capacitor to the bit line to charge the bit line to the first level value during the first period; and the number of the first and second groups,
and when the first level value does not reach the reading level value, applying word line voltage to the second word line in the second time period to enable the second storage transistor of the second storage subunit to be turned on, and reading storage data from the second storage capacitor to the bit line so as to continuously charge the bit line to the second level value.
8. The method of claim 7 wherein the time period from the start node to the end node in said first time period ranges from: 10 ns-20 ns; and the time range from the starting node to the ending node in the second time period is between 10ns and 20 ns.
9. The method of claim 7 wherein the time between the end node of the first time period to the start node of the second time period ranges from 1ns to 5 ns.
10. The method of multi-bit signaling in an integrated circuit memory according to any of claims 1-9, wherein said integrated circuit memory further comprises a plurality of active regions, said first memory sub-cell and said second memory sub-cell of said combined memory cell being formed on the same said active region.
11. The method of claim 10, wherein said first memory sub-cell and said second memory sub-cell of said combined memory cell share a same bitline node and are connected to a same bitline through said bitline node.
12. The method of multi-bit signaling in an integrated circuit memory of claim 11 wherein said bit line node is disposed at a central location in said active region, said first and second ones of said combined memory cells being symmetrically disposed with respect to said bit line node.
13. The method of any of claims 1-9, wherein the integrated circuit memory further comprises a plurality of active regions, and the first memory sub-cell and the second memory sub-cell of the combined memory cell are respectively formed on adjacent active regions connected to a same bit line and on different ranks.
14. The method of claim 13, wherein said first memory sub-cell has a first bitline node and said second memory sub-cell has a second bitline node, said first memory sub-cell and said second memory sub-cell being connected to the same bitline through said first bitline node and said second bitline node, respectively.
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