CN110740104A

CN110740104A - switch system startup management method and device

Info

Publication number: CN110740104A
Application number: CN201910970099.0A
Authority: CN
Inventors: 季冬冬; 薛广营; 张广乐
Original assignee: Suzhou Wave Intelligent Technology Co Ltd
Current assignee: Suzhou Wave Intelligent Technology Co Ltd
Priority date: 2019-10-12
Filing date: 2019-10-12
Publication date: 2020-01-31

Abstract

The invention relates to a method and a device for starting management of switch systems, wherein the method comprises the steps of accessing a power supply to enable the switch system to enter an external trigger starting state, executing service initialization by a BMC and sending an initialization completion signal after the initialization is completed, responding to the fact that a CPLD/FPGA receives the initialization completion signal sent by the BMC, sending a simulated starting signal to the switch system by the CPLD/FPGA, carrying out power-on preparation on the switch system based on the simulated starting signal and feeding back the standby signal to the CPLD/FPGA, responding to the fact that the CPLD/FPGA receives the standby signal, and controlling a power supply to power on all parts of the switch system one by one .

Description

switch system startup management method and device

Technical Field

The invention relates to the technical field of switches, in particular to a method and a device for power-on management of switch systems, which are further .

Background

In the switch system, the CPLD/FPGA chip is usually used for controlling the power-on and power-off sequence control, communication control, key detection, fan speed control, SFP lighting control and serial port switching, double BIOS switching, I2C multi-master and multi-slave communication and the like of the whole switch, the CPLD/FPGA is a semi-customized special integrated circuit, has the series advantages of flexible programming, quick response, high integration level and the like, and is increasingly applied to the field of development, verification and control application of at the early stage.

In order to solve the problem, generally selects a mode of setting default initial values in the system, such as initial rotating speed or full-speed running of a given fan, and the like.

Therefore, there is a need to provide optimized switch system boot management methods to effectively perform time-sequenced boot control on the switch system, especially the switch system with the added BMC.

Disclosure of Invention

, the present invention provides a method for power-on management of switch systems based on the above objects, wherein the method comprises the following steps:

accessing a power supply to enable the switch system to enter an external trigger starting state, executing service initialization by the BMC and sending an initialization completion signal after the initialization is completed;

responding to the CPLD/FPGA receiving an initialization completion signal sent by the BMC, and sending a simulated starting signal to the switch system by the CPLD/FPGA;

the switch system performs power-on standby preparation based on the simulated starting signal and feeds back the standby signal to the CPLD/FPGA;

and in response to the CPLD/FPGA receiving the standby signal, the CPLD/FPGA controls a power supply set to power on all parts of the switch system one by one .

An embodiment of a method for switch system power-on management according to the invention, wherein the method further comprises:

and in response to the CPLD/FPGA not receiving the initialization completion signal sent by the BMC after the preset time, the CPLD/FPGA controls the BMC fault indicator lamp to light up and sends a simulated starting signal to the switch system.

In an embodiment of the method for power-on management of a switch system according to the present invention, wherein the accessing the power source to make the switch system enter an external triggered power-on state, the performing, by the BMC, the service initialization and sending an initialization completion signal after completion further includes:

the system STBY power supply supplies power to the BMC to carry out service initialization;

the switch system enters an external trigger power-on state through the BIOS.

According to the embodiment of the switch system boot management method, the CPLD/FPGA is configured to be connected with the BMC through the GPIO interface, and the GPIO interface is configured to access a high-level signal by default,

responding to the CPLD/FPGA receiving the initialization completion signal sent by the BMC, the CPLD/FPGA sending the simulated starting signal to the switch system further steps including:

and responding to the BMC to complete the service initialization, and sending an initialization completion signal with low level to the GPIO interface.

According to an embodiment of the method for power-on management of the switch system, the CPLD/FPGA controlling the power pack to power on the components of the switch system by steps in response to the CPLD/FPGA receiving the standby signal step includes:

the CPLD/FPGA sends a power supply enabling signal to the power supply pack;

the power supply set powers on corresponding components according to the power supply enabling signal and feeds back a power supply indicating signal to the CPLD/FPGA;

and responding to the CPLD/FPGA to receive the power supply indication signal, and executing the steps again until all parts of the switch system are powered on.

In another aspect, the present invention further provides a device for power-on management of switch systems, wherein the device comprises:

at least processors, and

a memory storing processor-executable program instructions that, when executed by the processor, perform the steps of:

In an embodiment of the apparatus for switch system power on management according to the present invention, wherein the program instructions when executed by the processor further perform the steps of:

In an embodiment of the apparatus for power-on management of a switch system according to the present invention, wherein the power is switched on to enable the switch system to enter an externally triggered power-on state, the performing of the service initialization by the BMC and sending an initialization completion signal after completion further includes:

the switch system enters an external trigger power-on state through the BIOS.

According to the embodiment of the device for the switch system power-on management, the CPLD/FPGA is configured to be connected with the BMC through the GPIO interface, and the GPIO interface is configured to access a high-level signal by default,

An embodiment of the apparatus for power on management of an exchange system according to the present invention, wherein in response to the CPLD/FPGA receiving the standby signal, the CPLD/FPGA controlling the power pack by to power on each component of the exchange system further includes:

the CPLD/FPGA sends a power supply enabling signal to the power supply pack;

By adopting the technical scheme, the invention at least has the following beneficial effects: by means of the CPLD/FPGA, sequential control is carried out on the power-on of the BMC and other components in the switch system, the problems that the service of the BMC is not well initialized when the CPU is started, and corresponding basic services including a fan in the switch system are in an out-of-control state at the moment are solved, and the defects that unnecessary power consumption is increased, and the noise is large when the fan is started, so that bad influence is caused to a client are overcome. The method according to the invention is not limited to use in switch systems, but is also of value for server systems with BMC.

The present invention provides aspects of embodiments, which should not be used to limit the scope of the present invention. Other embodiments are contemplated in accordance with the techniques described herein, as will be apparent to one of ordinary skill in the art upon study of the following figures and detailed description, and are intended to be included within the scope of the present application.

Embodiments of the invention are explained and described in more detail below with reference to the drawings, but they should not be construed as limiting the invention.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the prior art and the description of the embodiments will be briefly described below, parts in the drawings are not drawn to scale, and related elements may be omitted, or in some cases the scale may have been exaggerated to emphasize and clearly illustrate the novel features described herein.

Fig. 1 shows a schematic block diagram of an embodiment of a method of switch system boot management according to the present invention.

Detailed Description

While the present invention may be embodied in various forms, there is shown in the drawings and will hereinafter be described exemplary and non-limiting embodiments, with the understanding that the present disclosure is to be considered an exemplification of the invention and is not intended to limit the invention to the specific embodiments illustrated.

Fig. 1 shows a schematic block diagram of an embodiment of a method of switch system boot management according to the present invention. In the embodiment shown in the figure, the method comprises at least:

s1: accessing a power supply to enable the switch system to enter an external trigger starting state, executing service initialization by the BMC and sending an initialization completion signal after the initialization is completed;

s2: responding to the CPLD/FPGA receiving an initialization completion signal sent by the BMC, and sending a simulated starting signal to the switch system by the CPLD/FPGA;

s3: the switch system performs power-on standby preparation based on the simulated starting signal and feeds back the standby signal to the CPLD/FPGA;

and S4, responding to the CPLD/FPGA receiving the standby signal, and controlling the power pack to power on all parts of the switch system by .

In order to solve the problem of controlling the basic services of the switch system with the BMC at startup, in the embodiment of the present invention, after the system is connected to the AC power source, the switch system and the BMC are not directly powered up and initialized at the same time, but the switch system is configured to be in an external trigger power-on state in step S1, and the BMC executes service initialization and sends out an initialization completion signal BMC _ INIT _ OK _ N after the completion of the power-on operation, it should be noted that the system connected to the AC power source described herein is preferably understood as enabling the AC power source by pressing a power-on key or the like to notify the system of startup.

The following will describe a further embodiment of the present invention, it should be noted that the numbering of the steps mentioned therein is only used for the convenience of indicating the steps explicitly without specific description, and does not limit the order of the steps.

In a further embodiment of the method for switch system power-on management of the present invention, the method further comprises:

s5: and in response to the CPLD/FPGA not receiving the initialization completion signal sent by the BMC after the preset time, the CPLD/FPGA controls the BMC fault indicator lamp to light up and sends a simulated starting signal to the switch system.

In cases, for example, the BMC fails to complete the initialization of the basic service due to reasons and does not send an initialization completion signal, therefore, in step S5 of step of the present invention, when the CPLD/FPGA does not receive the initialization completion signal sent by the BMC for more than a predetermined time, the CPLD/FPGA controls the BMC fault indicator to light up and send a simulated power-on signal to the switch system.

In embodiments of the method for managing the switch system in a power-on mode, the step S1 of accessing a power supply to enable the switch system to enter an external triggered power-on state, the BMC executing the service initialization and sending an initialization completion signal after the completion step includes that a system STBY power supply supplies power to the BMC to perform the service initialization and enabling the switch system to enter the external triggered power-on state through a BIOS.

In several embodiments of the method for switch system power-on management of the present invention, the CPLD/FPGA is configured to be connected to the BMC through a GPIO interface, and the GPIO interface is configured to access the high level signal by default the step S2 is performed in response to the CPLD/FPGA receiving the initialization completion signal sent by the BMC, the CPLD/FPGA sending the analog power-on signal to the switch system further includes:

s21: and responding to the BMC to complete the service initialization, and sending an initialization completion signal with low level to the GPIO interface.

In order to ensure that the BMC can communicate with the CPLD/FPGA, in embodiments, the CPLD/FPGA is configured to be connected to the BMC through a GPIO interface, and configures the GPIO interface to access a high-level signal by default to suppress the boot process of the CPLD/FPGA for controlling the switch system.

In or more embodiments of the method for power-on management of an exchange system of the present invention, the step S4, in response to the CPLD/FPGA receiving the standby signal, the CPLD/FPGA controlling the power pack to power on by the components of the exchange system further includes:

s41: the CPLD/FPGA sends a power supply enabling signal to the power supply pack;

s42: the power supply set powers on corresponding components according to the power supply enabling signal and feeds back a power supply indicating signal to the CPLD/FPGA;

s43: and responding to the CPLD/FPGA to receive the power supply indication signal, and executing the steps again until all parts of the switch system are powered on.

After receiving the standby signal, the CPLD/FPGA control power supply group of step S4 powers up each component of the switch system by step is divided into steps S41 of sending power enable signals to the power supply group VRs, then step S42 of powering up the corresponding component VR in the power supply group VRs according to the power enable signal and feeding back a power indication signal power _ good to the CPLD/FPGA, and when the CPLD/FPGA receives the power indication signal power _ good, step S43 executes the steps to power up the next components again (i.e. repeatedly) until all the components of the switch system are powered up completely.

In another aspect, the present invention further provides a device for power-on management of switch systems, wherein the device comprises at least processors, and a memory storing program instructions executable by the processors, the program instructions when executed by the processors perform the following steps:

In a further embodiment of the apparatus for switch system power-on management of the present invention, the method further comprises:

In embodiments of the apparatus for switch system power on management of the present invention, the step S1 accessing a power supply to cause the switch system to enter an external triggered power on state, the BMC performing the service initialization and sending an initialization completion signal after completion further includes powering the BMC by a system STBY power supply to perform the service initialization, and causing the switch system to enter the external triggered power on state through the BIOS.

In several embodiments of the apparatus for switch system power-on management of the present invention, the CPLD/FPGA is configured to be connected to the BMC through the GPIO interface, and the GPIO interface is configured to access the high level signal by default, step S2 is to respond that the CPLD/FPGA receives the initialization completion signal sent by the BMC, and the CPLD/FPGA sends the analog power-on signal to the switch system further includes:

In embodiments of the apparatus for switch system power-on management according to the invention, the step S4, in response to the CPLD/FPGA receiving the standby signal, the CPLD/FPGA controlling the power pack to power up by the components of the switch system further includes:

The devices, apparatuses and the like disclosed in the embodiments of the present invention may be various electronic terminal apparatuses, such as a mobile phone, a Personal Digital Assistant (PDA), a tablet computer (PAD), a smart television and the like, or may be a large terminal apparatus, such as a server and the like, and therefore, the scope of protection disclosed in the embodiments of the present invention should not be limited to a specific type of device, apparatus.

The computer-readable storage media (e.g., memory) described herein may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.

It is to be understood that the features listed above for the different embodiments may be combined with each other to form further embodiments within the scope of the invention, where technically feasible. Furthermore, the specific examples and embodiments described herein are non-limiting, and various modifications of the structure, steps and sequence set forth above may be made without departing from the scope of the invention.

In this application, the use of the conjunction is intended to include the conjunction, the use of definite or indefinite articles is not intended to indicate cardinality.A reference to "the" object or "" and "" objects is intended to mean possible in many such objects.

The above-described embodiments, particularly any "preferred" embodiments, are possible examples of implementations, and are presented merely for a clear understanding of the principles of the invention. Many variations and modifications may be made to the above-described embodiments without departing substantially from the spirit and principles of the technology described herein. All such modifications are intended to be included within the scope of this disclosure.

Claims

1, method for managing the startup of switch system, which is characterized in that the method comprises the following steps:

responding to a CPLD/FPGA receiving an initialization completion signal sent by the BMC, and sending a simulated starting signal to the switch system by the CPLD/FPGA;

the switch system performs power-on standby preparation based on the simulated starting signal and feeds back a standby signal to the CPLD/FPGA;

and responding to the CPLD/FPGA receiving the standby signal, and controlling a power pack to power on all parts of the switch system one by one by the CPLD/FPGA.

2. The method of claim 1, wherein the method further includes:

and in response to the CPLD/FPGA not receiving the initialization completion signal sent by the BMC after the preset time, the CPLD/FPGA controls the BMC fault indicator lamp to be turned on and sends a simulated starting signal to the switch system.

3. The method of claim 1, wherein accessing power to cause the switch system to enter an externally triggered power-on state, wherein performing service initialization by the BMC and issuing an initialization complete signal after completion further comprises:

supplying power to the BMC by a system STBY power supply for service initialization;

and enabling the switch system to enter an external trigger starting state through the BIOS.

4. The method of claim 1, wherein the CPLD/FPGA is configured to interface with the BMC via a GPIO interface, and wherein the GPIO interface is configured to access high level signals by default,

the step of sending an analog boot signal to the switch system in response to the CPLD/FPGA receiving the initialization completion signal sent by the BMC further includes:

and responding to the completion of service initialization by the BMC, and sending an initialization completion signal of low level to the GPIO interface.

5. The method of claim 1, wherein the CPLD/FPGA controlling a power pack to power up -by- -steps components of the switch system in response to the CPLD/FPGA receiving the standby signal comprises:

the CPLD/FPGA sends a power supply enabling signal to the power supply pack;

and responding to the CPLD/FPGA receiving the power supply indication signal, and executing the steps again until all parts of the switch system are powered on.

The device for managing the boot of the switch system of the type , comprising:

at least processors, and

7. The apparatus of claim 6 wherein the program instructions, when executed by the processor, further perform the steps of:

8. The apparatus of claim 6, wherein the accessing of the power to cause the switch system to enter an externally triggered power-on state, the performing of the service initialization by the BMC and the issuing of the initialization complete signal after completion further comprises:

9. The device of claim 6, wherein the CPLD/FPGA is configured to be connected with the BMC through a GPIO interface, and the GPIO interface is configured to access a high level signal by default,

10. The apparatus of claim 6, wherein the CPLD/FPGA control power pack to power up the switch system components by steps in response to the CPLD/FPGA receiving the standby signal comprises:

the CPLD/FPGA sends a power supply enabling signal to the power supply pack;