CN110739979A - hundred mega Ethernet self-adaptive threshold circuit - Google Patents

hundred mega Ethernet self-adaptive threshold circuit Download PDF

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CN110739979A
CN110739979A CN201910964244.4A CN201910964244A CN110739979A CN 110739979 A CN110739979 A CN 110739979A CN 201910964244 A CN201910964244 A CN 201910964244A CN 110739979 A CN110739979 A CN 110739979A
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metal aluminum
circuit
pmos
nmos transistor
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CN110739979B (en
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王星
张国贤
徐晓斌
赵霁
朱银忠
陈镇
朱佳
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CETC 58 Research Institute
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference

Abstract

The invention discloses hundred-mega Ethernet adaptive threshold circuits, which belong to the technical field of communication, wherein each hundred-mega Ethernet adaptive threshold circuit comprises a peak value-valley value detection circuit and a threshold value generation circuit, specifically, each peak value-valley value detection circuit comprises a peak value detection circuit and a valley value detection circuit, the peak value and the valley value of the waveform of an input signal MLT-3 are respectively measured, and signals are output to the threshold value generation circuit, each threshold value generation circuit comprises a unit gain negative feedback structure and a resistance voltage division circuit, and the output signals of the peak value-valley value detection circuits are subjected to voltage division through resistors to obtain slice threshold values Vthp, Vthn and common-mode voltage Vcm required by data slicing.

Description

hundred mega Ethernet self-adaptive threshold circuit
Technical Field
The invention relates to the technical field of communication, in particular to an hundred-megaEthernet self-adaptive threshold circuit.
Background
In the field of communications, the initial ethernet transmission rate is only 10Mbps, and a wideband transmission scheme based on the CSMA/CD (carrier sense Multiple Access with Collision Detection) protocol is adopted, which is called standard ethernet. As networks continue to evolve, it has become difficult for conventional standard ethernet networks to meet the ever-increasing network rate demands. In 3 months 1995, the IEEE has formally released the fast Ethernet (100BASE-TX) standard: ieee802.3u, opens the 100M ethernet era.
A100 BASE-TX based 100M Ethernet transmission medium is composed of two 5-class Unshielded Twisted Pair (UTP) pairs, pairs are connected to a hub, and another pairs are led out from the hub to support a full duplex mode, a digital domain adopts a coding mode that a 4b data interface of a MAC layer and a PHY layer starts, firstly, 4b/5b coding is carried out, parallel 25M 4b data is converted into parallel 25M 5b data, enough jump in a binary code stream transmitted in a line is ensured, 5b data is converted into serial 125M NRZ (non-return-to-zero code) coded data through a parallel-serial conversion module and then is converted into NRZ (non-return-to-zero inverted code) coding, both the NRZ and the ZINRZ are twisted Pair codes, only positive and zero levels and negative levels are avoided, a plurality of unipolar direct current components are contained, the unipolar direct current components are still not suitable for being transmitted as an electrical interface signal, and finally, the MLT-3 (multi-level transmission code) coding is carried out, and the MLT-3 coding process is obtained and is transmitted to an analog signal driver as shown in a picture 1.
The MLT-3 coding is tri-state coding, which comprises logics of +1, 0 and-1, and is characterized in that the coding is changed when the coding is changed to 1 and is kept unchanged when the coding is changed to 0, the output of the hundred mega Ethernet physical layer driver is used for carrying out differential MLT3 waveforms, and the IEEE802.3u protocol is used for carrying out specific specification on MLT3 waveforms, wherein the differential output amplitude range is 0.95-1.05V, the differential output current is 38-42 mA, the rising and falling edge time is 3-5 ns, for a receiving circuit, the MLT-3 waveforms received from twisted pairs are subjected to data division, namely, whether a transmission signal is +1, 0 or' -1 is accurately distinguished, the process is called data slicing, the slicing threshold value is particularly important, and whether the slicing threshold value is accurate or not directly influences the error rate of the received data.
At present, a hundred-mega Ethernet product on the market mostly adopts a receiving circuit solution shown in FIG. 2, an analog-to-digital converter (ADC) is adopted to sample and quantize an input differential MLT-3 waveform, a clock of the ADC is provided by a clock recovery circuit, multi-bit data output by the ADC is quantization information of an MLT-3 waveform amplitude, output data of the ADC is processed by a digital circuit, and a data slicing process is completed in a digital domain.
Disclosure of Invention
The invention aims to provide hundred-megaEthernet adaptive threshold circuits to solve the problems of complex structure and high power consumption of the existing ADC receiving solution.
In order to solve the technical problem, the invention provides kinds of hundred-mega Ethernet self-adaptive threshold circuits which are used for a hundred-mega Ethernet PHY chip and comprise a peak value-valley value detection circuit and a threshold value generation circuit;
the peak-valley detection circuit comprises a peak detection circuit and a valley detection circuit, respectively measures the peak value and the valley value of the input signal, and outputs the signal to the threshold value generation circuit;
the threshold generation circuit comprises a unit gain negative feedback structure and a resistance voltage division circuit, the output signal of the peak-valley detection circuit is subjected to resistance voltage division to obtain slice thresholds Vthp and Vthn and a common-mode voltage Vcm required by data slicing, and the slice thresholds Vthp and Vthn automatically adapt to the amplitude of the input signal.
The peak detection circuit comprises a comparator CMP1, NMOS tubes MN1 and MN2, PMOS tubes MP1 and MP2 and a load capacitor Cp; wherein the content of the first and second substances,
the substrate of the PMOS transistor MP1, the source electrode of the PMOS transistor MP2 and the substrate are connected with a power supply voltage VDD through metal aluminum; the grid electrode of the PMOS tube MP2 is connected with a bias voltage VB1 through metal aluminum, the grid electrode of the PMOS tube MP1 is connected with the output end of the comparator CMP1 through metal aluminum, and the drain electrode of the PMOS tube MP2 is connected with the source electrode of the PMOS tube MP1 through metal aluminum;
the substrate of the NMOS transistor MN1, the source electrode of the NMOS transistor MN2 and the substrate are connected with the ground GND through metal aluminum; the grid electrode of the NMOS transistor MN1 is connected with a bias voltage VB2 through metal aluminum, and the grid electrode of the NMOS transistor MN2 is connected with a bias voltage VB3 through metal aluminum; the source electrode of the NMOS transistor MN1 is connected with the drain electrode of the NMOS transistor MN2 through metal aluminum;
the drain electrode of the PMOS tube MP1, the drain electrode of the NMOS tube MN1, the positive phase end of the comparator CMP1 and the upper plate of the load capacitor Cp are connected through metal aluminum and are connected to an output signal Vp-mid;
the inverting terminal of the comparator CMP1 is connected to the input signal VIN through metal aluminum, and the lower plate of the load capacitor Cp is grounded.
The NMOS tubes MN1 and MN2, the PMOS tubes MP1 and MP2 and the load capacitor Cp form a charging and discharging circuit, and the pull-up current of the charging and discharging circuit is 5-10 times of the pull-down current.
The valley detection circuit comprises a comparator CMP2, NMOS tubes MN3 and MN4, PMOS tubes MP3 and MP4 and a load capacitor Cv; wherein the content of the first and second substances,
the substrate of the NMOS transistor MN3, the source electrode of the NMOS transistor MN4 and the substrate are connected with the ground GND through metal aluminum; the grid electrode of the NMOS transistor MN4 is connected with a bias voltage VB3 through metal aluminum, and the grid electrode of the NMOS transistor MN3 is connected with the output end of the comparator CMP2 through metal aluminum; the drain electrode of the NMOS transistor MN4 is connected with the source electrode of the NMOS transistor MN3 through metal aluminum;
the substrate of the PMOS transistor MP3, the source electrode of the PMOS transistor MP4 and the substrate are connected to a power supply voltage VDD through metal aluminum; the gate of the PMOS transistor MP4 is connected to a bias voltage VB1 through metal aluminum; the gate of the PMOS transistor MP3 is connected to a bias voltage VB4 through metal aluminum; the source electrode of the PMOS tube MP3 is connected with the drain electrode of the PMOS tube MP4 through metal aluminum;
the drain electrode of the NMOS transistor MN3, the drain electrode of the PMOS transistor MP3, the positive phase end of the comparator CMP2 and the upper plate of the load capacitor Cv are interconnected through metal aluminum and connected to an output signal Vv-mid;
the inverting terminal of the comparator CMP2 is connected with an input signal VIN through metal aluminum, and the lower plate of the load capacitor Cv is grounded.
The NMOS tubes MN3 and MN4, the PMOS tubes MP3 and MP4 and the load capacitor Cv form a charge-discharge circuit, and pull-up current of the charge-discharge circuit is 5-10 times of pull-down current.
The unit gain negative feedback structure comprises operational amplifiers AMP1 and AMP2, an NMOS transistor MN5 and a PMOS transistor MP5, wherein a source electrode and a drain electrode of the PMOS transistor MP5 are connected with a power supply voltage VDD through metal aluminum, a grid electrode of the PMOS transistor MP5 is connected with an output end of the operational amplifier AMP1 through metal aluminum, an inverting end of the operational amplifier AMP1 is connected with an output signal Vp-mid through metal aluminum, and a positive phase end, a drain electrode of the PMOS transistor MP5, an end of the resistance voltage division circuit and a filter resistor Rf are connected with each other through metal aluminum;
the source electrode and the drain electrode of the NMOS tube MN5 are connected with the ground GND through metal aluminum, the grid electrode of the NMOS tube MN5 is connected with the output end of the operational amplifier AMP2 through metal aluminum, the inverting end of the operational amplifier AMP2 is connected with an output signal Vv-mid through metal aluminum, and the positive end, the drain electrode of the NMOS tube MN5, the other end of the resistance voltage division circuit and the filter resistor Rf are interconnected through metal aluminum.
The resistance voltage division circuit comprises resistors R1-R4 with equal resistance values; the resistor R1, the resistor R2, the resistor R3 and the resistor R4 are sequentially connected in series to play a role of voltage division; and respectively obtaining slice thresholds Vthp and Vthn and a common-mode voltage Vcm through voltage division.
The invention provides hundred-mega Ethernet self-adaptive threshold circuits, which comprise a peak value-valley value detection circuit and a threshold value generation circuit, wherein the peak value-valley value detection circuit comprises a peak value detection circuit and a valley value detection circuit, the peak value and the valley value of the waveform of an input signal MLT-3 are respectively measured, signals are output to the threshold value generation circuit, the threshold value generation circuit comprises a unit gain negative feedback structure and a resistance voltage division circuit, and the output signals of the peak value-valley value detection circuit are subjected to resistance voltage division to obtain slice threshold values Vthp and Vthn and common-mode voltage Vcm required by data slicing.
The invention has the following beneficial effects:
(1) the circuit can be realized through common NMOS (N-channel metal oxide semiconductor) transistors and PMOS (P-channel metal oxide semiconductor) transistors in a CMOS (complementary metal oxide semiconductor) process, has a simple structure and is easy to push ;
(2) compared with the existing ADC receiving solution, the ADC receiving solution has the advantages of lower power consumption, smaller area and lower cost;
(3) the circuit application range is widely applied to the technical field of design of hundred-mega Ethernet physical layer chips without the cooperation of a clock circuit.
Drawings
FIG. 1 is a coding diagram of a hundred mega Ethernet PHY chip;
FIG. 2 is a schematic diagram of a data reception scheme employing an ADC;
fig. 3 is a circuit diagram of a hundred mega ethernet adaptive threshold circuit provided by the present invention;
fig. 4 is a schematic view of a data slice.
Detailed Description
The gigabit ethernet adaptive threshold circuit is described in further detail below in conjunction with the figures and the detailed description, advantages and features of the present invention will become more apparent from the following description and claims.
Example
The invention provides an hundred-mega Ethernet self-adaptive threshold circuit which comprises a peak value-valley value detection circuit and a threshold value generation circuit, wherein the peak value-valley value detection circuit comprises a peak value detection circuit and a valley value detection circuit, the peak value and the valley value of the waveform of an input signal MLT-3 are respectively measured, signals are output to the threshold value generation circuit, the threshold value generation circuit comprises a unit gain negative feedback structure and a resistance voltage division circuit, and the output signals of the peak value-valley value detection circuit are subjected to voltage division through resistors to obtain slice threshold values Vthp and Vthn and common-mode voltage Vcm required by data slicing.
Specifically, as shown in fig. 3, the peak detection circuit includes a comparator CMP1, NMOS transistors MN1 and MN2, PMOS transistors MP1 and MP2, and a load capacitor Cp; the substrate of the PMOS transistor MP1, the source electrode of the PMOS transistor MP2 and the substrate are connected with a power supply voltage VDD through metal aluminum; the grid electrode of the PMOS tube MP2 is connected with a bias voltage VB1 through metal aluminum, the grid electrode of the PMOS tube MP1 is connected with the output end of the comparator CMP1 through metal aluminum, and the drain electrode of the PMOS tube MP2 is connected with the source electrode of the PMOS tube MP1 through metal aluminum; the substrate of the NMOS transistor MN1, the source electrode of the NMOS transistor MN2 and the substrate are connected with the ground GND through metal aluminum; the grid electrode of the NMOS transistor MN1 is connected with a bias voltage VB2 through metal aluminum, and the grid electrode of the NMOS transistor MN2 is connected with a bias voltage VB3 through metal aluminum; the source electrode of the NMOS transistor MN1 is connected with the drain electrode of the NMOS transistor MN2 through metal aluminum; the drain electrode of the PMOS tube MP1, the drain electrode of the NMOS tube MN1, the positive phase end of the comparator CMP1 and the upper plate of the load capacitor Cp are connected through metal aluminum and are connected to an output signal Vp-mid; the inverting terminal of the comparator CMP1 is connected to the input signal VIN through metal aluminum, and the lower plate of the load capacitor Cp is grounded.
The valley detection circuit comprises a comparator CMP2, NMOS tubes MN3 and MN4, PMOS tubes MP3 and MP4 and a load capacitor Cv; the substrate of the NMOS transistor MN3, the source electrode of the NMOS transistor MN4 and the substrate are connected with the ground GND through metal aluminum; the grid electrode of the NMOS transistor MN4 is connected with a bias voltage VB3 through metal aluminum, and the grid electrode of the NMOS transistor MN3 is connected with the output end of the comparator CMP2 through metal aluminum; the drain electrode of the NMOS transistor MN4 is connected with the source electrode of the NMOS transistor MN3 through metal aluminum; the substrate of the PMOS transistor MP3, the source electrode of the PMOS transistor MP4 and the substrate are connected to a power supply voltage VDD through metal aluminum; the gate of the PMOS transistor MP4 is connected to a bias voltage VB1 through metal aluminum; the gate of the PMOS transistor MP3 is connected to a bias voltage VB4 through metal aluminum; the source electrode of the PMOS tube MP3 is connected with the drain electrode of the PMOS tube MP4 through metal aluminum; the drain electrode of the NMOS transistor MN3, the drain electrode of the PMOS transistor MP3, the positive phase end of the comparator CMP2 and the upper plate of the load capacitor Cv are interconnected through metal aluminum and connected to an output signal Vv-mid; the inverting terminal of the comparator CMP2 is connected with an input signal VIN through metal aluminum, and the lower plate of the load capacitor Cv is grounded.
With reference to fig. 3, the threshold generating circuit comprises a unit gain negative feedback structure and a resistance voltage divider circuit, the unit gain negative feedback structure comprises operational amplifiers AMP1 and AMP2, an NMOS tube MN5 and a PMOS tube MP5, wherein a source and a drain of the PMOS tube MP5 are connected to a power supply voltage VDD through metal aluminum, a gate is connected to an output end of the operational amplifier AMP1 through metal aluminum, an inverting terminal of the operational amplifier AMP1 is connected to an output signal Vp-mid through metal aluminum, a positive terminal, a drain of the PMOS tube MP5, a resistance voltage divider circuit and a filter resistance Rf are interconnected through metal aluminum, a source and a drain of the NMOS tube MN5 are connected to ground GND through metal aluminum, a gate is connected to an output end of the operational amplifier AMP2 through metal aluminum, an inverting terminal of the operational amplifier 2 is connected to the output signal Vv-mid through metal aluminum, a positive terminal, a drain of the NMOS tube MN5, a voltage divider circuit of the voltage divider resistor MP and a filter resistance resistor Rf are connected in series through metal aluminum resistors vtr 1, vtr 1 and vtr 3642, and the common mode resistor chip 3 are connected in series.
The working process and the working principle of the invention are as follows:
the working principle of the peak detection circuit is that in the peak detection circuit, NMOS tubes MN1 and MN2, PMOS tubes MP1 and MP2 and a load capacitor Cp form a charge-discharge circuit, the pull-up current is far larger than the pull-down current, sets the pull-up current to be 5-10 times of the pull-down current, the input signal VIN is assumed to be sine wave, no charge exists on the load capacitor Cp at the initial moment, the output voltage Vp-mid is 0, the input signal is larger than the output signal, a comparator CMP1 outputs low level, the PMOS tube MP1 is turned on, the load capacitor Cp is charged, the output voltage Vp-mid is quickly pulled up to the vicinity of the peak value of the input signal VIN due to the fact that the pull-up current is far larger than the pull-down current, when the input signal is lower than the output voltage Vp-mid, the comparator CMP1 outputs high level, the load capacitor Cp is discharged through NMOS tubes MN1 and MN2, but when the input signal is far smaller than the pull-up current, the output voltage Vp-mid is very slowly reduced, the output voltage is again to the vicinity of the peak value of the output voltage VIN, and the final ripple of the output peak value is very small.
The principle of the valley detection circuit is similar to that of the peak detection circuit, the NMOS tubes MN3 and MN4, the PMOS tubes MP3 and MP4 and the load capacitor Cv form a charge-discharge circuit in the valley detection circuit, the pull-down current is correspondingly set to be 5-10 times of the pull-up current, and finally the valley voltage Vv-mid is obtained.
The working principle of the threshold generating circuit is as follows: the threshold generating circuit comprises a unit gain negative feedback structure and a resistance voltage division circuit; the unit gain negative feedback structure comprises operational amplifiers AMP1 and AMP2, an NMOS transistor MN5 and a PMOS transistor MP 5; the resistance voltage division circuit comprises resistors R1-R4 with equal resistance values. The output voltages Vp-mid and Vv-mid of the peak-valley detection circuit are respectively connected to the inverting terminals of the operational amplifiers AMP1 and AMP2, the unit gain negative feedback structure clamps the voltages at the two ends of the resistance voltage division circuit to Vp-mid and Vv-mid, ripples exist on the detected peak-valley voltage due to the charging and discharging of the capacitor, and the ripple voltage in the signal is filtered by adding a low-pass filter circuit (a filter resistor Rf and a filter capacitor Cf) in order to reduce the circuit noise. Slice threshold values Vthp, Vthn and common-mode voltage Vcm are respectively obtained through resistance voltage division, and the voltage values are respectively as follows:
Figure BDA0002229958430000071
Figure BDA0002229958430000072
Figure BDA0002229958430000073
finally, the MLT-3 waveform is equally divided into four intervals: Vv-Vthn, Vthn-Vcm, Vcm-Vthp, Vthp-Vp, as shown in FIG. 4, these thresholds are supplied to a comparator circuit, and data slicing is performed on the input differential signal; meanwhile, the driving capability of the output signal is increased through a unit gain negative feedback structure.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (7)

  1. The self-adaptive threshold circuit of the hundred-mega Ethernet is used in a PHY chip of the hundred-mega Ethernet and is characterized by comprising a peak value-valley value detection circuit and a threshold value generation circuit;
    the peak-valley detection circuit comprises a peak detection circuit and a valley detection circuit, respectively measures the peak value and the valley value of the input signal, and outputs the signal to the threshold value generation circuit;
    the threshold generation circuit comprises a unit gain negative feedback structure and a resistance voltage division circuit, the output signal of the peak-valley detection circuit is subjected to resistance voltage division to obtain slice thresholds Vthp and Vthn and a common-mode voltage Vcm required by data slicing, and the slice thresholds Vthp and Vthn automatically adapt to the amplitude of the input signal.
  2. 2. The adaptive threshold circuit for a hundred mega Ethernet according to claim 1, wherein the peak detection circuit comprises a comparator CMP1, NMOS transistors MN1 and MN2, PMOS transistors MP1 and MP2, a load capacitor Cp; wherein the content of the first and second substances,
    the substrate of the PMOS transistor MP1, the source electrode of the PMOS transistor MP2 and the substrate are connected with a power supply voltage VDD through metal aluminum; the grid electrode of the PMOS tube MP2 is connected with a bias voltage VB1 through metal aluminum, the grid electrode of the PMOS tube MP1 is connected with the output end of the comparator CMP1 through metal aluminum, and the drain electrode of the PMOS tube MP2 is connected with the source electrode of the PMOS tube MP1 through metal aluminum;
    the substrate of the NMOS transistor MN1, the source electrode of the NMOS transistor MN2 and the substrate are connected with the ground GND through metal aluminum; the grid electrode of the NMOS transistor MN1 is connected with a bias voltage VB2 through metal aluminum, and the grid electrode of the NMOS transistor MN2 is connected with a bias voltage VB3 through metal aluminum; the source electrode of the NMOS transistor MN1 is connected with the drain electrode of the NMOS transistor MN2 through metal aluminum;
    the drain electrode of the PMOS tube MP1, the drain electrode of the NMOS tube MN1, the positive phase end of the comparator CMP1 and the upper plate of the load capacitor Cp are connected through metal aluminum and are connected to an output signal Vp-mid;
    the inverting terminal of the comparator CMP1 is connected to the input signal VIN through metal aluminum, and the lower plate of the load capacitor Cp is grounded.
  3. 3. The self-adaptive threshold circuit of the gigabit Ethernet as claimed in claim 2, wherein the NMOS transistors MN1 and MN2, the PMOS transistors MP1 and MP2, and the load capacitor Cp form a charging and discharging circuit, and the pull-up current of the charging and discharging circuit is 5-10 times of the pull-down current.
  4. 4. The gigabit ethernet adaptive threshold circuit of claim 1, wherein the valley detection circuit comprises a comparator CMP2, NMOS transistors MN3 and MN4, PMOS transistors MP3 and MP4, a load capacitor Cv; wherein the content of the first and second substances,
    the substrate of the NMOS transistor MN3, the source electrode of the NMOS transistor MN4 and the substrate are connected with the ground GND through metal aluminum; the grid electrode of the NMOS transistor MN4 is connected with a bias voltage VB3 through metal aluminum, and the grid electrode of the NMOS transistor MN3 is connected with the output end of the comparator CMP2 through metal aluminum; the drain electrode of the NMOS transistor MN4 is connected with the source electrode of the NMOS transistor MN3 through metal aluminum;
    the substrate of the PMOS transistor MP3, the source electrode of the PMOS transistor MP4 and the substrate are connected to a power supply voltage VDD through metal aluminum; the gate of the PMOS transistor MP4 is connected to a bias voltage VB1 through metal aluminum; the gate of the PMOS transistor MP3 is connected to a bias voltage VB4 through metal aluminum; the source electrode of the PMOS tube MP3 is connected with the drain electrode of the PMOS tube MP4 through metal aluminum;
    the drain electrode of the NMOS transistor MN3, the drain electrode of the PMOS transistor MP3, the positive phase end of the comparator CMP2 and the upper plate of the load capacitor Cv are interconnected through metal aluminum and connected to an output signal Vv-mid;
    the inverting terminal of the comparator CMP2 is connected with an input signal VIN through metal aluminum, and the lower plate of the load capacitor Cv is grounded.
  5. 5. The gigabit Ethernet adaptive threshold circuit according to claim 4, wherein the NMOS transistors MN3 and MN4, the PMOS transistors MP3 and MP4, and the load capacitor Cv form a charge-discharge circuit, and a pull-up current of the charge-discharge circuit is 5-10 times of a pull-down current.
  6. 6. The gigabit ethernet adaptive threshold circuit of claim 1, wherein the unity gain negative feedback architecture comprises operational amplifiers AMP1 and AMP2, NMOS transistor MN5, PMOS transistor MP 5; wherein the content of the first and second substances,
    the PMOS tube MP5 is characterized in that a source electrode and a drain electrode are connected with a power supply voltage VDD through metal aluminum, a grid electrode is connected with an output end of the operational amplifier AMP1 through metal aluminum, an inverting end of the operational amplifier AMP1 is connected with an output signal Vp-mid through metal aluminum, and a positive phase end, the drain electrode of the PMOS tube MP5, an end of the resistance voltage division circuit and the filter resistor Rf are interconnected through metal aluminum;
    the source electrode and the drain electrode of the NMOS tube MN5 are connected with the ground GND through metal aluminum, the grid electrode of the NMOS tube MN5 is connected with the output end of the operational amplifier AMP2 through metal aluminum, the inverting end of the operational amplifier AMP2 is connected with an output signal Vv-mid through metal aluminum, and the positive end, the drain electrode of the NMOS tube MN5, the other end of the resistance voltage division circuit and the filter resistor Rf are interconnected through metal aluminum.
  7. 7. The self-adaptive threshold circuit of the gigabit ethernet according to claim 1, wherein the resistor divider circuit comprises resistors R1 to R4 having equal resistance values; the resistor R1, the resistor R2, the resistor R3 and the resistor R4 are sequentially connected in series to play a role of voltage division; slice thresholds Vthp and Vthn and a common-mode voltage Vcm are obtained through voltage division respectively, and the slice thresholds are automatically adaptive to the amplitude of an input signal.
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