CN1107341C - Method for pattering insulator film by electron beam irradiation - Google Patents

Method for pattering insulator film by electron beam irradiation Download PDF

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Publication number
CN1107341C
CN1107341C CN98124903A CN98124903A CN1107341C CN 1107341 C CN1107341 C CN 1107341C CN 98124903 A CN98124903 A CN 98124903A CN 98124903 A CN98124903 A CN 98124903A CN 1107341 C CN1107341 C CN 1107341C
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semiconductor chip
dielectric film
film
electron beam
diaphragm
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Expired - Fee Related
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CN98124903A
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CN1218278A (en
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小森基史
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2051—Exposure without an original mask, e.g. using a programmed deflection of a point source, by scanning, by drawing with a light beam, using an addressed light or corpuscular source
    • G03F7/2059—Exposure without an original mask, e.g. using a programmed deflection of a point source, by scanning, by drawing with a light beam, using an addressed light or corpuscular source using a scanning corpuscular radiation beam, e.g. an electron beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Electron Beam Exposure (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A process for patterning an insulator film formed on a semiconductor substrate forms contact holes in the insulator film and also exposes a portion of the semiconductor substrate. The exposed portion is used for grounding the substrate during an electron beam irradiation step to an overlying insulator film for preventing the charge-up of the interface between the insulator film and the substrate.

Description

Make the method for dielectric film line pattern by electron beam irradiation
The present invention relates to a kind of method of using electron beam irradiation dielectric film to be made figure by direct wiring technique, more particularly, relating to a kind of effectively preventing when making the dielectric film figure is charged by electron production during the direct wiring of using electron beam irradiation.
The exposure technology of making semiconductor device roughly is divided into two kinds; a kind of is graphic conversion technology; it is transformed on the photoresist film by the figure of using up or the X-ray will be formed on the mask, and another kind of directly wiring technique is will write on the diaphragm according to the figure that layout draws by electron beam direct.
In direct wiring technique, if the ground connection of wafer or substrate is incomplete during on the dielectric film of electron beam irradiation to the wafer, will produce the electronics charging, wherein electronics accumulates on the interface between wafer and dielectric film.Thereby charging can cause the electron beam deflecting to make the figure deformation that is obtained between radiation era, and it will hinder direct wiring technique to obtain fine pattern.
Fig. 1 is illustrated in during the direct Wiring technique that uses electron beam the conventional art with wafer ground connection.Suitable power will be inserted on the wafer 11 to guarantee that ground lead 17 passes diaphragm 13 and dielectric film (SiO by having most advanced and sophisticated ground lead 17 usefulness 2) 12 and contact with wafer 11 grid and can around wafer, not produce any dust.Yet, in semiconductor device, during making top insulating layer, be difficult to guarantee to make wafer dead ground by ground lead 17 with multilayer interconnection layer, can't effectively suppress the problem of charging thus.
Patent gazette JP-A-1-220441 has disclosed a kind of improved direct wiring technique, and it can suppress charging in the multilayer interconnect structure of semiconductor device.In this scheme; before forming second diaphragm; by selecting to remove the counterpart that ground lead passes the following layer insulating of insulating barrier with the photoetching technique of first diaphragm, ground lead passes second diaphragm and contacts with substrate during making the top dielectric film.This technology can guarantee that ground lead passes at an easy rate with substrate and join.
Yet the direct wiring technique that is proposed is will remove the step of underclad portion as a kind of additional step, and it can reduce the production efficiency of direct wiring technique.
At the problems referred to above, the purpose of this invention is to provide a kind of direct wiring that is used to make figure
Technology can effectively suppress the charging of electronics, and need not increase processing step, and can not reduce the productivity ratio of direct Wiring technique.
Above-mentioned purpose of the present invention realizes by following method, according to a kind of method of making semiconductor device of the present invention, comprises following steps: form dielectric film on semiconductor chip; By the radiating electron bundle described dielectric film graphics processing is connect the hole to form in described dielectric film, described graphics processing step exposes the first of described semiconductor chip, and on the second portion of described semiconductor chip, form required figure simultaneously, and ground lead is received in the described first that exposes of described semiconductor chip.
Described dielectric film making step uses the eurymeric diaphragm as mask.
In according to another aspect of the present invention, a kind of method of making semiconductor device, it comprises following steps, forms dielectric film on semiconductor chip; By the radiating electron bundle described dielectric film graphics processing is connect the hole to form in described dielectric film, described graphics processing step exposes the first (11a) of described semiconductor chip, and forms required figure simultaneously on the second portion of described semiconductor chip; In the described described step that forms conducting film on the part that exposes of being produced the dielectric film and the described semiconductor chip of figure; By the radiating electron bundle described conducting film is made the part of figure with the described conducting film in the described first that reserves interconnection graph and described semiconductor chip on the described second portion of described semiconductor chip, the part of the described conducting film that stays by described graphics processing contacts with the first of described semiconductor chip; And on the part of the described conducting film that contacts with the described first of described semiconductor chip, set up ground lead.
Described conducting film make the figure step by the minus diaphragm as mask.
According to the inventive method, the step that the removal dielectric film is used to expose the substrate first that is provided with ground lead is with the dielectric film graphics processing is carried out with the step that formation connects the hole.Like this, can avoid increasing the reduction of processing step and production technology productivity ratio.
Can be by technology to above-mentioned and other purpose of the present invention below in conjunction with respective drawings, characteristics have clearer understanding.
Fig. 1 is at the direct sectional view of wafer during the Wiring technique of the tradition that is used to make figure;
Fig. 2 A is the schematic cross-section of wafer that is used for showing direct Wiring technique consecutive steps according to first embodiment of the invention to 2D;
Fig. 3 A is the schematic cross-section of wafer that is used for showing direct Wiring technique consecutive steps according to second embodiment of the invention to 3E.
Below with reference to respective drawings the present invention is described in detail, wherein represents similar parts with identical label.
To 2D, it illustrates the direct Wiring technique according to first embodiment of the invention with reference to figure 2A.In Fig. 2 A, on wafer (semiconductor chip) 11, form dielectric film 12 with known technology, then form positive diaphragm 13 by the liquid that uses forward type chemistry photoresist film.
Then, the wafer of making 11 is placed in the chamber that is used for the electron beam direct wiring, is used to comprise the required figure of the semiconductor device that connects the hole therein with electron beam 10 irradiate wafer with the figure of making diaphragm 13 with acquisition.The same part 13a of diaphragm 13 and the underclad portion of dielectric film 12 removed in the processing of butt hole; This place's wafer ground connection, be used to expose the surface portion of wafer.
More specifically, as shown in Fig. 2 B, be that the part 13a of 5mm * 5mm carries out electron beam irradiation and carries out with other graphics processing part of diaphragm 13 to the area of diaphragm 13.The intensity that is used for the electron beam of part 13a is substantially equal to be used to form the intensity of electron beam of the other parts of the diaphragm 13 that connects the hole.In this step, very moderate so can not cause substantive issue in 11 chargings that produce at the interface of dielectric film 12 and substrate.
After this, to by the part 13a of radiation and diaphragm 13 other by radiant section wash be used to select to remove part 13a and diaphragm 13 by radiant section.Usually, the part by removing the dielectric film 12 that exposes from diaphragm 13 as the electron beam exposure method of mask with diaphragm 13 is to be formed for connecing the hole and exposing the surface portion 11a of semiconductor chip 11 of semiconductor chip, as shown in Fig. 2 C.In the case, as shown in Fig. 2 D, ground lead 17 can be connected on the expose portion 11a of substrate 11, thereby obtain ground connection fully for next direct wiring process.In the present embodiment, owing to formed with connecing the hole, therefore do not increase processing step by exposed portions serve 13a.
To 3E, it shows the method for second embodiment of the invention with reference to figure 3A.Similar shown in step shown in Fig. 3 A and Fig. 2 C, wherein dielectric film 12 selected etchings are used to form the expose portion 11a that connects hole and semiconductor chip 11.After the step of Fig. 3 A, aluminium is deposited to the conducting film 14 that has part 14a on the whole surface of wafer with formation, wherein part 14a directly contacts with the expose portion 11a of substrate 11 as shown in Fig. 3 B.Then; the whole surface that the minus liquid protective film is provided to conducting film 14 is to form minus diaphragm 15; then be used to make figure with electron beam 10 radiation minus diaphragms 15; as shown in Fig. 3 C, the electron beam 10 that is radiated on the minus diaphragm 15 that covers conducting film 14 can be by any charging of electron production on the interface of dielectric film 12 and substrate 11.To the diaphragm 15 of described acquisition wash with stay the minus diaphragm 15 that comprises part 15a on the wafer by radiant section.
Then, as mask, conducting film 15 is carried out graphics processing with minus diaphragm 15 by the selection etching of electron beam irradiation.The figure of conducting film 14 has stayed the remainder 14a of required interconnection graph and conducting film 14, as shown in Fig. 3 D.In this stage, with ground lead 17 receive conducting film 14 surplus part 14a go up so that the good earth of substrate 11 to be provided, as shown in Fig. 3 E.
The part 11a that ground lead 17 is installed its with Fig. 3 A in adjacent area between be step-like, it is considered to cause 11 of ground lead 17 and substrates during another dielectric film 18 of formation bad the contact.Yet in the present embodiment, remedy step-like portion, can between the expose portion 11a of ground lead 17 and substrate, provide good like this and contact with the surplus part 14a of conducting film 14.This good contact can prevent the charging of electronics during with 18 graphics processings of electron beam irradiation dielectric film.
In the present embodiment, be used to expose substrate 11 part 11a dielectric film 12 making and can be respectively carry out simultaneously for 11 of ground lead 17 and substrates provide the making of the good conducting film that contacts 14 with the making of the dielectric film 12 that is used for contact hole and the making that is used for the conducting film 14 of interconnection graph.Its result can not increase the production stage that is used for semiconductor device.
Because the foregoing description only for describing embodiment, the invention is not restricted to this, various modifications of being made for a person skilled in the art and qualification do not depart from the scope of the present invention.

Claims (4)

1. method of making semiconductor device is characterized in that comprising following steps:
On semiconductor chip, form dielectric film;
By the radiating electron bundle described dielectric film graphics processing is connect the hole to form in described dielectric film, described graphics processing step exposes the first (11a) of described semiconductor chip, and forms required figure simultaneously on the second portion of described semiconductor chip;
And ground lead is received in the described first that exposes (11a) of described semiconductor chip.
2, method according to claim 1 is characterized in that described dielectric film making step usefulness eurymeric diaphragm is as mask.
3, a kind of method of making semiconductor device is characterized in that comprising following steps:
On semiconductor chip, form dielectric film;
By the radiating electron bundle described dielectric film graphics processing is connect the hole to form in described dielectric film, described graphics processing step exposes the first (11a) of described semiconductor chip, and forms required figure simultaneously on the second portion of described semiconductor chip;
In the described described step that forms conducting film on the part that exposes of being produced the dielectric film and the described semiconductor chip of figure;
By the radiating electron bundle described conducting film is made the part of figure with the described conducting film in the described first that reserves interconnection graph and described semiconductor chip on the described second portion of described semiconductor chip, the part of the described conducting film that stays by described graphics processing contacts with the first of described semiconductor chip; And
On the part of the described conducting film that contacts with the described first of described semiconductor chip, set up ground lead.
4, method according to claim 3, it is characterized in that described conducting film make the figure step by the minus diaphragm as mask.
CN98124903A 1997-11-13 1998-11-13 Method for pattering insulator film by electron beam irradiation Expired - Fee Related CN1107341C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP9312181A JPH11145046A (en) 1997-11-13 1997-11-13 Manufacture of semiconductor device
JP312181/97 1997-11-13
JP312181/1997 1997-11-13

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CN1218278A CN1218278A (en) 1999-06-02
CN1107341C true CN1107341C (en) 2003-04-30

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US (1) US6068964A (en)
JP (1) JPH11145046A (en)
KR (1) KR100307424B1 (en)
CN (1) CN1107341C (en)
TW (1) TW396431B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4302335B2 (en) * 2001-05-22 2009-07-22 株式会社半導体エネルギー研究所 Manufacturing method of solar cell
US8218284B2 (en) 2008-07-24 2012-07-10 Hermes-Microvision, Inc. Apparatus for increasing electric conductivity to a semiconductor wafer substrate when exposure to electron beam
US8094428B2 (en) 2008-10-27 2012-01-10 Hermes-Microvision, Inc. Wafer grounding methodology

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61104617A (en) * 1984-10-29 1986-05-22 Fujitsu Ltd Electron beam exposure method
JPH01220441A (en) * 1988-02-27 1989-09-04 Oki Electric Ind Co Ltd Charge-up preventing method
JPH0231416A (en) * 1988-07-21 1990-02-01 Sony Corp Semiconductor wafer for direct lithography
JPH02174216A (en) * 1988-12-27 1990-07-05 Fujitsu Ltd Manufacture of semiconductor device
JPH02276237A (en) * 1989-04-18 1990-11-13 Oki Electric Ind Co Ltd Lamination of charged beam resist
DE69021119T2 (en) * 1989-04-28 1995-12-21 Fujitsu Ltd Imaging process using an electrically conductive composition.
US5288368A (en) * 1992-12-23 1994-02-22 At&T Bell Laboratories Electron beam lithography with reduced charging effects

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KR100307424B1 (en) 2001-11-30
KR19990045253A (en) 1999-06-25
CN1218278A (en) 1999-06-02
JPH11145046A (en) 1999-05-28
TW396431B (en) 2000-07-01
US6068964A (en) 2000-05-30

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