CN110728952A

CN110728952A - Pixel driving circuit, driving method thereof and display device

Info

Publication number: CN110728952A
Application number: CN201911053617.9A
Authority: CN
Inventors: 李杰良; 黄婉铭
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2019-10-31
Filing date: 2019-10-31
Publication date: 2020-01-24
Anticipated expiration: 2039-10-31
Also published as: CN110728952B

Abstract

The invention discloses a pixel driving circuit, a driving method thereof and a display device, relating to the technical field of display, wherein the pixel driving circuit comprises: the driving circuit comprises a first power supply signal end, a second power supply signal end and a driving transistor, wherein the grid electrode of the driving transistor is connected to a first node, the first pole of the driving transistor is connected to a second node, and the second pole of the driving transistor is connected to a third node; a light emitting element; a light emission control module; the first end of the storage module is electrically connected with the first power signal end, and the second end of the storage module is electrically connected with the first node; the first end of the switch transistor module is connected with the first node, at least part of the switch transistor modules comprise two sub-transistors which are connected in series, the polarities of the two sub-transistors are opposite, and in the same time frame, the two sub-transistors are simultaneously switched on or simultaneously switched off under the control of a control signal. Therefore, the display brightness uniformity of the display device is improved.

Description

Pixel driving circuit, driving method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to a pixel driving circuit, a driving method thereof and a display device.

Background

The organic light emitting display device has the advantages of self-luminescence, low driving voltage, high luminous efficiency, fast response speed, lightness, thinness, high contrast ratio and the like, and is considered as the most promising display device of the next generation.

A pixel in an organic light emitting display device includes a pixel driving circuit in which a driving transistor generates a driving current in response to which a light emitting element emits light, wherein the driving current generated by the driving transistor is related to a voltage between a gate and a source of the driving transistor. In the conventional pixel driving circuit, the switching transistor is turned on or off in different operation stages of the pixel driving circuit, a voltage between the gate and the source of the switching transistor changes during the on-off process of the switching transistor, and the switching transistor generates a coupling capacitance even in the off-state, for example, a coupling capacitance exists between the gate and the source or between the gate and the drain. Because the switching transistor is connected with the gate of the driving transistor, the gate voltage of the driving transistor is affected by the existence of the coupling capacitor of the switching transistor, and when the gate voltage of the driving transistor changes, the driving current generated by the driving transistor may be affected, so that the driving current actually generated by the driving transistor deviates from the preset driving current, and further, the display device has the phenomenon of uneven display brightness, and the display effect is affected.

Disclosure of Invention

In view of this, the invention provides a pixel driving circuit, a driving method thereof and a display device, which are beneficial to improving the display brightness uniformity of the display device and improving the display effect of the display device.

In a first aspect, the present application provides a pixel driving circuit, comprising: a first power signal terminal and a second power signal terminal;

a driving transistor, a gate of the driving transistor being connected to a first node, a first pole of the driving transistor being connected to a second node, and a second pole of the driving transistor being connected to a third node;

the anode of the light-emitting element is connected with the fourth node, and the cathode of the light-emitting element is electrically connected with the second power signal end;

a light emission control module, the driving transistor, and the light emitting element being connected in series between the first power signal terminal and the second power signal terminal;

a first end of the storage module is electrically connected with the first power signal end, and a second end of the storage module is electrically connected with the first node;

at least one switch transistor module, the first end of switch transistor module is connected the first node, at least part the switch transistor module includes two sub-transistors of series connection, two sub-transistor's polarity is opposite, and in same time frame, two sub-transistors switch on simultaneously or cut off simultaneously under control signal's control.

In a second aspect, the present application provides a driving method of a pixel driving circuit, where the driving method is used to drive the pixel driving circuit in the present application, and the driving circuit includes a first power signal terminal, a second power signal terminal, a driving transistor, a light emitting element, a light emitting control module, and at least one switching transistor module, where a first terminal of the switching transistor module is connected to the first node, and at least a part of the switching transistor module includes two sub-transistors connected in series; the driving circuit comprises an initialization phase, a data writing phase and a light emitting phase, and the driving method comprises the following steps:

in the initialization stage, transmitting a reference voltage signal to the first node to enable the driving transistor to be conducted;

in the data writing phase, the first node and the third node are connected, a signal of a data signal end is transmitted to the second node, a signal of the second node is transmitted to the third node through the driving transistor, and a signal of the third node is transmitted to the first node; the storage module is used for realizing the charging of the first node and maintaining the voltage of the first node;

in the light emitting phase, the first node and the third node are disconnected, the light emitting control module is turned on, a signal of the first power signal terminal is transmitted to the second node, and the driving transistor generates a driving current for driving the light emitting element to emit light, so that the light emitting element emits light;

and in the same time frame, the two sub-transistors are simultaneously turned on or simultaneously turned off under the control of the control signal.

In a third aspect, the present application further provides a display device including the pixel driving circuit provided in the present application.

Compared with the prior art, the pixel driving circuit, the driving method thereof and the display device provided by the invention at least realize the following beneficial effects:

in the pixel driving circuit, the driving method thereof and the display device provided by the embodiment of the application, the pixel driving circuit includes a driving transistor and a switching transistor module, wherein a gate of the driving transistor is connected to a first node, and a first end of the switching transistor module is also connected to the first node, that is, electrically connected to the gate of the driving transistor. In particular, at least part of the switching transistor module comprises two sub-transistors connected in series, the polarities of the two sub-transistors being opposite, and the gates of the two sub-transistors are turned on or off simultaneously under the control of the control signal in the same time frame. When the two sub-transistors are turned on and off, the voltages of the gates of the two sub-transistors are changed, and even after the two sub-transistors are turned off, the two sub-transistors have parasitic capacitance; because the polarities of the two sub-transistors are opposite, when the two sub-transistors are both turned off, the parasitic capacitance applied to the first node by one of the sub-transistors is a positive value, and is assumed to be a first parasitic capacitance value; the parasitic capacitance applied to the first node by the other sub-transistor is a negative value, which is assumed to be a second parasitic capacitance value. After the two sub-transistors are connected in series, the parasitic capacitance acting on the first node becomes the sum of the first parasitic capacitance and the second parasitic capacitance, and the sum is assumed to be the third parasitic capacitance. Since the polarities of the two sub-transistors are opposite, the absolute value of the third parasitic capacitance will be smaller than the first parasitic capacitance, and will also be smaller than the absolute value of the second parasitic capacitance, that is, the third parasitic capacitance will have less influence on the first node than the first parasitic capacitance and the second parasitic capacitance. Therefore, the mode that two sub-transistors with opposite polarities are connected in series is adopted, the influence of parasitic capacitance on the grid electrode of the driving transistor in the process of conducting to stopping of the switching transistor in the prior art is weakened, the driving current generated by the driving transistor is closer to the preset driving current, and therefore the display brightness uniformity of the display device is favorably improved, and the display effect is favorably improved.

Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic diagram of a frame structure of a pixel driving circuit according to the present invention;

FIG. 2 is a schematic diagram of a frame structure of another pixel driving circuit provided in the present invention;

FIG. 3 is a schematic diagram of a frame structure of a pixel driving circuit according to another embodiment of the present invention;

FIG. 4 is a schematic diagram of a frame structure of a pixel driving circuit according to still another embodiment of the present invention;

FIG. 5 is a schematic diagram of a frame structure of a pixel driving circuit according to still another embodiment of the present invention;

FIG. 6 is a schematic diagram of a frame structure of a pixel driving circuit according to still another embodiment of the present invention;

FIG. 7 is a circuit diagram of a pixel driving circuit according to the present invention;

FIG. 8 is a circuit diagram of another pixel driving circuit provided in the present invention;

fig. 9 is a driving timing diagram of the pixel driving circuit provided in the present invention;

fig. 10 is a schematic diagram of a working flow of a driving method of a pixel driving circuit provided by the present invention;

fig. 11 is a schematic plan view of a display device according to the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

Fig. 1 is a schematic diagram of a frame structure of a pixel driving circuit provided in the present invention, and referring to fig. 1, the present embodiment provides a pixel driving circuit, including:

a first power signal terminal PVDD and a second power signal terminal PVEE;

a driving transistor M0, a gate of the driving transistor M0 being connected to the first node N1, a first pole of the driving transistor M0 being connected to the second node N2, a second pole of the driving transistor M0 being connected to the third node N3;

a light emitting element D1, wherein the anode of the light emitting element D1 is connected to the fourth node N4, and the cathode is electrically connected to the second power signal terminal PVEE;

a light emission control module 20, the driving transistor M0, and the light emitting element D1 being connected in series between a first power signal terminal PVDD and a second power signal terminal PVEE;

a memory module 30, a first terminal of the memory module 30 being electrically connected to the first power signal terminal PVDD, a second terminal of the memory module 30 being electrically connected to the first node N1;

at least one switching transistor module 40, wherein a first terminal of the switching transistor module 40 is connected to the first node N1, at least a part of the switching transistor module 40 includes two sub-transistors 41 connected in series, the polarities of the two sub-transistors 41 are opposite, and the gates of the two sub-transistors 41 are turned on or off simultaneously under the control of the control signal in the same time frame.

It should be noted that, in the present application, two sub-transistors 41 are connected in series, which means that in the two sub-transistors 41, the first pole of one sub-transistor 41 is electrically connected to the first pole or the second pole of the other sub-transistor 41, so that the first pole and the second pole of the two sub-transistors 41 are connected in series in the same path. The two sub-transistors 41 with opposite polarities in the present application refer to that for the voltages applied to the gates of the two sub-transistors, one of the two sub-transistors is turned on when the gate receives a high level, and the other is turned on when the gate receives a low level, in other words, the polarities of the turn-on voltages of the two sub-transistors are opposite to that of the reference voltage, for example, assuming that the reference voltage is V0, the turn-on voltage of one sub-transistor 41 is V0+ V1, and the turn-on voltage of the other sub-transistor 41 may be V0-V1. It should be noted that, in this embodiment, the transistor may be a thin film transistor, and in the first electrode and the second electrode of the transistor in this embodiment, one of the first electrode and the second electrode is a source electrode of the transistor, and the other is a drain electrode of the transistor.

Specifically, in the initialization phase, a reference voltage signal is transmitted to the first node N1, so that the driving transistor M0 is turned on; in the data writing phase, the first node N1 is connected to the third node N3, the signal of the data signal terminal Vdata is transmitted to the second node N2, the signal of the second node N2 is transmitted to the third node N3 through the driving transistor M0, and the signal of the third node N3 is transmitted to the first node N1; the storage module 30 is used for charging the first node N1 and maintaining the voltage of the first node N1; in the lighting phase, the first node N1 and the third node N3 are disconnected, the lighting control module 20 is turned on, the signal of the first power signal terminal PVDD is transmitted to the second node N2, the driving transistor M0 generates a driving current for driving the lighting element D1 to light, and the driving current is transmitted to the anode of the lighting element D1 through the lighting control module 20, so that the lighting element D1 lights.

Wherein, in the same time frame, the two sub-transistors 41 are turned on or off simultaneously under the control of the control signal. When the two sub-transistors 41 are turned on and off, the voltages of the gates thereof change, and even after the two sub-transistors are turned off, parasitic capacitances still exist in the two sub-transistors 41, and when the sub-transistors are turned on and off, the voltages of the gates thereof change, and after the sub-transistors are turned off, capacitances formed between the gates and the sources, and between the gates and the drains thereof are the parasitic capacitances. Since the source or the drain of the sub-transistor is electrically connected to the first node N1 directly or indirectly, the parasitic capacitance is applied to the first node. In addition, for two sub-transistors with opposite polarities, one of the transistors is turned on when the grid electrode receives high level, is turned off when the grid electrode receives low level signals, and jumps from high level to low level from turning on to turning off; the other sub-transistor is turned on when the grid electrode receives a low-level signal, is turned off when the grid electrode receives a high-level signal, and jumps from the low level to the high level from the on state to the off state; therefore, the parasitic capacitances of the two sub-transistors with opposite polarities applied to the first node are positive and negative. Since the polarities of the two sub-transistors 41 are opposite, when the two sub-transistors 41 are both turned off, the parasitic capacitance applied to the first node N1 by one of the sub-transistors 41 is a positive value, which is assumed to be a first parasitic capacitance value; the parasitic capacitance of the other sub-transistor 41 acting on the first node N1 is a negative value, which is assumed to be a second parasitic capacitance value. When the two sub-transistors 41 are connected in series, the parasitic capacitance applied to the first node N1 becomes the sum of the first parasitic capacitance and the second parasitic capacitance, which is assumed to be the third parasitic capacitance. Since the polarities of the two sub-transistors 41 are opposite, the parasitic capacitances that the two sub-transistors may generate at the first node N1 can cancel each other out, so the absolute value of the third parasitic capacitance will be smaller than the first parasitic capacitance, and will also be smaller than the absolute value of the second parasitic capacitance, that is, the third parasitic capacitance will have less influence on the first node N1 than the first parasitic capacitance and the second parasitic capacitance. Therefore, in the present application, the two sub-transistors 41 with opposite polarities are connected in series, so that the influence of the parasitic capacitance on the gate of the driving transistor M0 in the process from the on state to the off state of the sub-transistors is reduced, and the driving current generated by the driving transistor M0 is closer to the preset driving current, thereby facilitating the improvement of the display brightness uniformity of the display device, and further facilitating the improvement of the display effect.

Optionally, in the pixel driving circuit provided by the present application, the two sub-transistors 41 connected in series include a P-type transistor and an N-type transistor, where the P-type transistor is a PMOS transistor, and the N-type transistor is an NMOS transistor or an oxide thin film transistor. The P-type transistor is generally turned on by a low-level signal and turned off by a high-level signal, and the N-type transistor is generally turned on by a high-level signal and turned off by a low-level signal. When the two sub-transistors 41 are turned off from the on state, the parasitic capacitance applied to the first node N1 by the P-type transistor is a positive capacitance, the parasitic capacitance applied to the first node N1 by the N-type transistor is a negative capacitance, and the parasitic capacitance applied to the first node N1 is reduced by the positive capacitance and the negative capacitance, so that the influence of the sub-transistors 41 on the gate voltage of the driving transistor M0 when turned on and off is reduced, and the driving current generated by the driving transistor M0 is closer to the preset driving current. In an ideal state, the sum of the positive capacitance value and the negative capacitance value is 0, that is, the influence of the parasitic capacitance of the sub-transistor 41 on the gate voltage of the driving transistor M0 when the sub-transistor is turned on and turned off can be eliminated, so that the driving current generated by the driving transistor M0 is equal to the preset driving current, which is more beneficial to improving the uniformity of the display brightness of the display device. In addition, when the N-type transistor is selected as the oxide thin film transistor, the oxide thin film transistor has the advantage of small leakage current and is favorable for realizing low-frequency driving, so that the load capacity of a chip in the display device can be reduced when the N-type transistor is selected as the oxide thin film transistor.

Fig. 1 shows a connection relationship of two sub-transistors 41 connected in series, and optionally, in this embodiment, the two sub-transistors 41 are an N-type transistor and a P-type transistor, respectively, and the P-type transistor is connected in series between the N-type transistor and the first node N1. At this time, one electrode of the P-type transistor is directly electrically connected to the first node N1, when the P-type transistor and the N-type transistor are turned on to off, the parasitic capacitance value of the P-type transistor acting on the first node N1 is positive, the parasitic capacitance value of the N-type node acting on the first node N1 is negative, and the parasitic capacitance value superposed by the P-type transistor and the N-type transistor is smaller than any one of the two values, so that the manner of connecting the P-type transistor and the N-type transistor in series is favorable for reducing the influence of the parasitic capacitance on the gate voltage of the driving transistor M0 when the transistors are turned on to off, so that the driving current generated by the driving transistor M0 is closer to the preset driving current, thereby being favorable for improving the display luminance uniformity of the display device and improving.

Fig. 2 is a schematic diagram of a frame structure of another pixel driving circuit provided in the present invention, and this embodiment shows another connection relationship of two sub-transistors 41 connected in series. Alternatively, in this embodiment, the two sub-transistors 41 are a P-type transistor and an N-type transistor, respectively, and the N-type transistor is connected in series between the P-type transistor and the first node N1. At this time, one electrode of the N-type transistor is directly electrically connected to the first node N1, when the N-type transistor and the P-type transistor are turned on to off, the parasitic capacitance value of the N-type node acting on the first node N1 is negative, the parasitic capacitance value of the P-type transistor acting on the first node N1 is positive, and the parasitic capacitance value superposed by the two is smaller than any one of the two, so that the manner of connecting the N-type transistor and the P-type transistor in series is favorable for reducing the influence of the parasitic capacitance on the gate voltage of the driving transistor M0 when the transistors are turned on to off, so that the driving current generated by the driving transistor M0 is closer to the preset driving current, thereby being favorable for improving the display luminance uniformity of the display device and improving the display effect of the display device.

In addition, when the N-type transistor is connected in series between the P-type transistor and the first node N1 in the two sub-transistors 41 connected in series, the N-type transistor is directly connected to the first node N1, and when the N-type transistor is turned on and off, the signal at the gate thereof changes from high to low, and the signal applied to the N1 node also changes to a low signal. When the driving transistor M0 is a P-type transistor, when the two series-connected sub-transistors 41 are turned off, the driving transistor M0 is in an on state, and even if the N-type transistor in the series-connected sub-transistors generates a low level signal acting on the node N1, the low level signal does not turn off the driving transistor (when the driving transistor M0 is a P-type transistor, it can only be turned off when its gate receives a high level signal), and the driving transistor M0 can be kept in an on state, thereby effectively avoiding the possibility that the driving transistor M0 is turned off due to the influence of the level signal of the node N1.

Fig. 3 is a schematic diagram of a frame structure of another pixel driving circuit provided by the present invention, and this embodiment further explains a connection relationship between an inverter 43 and two sub-transistors 41 when the switching transistor includes the inverter 43.

Optionally, the switching transistor module 40 further includes an inverter 43, and an input terminal of the inverter 43 is connected to the seventh control terminal S_1-p(ii) a One of the two sub-transistors 41 has its gate connected to the seventh control terminal S_1-pAnd the gate of the other is connected to the output terminal of the inverter 43.

Specifically, since the polarities of the two sub-transistors 41 in the switching transistor module 40 are opposite, if it is required that the two sub-transistors are turned on or off simultaneously, one of the control signals provided to the two sub-transistors is a high level signal, and the other is a low level signal. In this embodiment, the gate of one of the sub-transistors 41 receives the first seven control terminal S_1-pThe transmitted control signal, and the seventh control terminal S_1-pThe transmitted control signal is also inputted to the inverter 43, and the inverter 43 performs an inversion operation, and another control signal having a phase opposite to that of the control signal is inputted to the gate of the other sub-transistor 41, thereby realizing simultaneous turning-on or simultaneous turning-off of the two sub-transistors 41. Thus, the gates of the two sub-transistors 41 do not need to be connected to different control terminals, and two kinds of control can be realized by using one control terminalAnd the output of the signals is favorable for reducing the number of control terminals on the chip in the display device and saving the production cost of the chip.

Fig. 4 is a schematic diagram of a frame structure of another pixel driving circuit provided by the present invention, and this embodiment further explains the specific configuration and connection relationship of the initialization module 50 when the switching transistor module 40 includes the initialization module 50.

Optionally, the switch transistor module 40 includes an initialization module 50, a first terminal of the initialization module 50 is connected to the first node N1, a second terminal of the initialization module is connected to a reference voltage terminal Vref1, and the reference voltage terminal Vref1 is configured to provide a reference voltage signal to the first node N1, so that the driving transistor M0 is turned on or off; the initialization module 50 includes a first sub-transistor M1 and a second sub-transistor M2, wherein a gate of the first sub-transistor M1 is connected to the first control terminal S_1-p(multiplexed with the seven control terminals described above), the gate of the second sub-transistor M2 is connected to the second control terminal S_1-n(ii) a Within the same time frame, the first control terminal S_1-pA control signal to the first sub-transistor M1, a second control terminal S_1-nA control signal is sent to the second sub-transistor M2 to turn on the first sub-transistor M1 and the second sub-transistor M2 at the same time or turn off at the same time.

It should be noted that, in this embodiment, only the first sub-transistor M1 is a P-type transistor and the second sub-transistor M2 is an N-type transistor, in some other embodiments of the present application, the first sub-transistor M1 may also be an N-type transistor, and the second sub-transistor M2 may also be a P-type transistor, which is not specifically limited in this application.

Specifically, in the initialization phase, the first control terminal S_1-pSending a low-level control signal to the gate of the first sub-transistor M1 to turn on the first sub-transistor M1; at the same time, the second control terminal S_1-nA high level control signal is sent to the gate of the second sub-transistor M2, turning on the second sub-transistor M2. The signal of the reference voltage terminal Vref1 is transmitted to the first node N1 through the first sub-transistor M1 and the second sub-transistor M2, and further transmitted to the gate of the driving transistor M0, so that the driving transistor M0 is turned on. In the data writing stage, the first control terminalS_1-pA high-level control signal is sent to the gate of the first sub-transistor M1, and the second control terminal S_1-nA low-level control signal is transmitted to the gate of the second transistor so that the first sub-transistor M1 and the second sub-transistor M2 are simultaneously turned off. When the first sub-transistor M1 and the second sub-transistor M0 are turned off, due to the existence of the parasitic capacitance, at this time, the parasitic capacitance of the first sub-transistor M1 acting on the first node N1 is a positive value, the parasitic capacitance of the second sub-transistor M2 acting on the first node N1 is a negative value, and the influence of the parasitic capacitance value on the first node N1 after the first sub-transistor M1 and the second sub-transistor M2 are overlapped is reduced, so that the influence on the gate voltage of the driving transistor M0 is reduced, and the driving current generated by the driving transistor M0 is closer to the preset driving current value, thereby being beneficial to improving the uniformity of the display brightness of the display device and improving the display effect of the display device.

Fig. 5 is a schematic diagram of a frame structure of another pixel driving circuit provided by the present invention, and this embodiment further explains the specific configuration and connection relationship of the first data writing module 61 when the switching transistor module 40 includes the first data writing module 61.

Optionally, the switch transistor module 40 includes a first data writing module 61, a first terminal of the first data writing module 61 is connected to the first node N1, a second terminal of the first data writing module 61 is connected to the third node N3, and the first data writing module 61 is configured to transmit a signal of the third node N3 to the first node N1; the first data writing module 61 includes a third sub-transistor M3 and a fourth sub-transistor M4, wherein a gate of the third sub-transistor M3 is connected to a third control terminal S_2-pThe gate of the fourth sub-transistor M4 is connected to the fourth control terminal S_2-n(ii) a Within the same time frame, the third control terminal S_2-pA fourth control terminal S for sending a control signal to the third sub-transistor M3_2-nA control signal is sent to the fourth sub-transistor M4 to turn on the third sub-transistor M3 and the fourth sub-transistor M4 at the same time or turn off at the same time.

It should be noted that, in this embodiment, only the third sub-transistor M3 is a P-type transistor and the fourth sub-transistor M4 is an N-type transistor, in some other embodiments of the present application, the third sub-transistor M3 may also be an N-type transistor, and the fourth sub-transistor M4 may also be a P-type transistor, which is not specifically limited in this application.

Specifically, in the data writing stage, the third control terminal S_2-pSending a low-level control signal to the gate of the third sub-transistor M3 to turn on the third sub-transistor M3; meanwhile, the fourth control terminal S_2-nA high level control signal is transmitted to the gate of the third sub-transistor M3, turning on the fourth sub-transistor M4. The signal of the data signal terminal Vdata is transmitted to the second node N2, the signal of the second node N2 is transmitted to the third node N3 through the driving transistor M0, and the signal of the third node N3 is transmitted to the first node N1 through the third sub-transistor M3 and the fourth sub-transistor M4. In the light emitting stage, the third control terminal S_2-pA high-level control signal is sent to the gate of the third sub-transistor M3, and a fourth control terminal S_2-nA low level control signal is transmitted to the gate of the third sub-transistor M3, turning off the third sub-transistor M3 and the fourth sub-transistor M4 at the same time. When the third sub-transistor M3 and the fourth sub-transistor M4 are turned on and off, the gate voltages of the third sub-transistor M3 and the fourth sub-transistor M4 are changed, and even after the third sub-transistor M3 and the fourth sub-transistor M4 are turned off, parasitic capacitances of the third sub-transistor M3 and the fourth sub-transistor M4 are present. Because the polarities of the third sub-transistor M3 and the fourth sub-transistor M4 are opposite, the parasitic capacitance of the third sub-transistor M3 acting on the first node N1 is a positive value, the parasitic capacitance of the fourth sub-transistor M4 acting on the first node N1 is a negative value, and the influence of the superimposed parasitic capacitance values on the first node N1 is reduced, so that the influence on the gate voltage of the driving transistor M0 is reduced, and the driving current generated by the driving transistor M0 is closer to the preset driving current value, thereby being beneficial to improving the uniformity of the display brightness of the display device and improving the display effect of the display device.

With reference to fig. 5, when the initialization module 50 and the first data writing module 61 are both configured with two sub-transistors with opposite polarities, it is beneficial to reduce the influence of the parasitic capacitances of the first sub-transistor M1 and the second sub-transistor M2 in the initialization module 50 on the gate voltage of the driving transistor M0 when the initialization stage is shifted to the data writing stage, and at the same time, it is beneficial to reduce the influence of the parasitic capacitances of the third sub-transistor M3 and the fourth sub-transistor M4 in the first data writing module 61 on the gate voltage of the driving transistor M0 when the data writing stage is shifted to the light emitting stage, so that the driving current finally generated by the driving transistor M0 is closer to the preset driving current, which is further beneficial to improve the display luminance uniformity of the display device and further beneficial to improve the display effect of the display device.

With continued reference to fig. 5, in the first data writing module 61 in this embodiment, one pole of the fourth sub-transistor M4 is directly connected to the first node N1, since the fourth sub-transistor M4 is an N-type transistor, when the fourth sub-transistor M4 is turned from on to off (e.g., during the data writing period T2 of the timing sequence in this application), the signal at the gate thereof changes from high level to low level, and the signal applied to the node N1 also changes to low level or tends to change to a lower potential. Since the fourth transistor M4 is turned from on to off, no more Vref signal is input to the first node N1 through the fourth transistor M4. When the fourth transistor M4 is turned on and off, when the driving transistor M0 is a P-type transistor and the fourth sub-transistor M4 is turned off, the driving transistor M0 is turned on, and even if the fourth transistor M4 generates a low-level signal acting on the N1 node, the low-level signal does not turn off the driving transistor M0 (when the driving transistor M0 is a P-type transistor, it can be turned off only when the gate thereof receives a high-level signal), so that the driving transistor M0 can be kept in the on state, and the driving transistor M0 is effectively prevented from being turned off due to the influence of the level signal of the N1 node.

In addition, with continued reference to fig. 5, in the first data writing module 61 of this embodiment, a pole of the third sub-transistor M3 is directly connected to the third node N3, i.e., directly connected to a pole of the driving transistor M0. Because the third sub-transistor M3 is a P-type transistor, when the driving transistor M0 is also a P-type transistor, in the layout design and the actual production process, the active layers of the two P-type transistors can be electrically connected in the same film structure, and the connection through a via hole is not needed, so that the layout design is facilitated, the production process is simplified, and the production efficiency is improved. The reason why the active layers of the two P-type transistors need to be connected is that, in general, the active layer of the P-type transistor is a polysilicon layer, the polysilicon layer forms a source region and a drain region by doping impurity ions, the region between the source region and the drain region is a channel region, the source region and the drain region respectively form a source and a drain of the transistor, and the active layers of the two P-type transistors are connected, in fact, the source or the drain of one of the transistors is connected to the source or the drain of the other P-type transistor, that is, the source or the drain of the third sub-transistor M3 transistor is electrically connected to the source or the drain of the driving transistor M0.

Fig. 6 is a schematic diagram of a frame structure of still another pixel driving circuit provided by the present invention, and this embodiment further illustrates a specific connection relationship between the second data writing module 62 and the compensation capacitor C0 when the switching transistor module 40 includes the second data writing module 62 and the compensation capacitor C0.

Optionally, the switch transistor module 40 includes a second data writing module 62, a first terminal of the second data writing module 62 is connected to the first node N1, a second terminal of the second data writing module 62 is connected to the third node N3, and the second data writing module 62 is configured to transmit a signal of the third node N3 to the first node N1; the second data writing module 62 includes a fifth transistor M5, wherein the gate of the fifth transistor M5 is connected to a fifth control terminal (the fifth control terminal can be used to multiplex the fourth control terminal S)_2-n) (ii) a The pixel driving circuit further includes a compensation capacitor C0, a first pole of the compensation capacitor C0 is connected to the first node N1, a second pole of the compensation capacitor C0 is connected to a sixth control terminal (the fifth control terminal can multiplex the fourth control terminal S)_2-P) (ii) a In the same time frame, the polarity of the compensation capacitor C0 is opposite to the polarity of the capacitance formed between the gate and the first pole of the fifth transistor M5.

It should be noted that, this embodiment is only described by taking the fifth transistor M5 included in the second data writing module 62 as an N-type transistor as an example, in some other embodiments of the present application, the fifth transistor M5 may also be a P-type transistor, which is not specifically limited in this application.

Specifically, in the data writing stage, the fifth control terminal S_2-nA high level control signal is transmitted to the gate of the fifth transistor M5, turning on the fifth transistor M5. The signal of the data signal terminal Vdata is transmitted to the second node N2, the signal of the second node N2 is transmitted to the third node N3 through the driving transistor M0, and the signal of the third node N3 is transmitted to the first node N1 through the fifth transistor M5. In the light emitting stage, the fifth control terminal S_2-nSending a low-level control signal to the gate of the fifth sub-transistor 41 to turn off the fifth transistor M5, so that a negative parasitic capacitance is formed to act on the first node N1 when the fifth transistor M5 is turned from on to off; at this time, the sixth control terminal S_2-pAnd sending a high-level control signal to the second pole of the compensation capacitor, so that the compensation capacitor forms a positive capacitance value to be applied to the first node N1, the influence of the positive capacitance value and the negative parasitic capacitance value on the first node N1 is reduced after the positive capacitance value and the negative parasitic capacitance value are superposed, and the influence on the gate voltage of the driving transistor M0 is reduced, so that the driving current generated by the driving transistor M0 is closer to a preset driving current value, and therefore, the display brightness uniformity of the display device is favorably improved, and the display effect of the display device is favorably improved.

Fig. 7 is a circuit schematic diagram of a pixel driving circuit provided by the present invention, and this embodiment further illustrates an electrical connection relationship between the sixth transistor M6 and the seventh transistor M7 when the light emission control module 20 includes the sixth transistor M6 and the seventh transistor M7.

Optionally, the light emitting control module 20 includes a sixth transistor M6 and a seventh transistor M7, a gate of the sixth transistor M6 is electrically connected to the light emitting control signal end Emit through the first light emitting control line 21, a gate of the seventh transistor M7 is electrically connected to the light emitting control signal end Emit through the second light emitting control line 22, and the light emitting control signal end Emit is configured to provide a switch control signal to the sixth transistor M6 and the seventh transistor M7; a first pole of the sixth transistor M6 is connected to the first power signal terminal PVDD, and a second pole is connected to the second node N2; the seventh transistor M7 has a first pole connected to the third node N3 and a second pole connected to the fourth node N4.

It should be noted that, in this embodiment, only the sixth transistor M6 and the seventh transistor M7 are both P-type transistors for illustration, in some other embodiments of the present application, the sixth transistor M6 and the seventh transistor M7 may also be both N-type transistors, and when the types of the sixth transistor M6 and the seventh transistor M7 are set to be the same, they may be connected to the same emission control signal end Emit through the emission control line, which is beneficial to reducing the number of signal ends in a chip of the display device, and thus beneficial to saving the production cost of the chip.

Specifically, in the light emitting phase, the light emission control signal terminal Emit inputs a low level control signal to the gates of the sixth transistor M6 and the seventh transistor M7, the sixth transistor M6 and the seventh transistor M7 are turned on, the signal of the first power supply signal terminal PVDD is transmitted to the second node N2 through the sixth transistor M6, the driving transistor M0 forms a driving current, the driving current is transmitted to the anode of the organic light emitting element D1 through the seventh transistor M7, and the organic light emitting element D1 emits light according to the driving current, thereby implementing the display function of the display device.

With continued reference to fig. 7, fig. 7 further illustrates the structure and connection relationship of the third data writing module 63 when the pixel driving circuit includes the third data writing module 63.

Optionally, the pixel driving circuit further includes a third data writing module 63, the third data writing module 63 includes an eighth transistor M8, a gate of the eighth transistor M8 and an eighth control terminal (multiplexing the third control terminal S mentioned above)_2-p) Electrically, a first pole of the eighth transistor M8 is electrically connected to a data signal terminal Vdata, a second pole of the eighth transistor M8 is electrically connected to the second node N2, and the data signal terminal Vdata is used for providing a data signal to the second node N2.

It should be noted that, this embodiment is only described by taking the eighth transistor M8 in the third data writing module 63 as a P-type transistor as an example, in some other embodiments of the present application, the eighth transistor M8 may also be an N-type transistor, which is not specifically limited in this application.

Specifically, in the data writing stage, the eighth control terminal S_2-pA low level control signal is input to the gate of the eighth transistor M8, the eighth transistor M8 is turned on, the third data writing module 63 transmits the signal of the data signal terminal Vdata to the second node N2 through the eighth transistor M8, the signal of the second node N2 is transmitted to the third node N3 through the driving transistor M0, and the potential of the third node N3 is transmitted to the first node N1 through the first data writing module 61 or the second data writing module 62. The eighth control terminal in this embodiment and the third control terminal S_2-pMultiplexing is beneficial to reducing the number of control terminals on a chip in the display device, thereby being beneficial to reducing the production cost of the chip. It should be noted that, when the eighth transistor M8 is an N-type transistor, the eighth control terminal can multiplex the fourth control terminal S_2-nTo reduce the number of control terminals on a chip in the display device.

Fig. 8 is a circuit diagram of another pixel driving circuit provided in the present invention, and this embodiment further explains the specific configuration and electrical connection relationship of the reset module 70 when the pixel driving circuit includes the reset module 70.

Optionally, the pixel driving circuit further includes a reset module 70, wherein the reset module 70 includes a ninth transistor M9, a gate of the ninth transistor M9 and a ninth control terminal (multiplexing the third control terminal S mentioned above)_2-p) Electrically, a first pole of the ninth transistor M9 is electrically connected to a reset voltage terminal Vref2, a second pole of the ninth transistor M9 is electrically connected to the fourth node N4, and the reset voltage terminal Vref2 is used to provide a reset signal to the fourth node N4.

It should be noted that, this embodiment only takes the ninth transistor M9 in the reset module 70 as a P-type transistor as an example, and in some other embodiments of the present application, the ninth transistor M9 may also be an N-type transistor, which is not specifically limited in this application. When the ninth transistor M9 is an N-type transistor, the ninth control terminal can multiplex the fourth control terminal S_2-nTo reduce the number of control terminals on a chip in the display device.

Before the light-emitting phase, e.g. in the data writing phase, a ninth control terminal S_2-pA low-level signal is input to the gate of the ninth transistor M9, the ninth transistor M9 is turned on,the signal of the reset voltage terminal Vref2 is transmitted to the fourth node N4 through the ninth transistor M9, so that the reset of the fourth node N4 is realized, and the organic light emitting element D1 is effectively prevented from emitting light in the data writing phase. At this time, the ninth control terminal S_2-pReusable third control terminal S_2-pSo that the fourth node N4 is reset during the data write phase. A ninth control terminal S_2-pAnd a third control terminal S_2-pThe multiplexing mode is favorable for reducing the number of control ends on the chip of the display device, thereby being favorable for saving the production cost of the chip.

The driving sequence of the pixel driving circuit provided by the present application will be described with reference to fig. 8 and 9, wherein fig. 9 is a driving timing chart of the pixel driving circuit provided by the present invention. Fig. 8 only illustrates the driving transistor M0, the first sub-transistor M1, the third sub-transistor M3, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 in the pixel driving circuit as P-type transistors, and the second sub-transistor M2 and the fourth sub-transistor M4 are N-type transistors. In some optional embodiments, the driving transistor M0, the first sub transistor M1, the third sub transistor M3, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 may also be N-type transistors, and the second sub transistor M2 and the fourth sub transistor M4 are P-type transistors, at this time, corresponding driving timings in this embodiment will also change accordingly, which is not described herein.

In the embodiment shown in fig. 8, the memory module 30 is embodied as a first capacitor C1. A third control terminal electrically connected to the gate of the third sub-transistor M3, an eighth control terminal electrically connected to the gate of the eighth transistor M8, and a ninth control terminal electrically connected to the ninth transistor M9 share the same control terminal S_2-PTherefore, the number of control terminals on the chip of the display device is reduced, and the production cost of the chip is saved.

In the initialization stage T1, the first control terminal S_1-pSending a low-level control signal to the gate of the first sub-transistor M1 to turn on the first sub-transistor M1; at the same time, the second control terminal S_1-nA high level control signal is sent to the gate of the second sub-transistor M2 to enableThe second sub-transistor M2 is turned on. The signal of the reference voltage terminal Vref1 is transmitted to the first node N1 through the first sub-transistor M1 and the second sub-transistor M2, and further transmitted to the gate of the driving transistor M0, so that the driving transistor M0 is turned on.

In the data writing phase T2, the first control terminal S_1-pA high-level control signal is sent to the gate of the first sub-transistor M1, and the second control terminal S_1-nSending a low-level control signal to the gate of the second sub-transistor M2 so that the first sub-transistor M1 and the second sub-transistor M2 are turned off at the same time; control terminal S_2-pA low level control signal to the eighth transistor M8, a low level control signal to the ninth transistor M9, and a low level control signal to the third sub-transistor M3, while controlling the terminal S_2-nTransmitting a high-level control signal to the fourth sub-transistor M4 to turn on the eighth transistor M8, the ninth transistor M9, the third sub-transistor M3, and the fourth sub-transistor M4, transmitting a signal of the data signal terminal Vdata to the second node N2 through the eighth transistor M8, transmitting a signal of the second node N2 to the third node N3 through the driving transistor M0, and transmitting a signal of the third node N3 to the first node N1 through the third sub-transistor M3 and the fourth sub-transistor M4; the first capacitor C1 charges the first node N1 and maintains the voltage of the first node N1; the reset voltage terminal Vref2 provides a reset signal to the fourth node N4 through the ninth transistor M9;

in the lighting period T3, the control terminal S_2-pA high level control signal to the eighth transistor M8, a high level control signal to the ninth transistor M9, and a high level control signal to the third sub-transistor M3, while controlling the terminal S_2-nSending a low-level control signal to the fourth sub-transistor M4 to turn off the eighth transistor M8, the ninth transistor M9, the third sub-transistor M3, and the fourth sub-transistor M4; the emission control signal terminal Emit transmits a low level control signal to the sixth transistor M6 and the seventh transistor M7 to turn on the sixth transistor M6 and the seventh transistor M7, the signal of the first power signal terminal PVDD is transmitted to the second node N2 through the sixth transistor M6, the driving transistor M0 generates a driving current, the driving current is transmitted to the anode of the organic light emitting element D1 through the seventh transistor M7, and the organic light emitting element D1 emits lightThe element D1 emits light in accordance with the drive current.

In the initialization period T1, the first sub-transistor M1 and the second sub-transistor M2 are turned on simultaneously; in the data writing phase T2, the first sub-transistor M1 and the second sub-transistor M2 are simultaneously turned off. In the process from turning on to turning off, the gate voltages of the first sub-transistor M1 and the second sub-transistor M2 both change, even after turning off, parasitic capacitances exist in the first sub-transistor M1 and the second sub-transistor M2, and the parasitic capacitance of the first sub-transistor M1 acting on the first node N1 is a positive value, which is assumed to be a first parasitic capacitance; the parasitic capacitance of the second sub-transistor M2 acting on the first node N1 is a negative value, which is assumed to be a second parasitic capacitance; the parasitic capacitance after the first parasitic capacitance and the second parasitic capacitance are superposed and act on the first node N1 is a third parasitic capacitance, an absolute value of the third parasitic capacitance is smaller than the first parasitic capacitance and is also smaller than an absolute value of the second parasitic capacitance, and compared with the first parasitic capacitance and the second parasitic capacitance, the influence of the third parasitic capacitance on the first node N1 is greatly reduced, so that the influence of the parasitic capacitance on the gate of the driving transistor M0 in the process from the on state to the off state of the first sub-transistor M1 and the second sub-transistor M2 is weakened, and the driving current generated by the driving transistor M0 is closer to a preset driving current, so that the display luminance uniformity of the display device is favorably improved, and the display effect is favorably improved.

Similarly, in the data writing phase T2, the third sub-transistor M3 and the fourth sub-transistor M4 are turned on simultaneously; in the light emitting period T3, the third sub-transistor M3 and the fourth sub-transistor M4 are simultaneously turned off. After the third sub-transistor M3 and the fourth sub-transistor M4 are turned off, due to the existence of the parasitic capacitance, the parasitic capacitance acting on the first node N1 exists in both the third sub-transistor M3 and the fourth sub-transistor M4, wherein the parasitic capacitance acting on the first node N1 by the third sub-transistor M3 is a positive value, the parasitic capacitance acting on the first node N1 by the fourth sub-transistor M4 is a negative value, and the parasitic capacitance value after the superposition of the two values is reduced, which is also beneficial to reducing the influence of the parasitic capacitance on the gate of the driving transistor M0 in the process from the on state to the off state of the third sub-transistor M3 and the fourth sub-transistor M4, so that the driving current generated by the driving transistor M0 is closer to the preset driving current, thereby being beneficial to improving the uniformity of the display luminance of the display device and further being beneficial to improving the display effect.

Based on the same inventive concept, the present application further provides a driving method of a pixel driving circuit, and fig. 10 is a schematic workflow diagram of the driving method of the pixel driving circuit provided by the present invention, the driving method is used for driving the pixel driving circuit in the above embodiment, please refer to fig. 1, the driving circuit includes a first power signal terminal PVDD, a second power signal terminal PVEE, a driving transistor M0, a light emitting element D1, a light emitting control module 20, and at least one switching transistor module 40, a first end of the switching transistor module 40 is connected to a first node N1, and at least a part of the switching transistor module 40 includes two sub-transistors 41 connected in series; the driving circuit comprises an initialization stage, a data writing stage and a light emitting stage, and the driving method comprises the following steps:

in the initialization phase, a reference voltage signal is transmitted to the first node N1, so that the driving transistor M0 is turned on;

in the data writing phase, the first node N1 is connected to the third node N3, the signal of the data signal terminal Vdata is transmitted to the second node N2, the signal of the second node N2 is transmitted to the third node N3 through the driving transistor M0, and the signal of the third node N3 is transmitted to the first node N1; the storage module 30 is used for charging the first node N1 and maintaining the voltage of the first node N1;

in the light emitting phase, the first node N1 and the third node N3 are disconnected, the light emitting control module 20 is turned on, the signal of the first power signal terminal PVDD is transmitted to the second node N2, and the driving transistor M0 generates a driving current for driving the light emitting element D1 to emit light, so that the light emitting element D1 emits light;

wherein, in the same time frame, the two sub-transistors 41 are turned on or off simultaneously under the control of the control signal.

Specifically, the present embodiment further explains the driving method of the pixel driving circuit in the above embodiments, referring to fig. 1 and fig. 10, the embodiment takes as an example that the switching transistor module 40 including two sub-transistors 41 is connected in series between the reference voltage terminal Vref1 and the first node N1, and the driving method includes at least three steps:

step 101, in the initialization stage, a first control terminal S_1-pAnd a second control terminal S_1-nSending control signals to the two sub-transistors 41 respectively to enable the two sub-transistors 41 to be conducted simultaneously; the reference voltage terminal Vref1 transmits a reference voltage signal to the driving transistor M0 through the two sub-transistors 41, so that the driving transistor M0 is turned on;

step 102, in the data writing stage, the first control terminal S_1-pAnd a second control terminal S_1-nSending control signals to the two sub-transistors 41 respectively so that the two sub-transistors 41 are turned off at the same time; the first node N1 and the third node N3 are connected, a signal of the data signal terminal Vdata is transmitted to the second node N2, a signal of the second node N2 is transmitted to the third node N3 through the driving transistor M0, and a signal of the third node N3 is transmitted to the first node N1; the storage module 30 is used for charging the first node N1 and maintaining the voltage of the first node N1;

in step 103, in the light emitting phase, the first node N1 and the third node N3 are disconnected, the light emitting control module 20 is turned on, the signal of the first power signal terminal PVDD is transmitted to the second node N2, and the driving transistor M0 generates a driving current for driving the light emitting element D1 to emit light, so that the light emitting element D1 emits light.

In the driving method of the pixel driving circuit provided by the present application, in the data writing stage, the two sub-transistors 41 in the switching transistor module 40 are turned off at the same time. Since the two sub-transistors 41 still have parasitic capacitance even after being turned off and the polarities of the two sub-transistors 41 are opposite, when the two sub-transistors 41 are both turned off, the parasitic capacitance applied to the first node N1 by one of the sub-transistors 41 has a positive value, which is assumed to be a first parasitic capacitance value; the parasitic capacitance of the other sub-transistor 41 acting on the first node N1 is a negative value, which is assumed to be a second parasitic capacitance value. When the two sub-transistors 41 are connected in series, the parasitic capacitance applied to the first node N1 becomes the sum of the first parasitic capacitance and the second parasitic capacitance, which is assumed to be the third parasitic capacitance. Since the polarities of the two sub-transistors 41 are opposite, the absolute value of the third parasitic capacitance will be smaller than the first parasitic capacitance, and will also be smaller than the absolute value of the second parasitic capacitance, that is, the third parasitic capacitance will have less influence on the first node N1 than the first parasitic capacitance and the second parasitic capacitance. Therefore, in the present application, the two sub-transistors 41 with opposite polarities are connected in series, so that the influence of the parasitic capacitance of the sub-transistor 41 on the gate of the driving transistor M0 in the process from turning on to turning off is reduced, and the driving current generated by the driving transistor M0 is closer to the preset driving current, thereby facilitating the improvement of the display brightness uniformity of the display device, and further facilitating the improvement of the display effect.

Referring to fig. 4, optionally, the switch transistor module 40 includes an initialization module 50, a first terminal of the initialization module 50 is connected to the first node N1, and a second terminal is connected to the reference voltage terminal Vref 1; the initialization module 50 includes a first sub-transistor M1 and a second sub-transistor M2, wherein a gate of the first sub-transistor M1 is connected to the first control terminal S_1-pThe gate of the second sub-transistor M2 is connected to the second control terminal S_1-n；

In the initialization phase, the first control terminal S_1-pA first turn-on control signal is sent to the first sub-transistor M1, and at the same time, the second control terminal S_1-nSending a second turn-on control signal to the second sub-transistor M2 to turn on the first sub-transistor M1 and the second sub-transistor M2 simultaneously, and the reference voltage terminal Vref1 transmits a reference voltage signal to the first node N1 to turn on the driving transistor M0; in the data writing stage, the first control terminal S_1-pA first off control signal is sent to the first sub-transistor M1, and at the same time, the second control terminal S_1-nThe second off control signal is transmitted to the second sub transistor M2 to simultaneously turn off the first sub transistor M1 and the second sub transistor M2.

Specifically, in the initialization phase, the first control terminal S_1-pSending a low-level control signal to the gate of the first sub-transistor M1 to turn on the first sub-transistor M1; at the same time, the second control terminal S_1-nA high level control signal is sent to the gate of the second sub-transistor M2, turning on the second sub-transistor M2. The signal of the reference voltage terminal Vref1 is transmitted to the first node N1 through the first sub-transistor M1 and the second sub-transistor M2, and further transmitted to the gate of the driving transistor M0, so that the driving transistor M0 is turned on. In the data writing stage, the first control terminal S_1-pA high-level control signal is sent to the gate of the first sub-transistor M1, and the second control terminal S_1-nA low-level control signal is transmitted to the gate of the second sub-transistor M2 such that the first sub-transistor M1 and the second sub-transistor M2 are simultaneously turned off. When the first sub-transistor M1 and the second sub-transistor M0 are turned off, due to the existence of the parasitic capacitance, at this time, the parasitic capacitance of the first sub-transistor M1 acting on the first node N1 is a positive value, the parasitic capacitance of the second sub-transistor M2 acting on the first node N1 is a negative value, and the influence of the parasitic capacitance value on the first node N1 after the first sub-transistor M1 and the second sub-transistor M2 are overlapped is reduced, so that the influence on the gate voltage of the driving transistor M0 is reduced, and the driving current generated by the driving transistor M0 is closer to the preset driving current value, thereby being beneficial to improving the uniformity of the display brightness of the display device and improving the display effect of the display device.

Referring to fig. 5, optionally, the switch transistor module 40 includes a first data writing module 61, a first terminal of the first data writing module 61 is connected to the first node N1, and a second terminal is connected to the third node N3; the first data writing module 61 includes a third sub-transistor M3 and a fourth sub-transistor M4, wherein a gate of the third sub-transistor M3 is connected to a third control terminal S_2-pThe gate of the fourth sub-transistor M4 is connected to the fourth control terminal S_2-n；

In the data writing stage, the third control terminal S_2-pA third turn-on control signal is sent to the third sub-transistor M3, and at the same time, the fourth control terminal S_2-nSending a fourth turn-on control signal to the fourth sub-transistor M4 to make the third sub-transistor M3 and the fourth sub-transistorThe transistor M4 is turned on simultaneously, and the first data writing module 61 transmits the signal of the third node N3 to the first node N1; in the light emitting stage, the third control terminal S_2-pA third cut-off control signal is sent to the third sub-transistor M3, and at the same time, the fourth control terminal S_2-nThe fourth off control signal is transmitted to the fourth sub transistor M4 to turn off the third sub transistor M3 and the fourth sub transistor M4 at the same time.

Specifically, in the data writing stage, the third control terminal S_2-pSending a low-level control signal to the gate of the third sub-transistor M3 to turn on the third sub-transistor M3; meanwhile, the fourth control terminal S_2-nA high level control signal is transmitted to the gate of the third sub-transistor M3, turning on the fourth sub-transistor M4. The signal of the data signal terminal Vdata is transmitted to the second node N2, the signal of the second node N2 is transmitted to the third node N3 through the driving transistor M0, and the potential of the third node N3 is transmitted to the first node N1 through the third sub-transistor M3 and the fourth sub-transistor M4. In the light emitting stage, the third control terminal S_2-pA high-level control signal is sent to the gate of the third sub-transistor M3, and a fourth control terminal S_2-nA low level control signal is transmitted to the gate of the third sub-transistor M3, turning off the third sub-transistor M3 and the fourth sub-transistor M4 at the same time. When the third sub-transistor M3 and the fourth sub-transistor M4 are turned on and off, the gate voltages of the third sub-transistor M3 and the fourth sub-transistor M4 are changed, and even after the third sub-transistor M3 and the fourth sub-transistor M4 are turned off, parasitic capacitances of the third sub-transistor M3 and the fourth sub-transistor M4 are present. Since the polarities of the third sub-transistor M3 and the fourth sub-transistor M4 are opposite, the parasitic capacitance of the third sub-transistor M3 acting on the first node N1 is a positive value, the parasitic capacitance of the fourth sub-transistor M4 acting on the first node N1 is a negative value, and the influence of the superimposed parasitic capacitance values on the first node N1 is reduced, so that the third sub-transistor M3 and the fourth sub-transistor M4 are opposite, and the parasitic capacitance value is reducedThe influence on the gate voltage of the driving transistor M0 is reduced, so that the driving current generated by the driving transistor M0 is closer to the preset driving current value, thereby facilitating the improvement of the display brightness uniformity of the display device and the display effect of the display device.

Referring to fig. 6, optionally, the switch transistor module 40 includes a second data writing module 62, a first terminal of the second data writing module 62 is connected to the first node N1, and a second terminal is connected to the third node N3; the second data writing module 62 includes a fifth transistor M5, wherein the gate of the fifth transistor M5 is connected to the fifth control terminal (multiplexing the fourth control terminal S)_2-n) (ii) a The pixel driving circuit further comprises a compensation capacitor, wherein a first pole of the compensation capacitor C0 is connected to the first node N1, and a second pole of the compensation capacitor C0 is connected to a sixth control terminal (multiplexing the third control terminal S)_2-P)；

In the data writing stage, the fifth control terminal S_2-nSending a fifth turn-on control signal to the fifth transistor M5 to turn on the fifth transistor M5, so that the second data writing module 62 transmits the signal of the third node N3 to the first node N1; in the light emitting stage, the fifth control terminal S_2-nSending a fifth off control signal to the fifth transistor M5 to turn off the fifth transistor M5; meanwhile, a sixth control terminal S_2-PSending a charging signal to the compensation capacitor C0 to charge the compensation capacitor C0; in the same time frame, the polarity of the compensation capacitor C0 is opposite to the polarity of the capacitance formed between the gate and the first pole of the fifth transistor M5.

It should be noted that, this embodiment is only described by taking the fifth transistor M5 included in the second data writing module 62 as an N-type transistor as an example, in some other embodiments of the present application, the fifth transistor M5 may also be a P-type transistor, which is not specifically limited in this application. When the fifth transistor M5 is a P-type transistor, the fifth control terminal can be used to multiplex the third control terminal S_2-PThe sixth control terminal connected to the compensation capacitor C0 can multiplex the fourth control terminal S_2-n。

Specifically, in the data writing stage, the fifth control terminal S_2-nSends a high level to the gate of the fifth transistor M5The control signal turns on the fifth transistor M5. The signal of the data signal terminal Vdata is transmitted to the second node N2, the signal of the second node N2 is transmitted to the third node N3 through the driving transistor M0, and the potential of the third node N3 is transmitted to the first node N1 through the fifth transistor M5. In the light emitting stage, the fifth control terminal S_2-nSending a low-level control signal to the gate of the fifth sub-transistor 41 to turn off the fifth transistor M5, so that a negative parasitic capacitance is formed to act on the first node N1 when the fifth transistor M5 is turned from on to off; at this time, the sixth control terminal S_2-PA high-level control signal is sent to the second pole of the compensation capacitor C0, so that the compensation capacitor C0 forms a positive capacitance value to be applied to the first node N1, the influence of the positive capacitance value and the negative parasitic capacitance value on the first node N1 is reduced after the positive capacitance value and the negative parasitic capacitance value are superposed, and therefore, the influence on the gate voltage of the driving transistor M0 is reduced, the driving current generated by the driving transistor M0 is closer to a preset driving current value, and therefore, the display brightness uniformity of the display device is improved, and the display effect of the display device is improved.

Based on the same inventive concept, embodiments of the present invention provide a display device, including the above pixel driving circuit.

Referring to fig. 11, fig. 11 is a schematic plan view illustrating a display device 100 according to the present invention. Fig. 11 provides a display device 100 including a pixel driving circuit according to any of the above embodiments of the present invention. The display device in the embodiment of the present invention is described by taking a mobile phone as an example, but it should be understood that the display device provided in the embodiment of the present invention may be other display devices with a display function, such as a computer, a television, and a vehicle-mounted display device, and the present invention is not limited thereto. The display device provided in the embodiment of the present invention has the beneficial effects of the pixel driving circuit provided in the embodiment of the present invention, and specific reference may be made to the specific description of the pixel driving circuit in each of the above embodiments, which is not repeated herein.

As can be seen from the foregoing embodiments, the pixel driving circuit, the driving method thereof, and the display device provided in the present invention at least achieve the following advantages:

Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A pixel driving circuit, comprising:

a first power signal terminal and a second power signal terminal;

2. The pixel driving circuit according to claim 1, wherein the switching transistor module comprises an initialization module having a first terminal connected to the first node and a second terminal connected to a reference voltage terminal, the reference voltage terminal being configured to provide a reference voltage signal to the first node to turn on or off the driving transistor;

the initialization module comprises a first sub transistor and a second sub transistor, wherein the grid electrode of the first sub transistor is connected with a first control end, and the grid electrode of the second sub transistor is connected with a second control end; in the same time frame, the first control terminal sends a control signal to the first sub-transistor, and the second control terminal sends a control signal to the second sub-transistor, so that the first sub-transistor and the second sub-transistor are turned on or turned off simultaneously.

3. The pixel driving circuit according to claim 1, wherein the switching transistor module comprises a first data writing module, a first terminal of the first data writing module is connected to the first node, a second terminal of the first data writing module is connected to the third node, and the first data writing module is configured to transmit a signal of the third node to the first node;

the first data writing module comprises a third sub-transistor and a fourth sub-transistor, the grid electrode of the third sub-transistor is connected with a third control end, and the grid electrode of the fourth sub-transistor is connected with a fourth control end; in the same time frame, the third control terminal sends a control signal to the third sub-transistor, and the fourth control terminal sends a control signal to the fourth sub-transistor, so that the third sub-transistor and the fourth sub-transistor are turned on or turned off simultaneously.

4. The pixel driving circuit according to claim 1 or 2, wherein the switching transistor module comprises a second data writing module, a first terminal of the second data writing module is connected to the first node, a second terminal of the second data writing module is connected to the third node, and the second data writing module is configured to transmit a signal of the third node to the first node; the second data writing module comprises a fifth transistor, the grid electrode of the fifth transistor is connected with a fifth control end, and the first pole of the fifth transistor is connected with the first node;

the pixel driving circuit further comprises a compensation capacitor, a first pole of the compensation capacitor is connected with the first node, and a second pole of the compensation capacitor is connected with a sixth control end; in the same time frame, the polarity of the compensation capacitance is opposite to the polarity of the capacitance formed between the gate and the first pole of the fifth transistor.

5. The pixel driving circuit according to claim 1, wherein the switching transistor module further comprises an inverter, an input terminal of the inverter is connected to a seventh control terminal;

and the grid electrode of one of the two sub-transistors is connected to the seventh control end, and the grid electrode of the other sub-transistor is connected to the output end of the inverter.

6. The pixel driving circuit according to claim 1, wherein the two sub-transistors comprise a P-type transistor and an N-type transistor, the P-type transistor is a PMOS transistor, and the N-type transistor is an NMOS transistor or an oxide thin film transistor.

7. The pixel driving circuit according to claim 6, wherein the P-type transistor is connected in series between the N-type transistor and the first node, or wherein the N-type transistor is connected in series between the P-type transistor and the first node.

8. The pixel driving circuit according to claim 1, wherein the light emission control module includes a sixth transistor and a seventh transistor, a gate of the sixth transistor is electrically connected to a light emission control signal terminal through a first light emission control line, a gate of the seventh transistor is electrically connected to a light emission control signal terminal through a second light emission control line, and the light emission control signal terminal is configured to provide a switch control signal to the sixth transistor and the seventh transistor;

a first pole of the sixth transistor is connected with a first power supply signal end, and a second pole of the sixth transistor is connected with the second node; the first pole of the seventh transistor is connected to the third node, and the second pole of the seventh transistor is connected to the fourth node.

9. The pixel driving circuit according to claim 1, further comprising a third data writing module, wherein the third data writing module comprises an eighth transistor, a gate of the eighth transistor is electrically connected to the eighth control terminal, a first electrode of the eighth transistor is electrically connected to a data signal terminal, a second electrode of the eighth transistor is electrically connected to the second node, and the data signal terminal is configured to provide a data signal to the second node.

10. The pixel driving circuit according to claim 1, further comprising a reset module, wherein the reset module comprises a ninth transistor, a gate of the ninth transistor is electrically connected to the ninth control terminal, a first electrode of the ninth transistor is electrically connected to a reset voltage terminal, a second electrode of the ninth transistor is electrically connected to the fourth node, and the reset voltage terminal is configured to provide a reset signal to the fourth node.

11. A driving method of a pixel driving circuit, wherein the driving method is used for driving the pixel driving circuit according to any one of claims 1 to 10, the driving circuit comprises a first power signal terminal, a second power signal terminal, a driving transistor, a light emitting element, a light emitting control module, and at least one switching transistor module, a first terminal of the switching transistor module is connected to the first node, and at least a part of the switching transistor module comprises two sub-transistors connected in series; the driving circuit comprises an initialization phase, a data writing phase and a light emitting phase, and the driving method comprises the following steps:

12. The driving method of the pixel driving circuit according to claim 11, wherein the switching transistor module comprises an initialization module having a first terminal connected to the first node and a second terminal connected to a reference voltage terminal; the initialization module comprises a first sub transistor and a second sub transistor, wherein the grid electrode of the first sub transistor is connected with a first control end, and the grid electrode of the second sub transistor is connected with a second control end;

in the initialization stage, a first control end sends a first conduction control signal to the first sub-transistor, and simultaneously, a second control end sends a second conduction control signal to the second sub-transistor, so that the first sub-transistor and the second sub-transistor are simultaneously conducted, and a reference voltage end transmits a reference voltage signal to the first node to conduct the driving transistor;

in the data writing phase, the first control terminal sends a first off control signal to the first sub-transistor, and simultaneously, the second control terminal sends a second off control signal to the second sub-transistor, so that the first sub-transistor and the second sub-transistor are turned off simultaneously.

13. The driving method of the pixel driving circuit according to claim 11, wherein the switching transistor module includes a first data writing module, a first terminal of the first data writing module is connected to the first node, and a second terminal of the first data writing module is connected to the third node; the first data writing module comprises a third sub-transistor and a fourth sub-transistor, the grid electrode of the third sub-transistor is connected with a third control end, and the grid electrode of the fourth sub-transistor is connected with a fourth control end;

in the data writing stage, a third control terminal sends a third conduction control signal to the third sub-transistor, and simultaneously, a fourth control terminal sends a fourth conduction control signal to the fourth sub-transistor, so that the third sub-transistor and the fourth sub-transistor are simultaneously conducted, and the first data writing module transmits a signal of the third node to the first node;

in the light emitting stage, the third control terminal sends a third cut-off control signal to the third sub-transistor, and simultaneously, the fourth control terminal sends a fourth cut-off control signal to the fourth sub-transistor, so that the third sub-transistor and the fourth sub-transistor are cut off simultaneously.

14. The driving method of the pixel driving circuit according to claim 11, wherein the switching transistor module includes a second data writing module, a first terminal of the second data writing module is connected to the first node, and a second terminal of the second data writing module is connected to the third node; the second data writing module comprises a fifth transistor, and the grid electrode of the fifth transistor is connected with a fifth control terminal; the pixel driving circuit further comprises a compensation capacitor, a first pole of the compensation capacitor is connected with the first node, and a second pole of the compensation capacitor is connected with a sixth control end;

in the data writing phase, the fifth control terminal sends a fifth conduction control signal to the fifth transistor, so that the fifth transistor is turned on, and the second data writing module transmits a signal of the third node to the first node;

in the light emitting stage, the fifth control terminal sends a fifth cut-off control signal to the fifth transistor to cut off the fifth transistor; meanwhile, the sixth control end sends a charging signal to the compensation capacitor to charge the compensation capacitor; in the same time frame, the polarity of the compensation capacitance is opposite to the polarity of the capacitance formed between the gate and the first pole of the fifth transistor.

15. A display device comprising the pixel driving circuit according to any one of claims 1 to 10.