CN110728365B - Method for selecting calculation bit width of multi-bit-width PE array and calculation precision control circuit - Google Patents
Method for selecting calculation bit width of multi-bit-width PE array and calculation precision control circuit Download PDFInfo
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Abstract
The invention discloses a method for selecting the calculation bit width of a multi-bit wide PE array and a calculation precision control circuit, and belongs to the technical field of calculation, calculation and counting. The method analyzes the output probability value of the last Softmax layer of the neural network to judge the size of the output maximum probability to evaluate the network identification precision, judges whether the output maximum probability value meets the calculation precision requirement or not through two set probability threshold values, adopts a signal of a high bit width processing element array if the maximum probability value is smaller than the minimum threshold value, maintains the previous bit width processing element array if the maximum probability value is larger than the minimum threshold value and smaller than the maximum threshold value, adopts a signal of a low bit width processing element array if the maximum probability value is larger than the maximum threshold value, maintains the maximum probability output by the network in a certain atmosphere, ensures the identification precision of the network and reduces the power consumption.
Description
Technical Field
The invention discloses a method for selecting the calculation bit width of a multi-bit wide PE array and a calculation precision control circuit, relates to the physical realization of a neural network, and belongs to the technical field of calculation, calculation and counting.
Background
In recent years, deep neural networks have become the most popular research direction. Neural networks have been widely used in many research fields, such as pattern recognition, automatic control, signal processing, decision assistance, artificial intelligence, etc. After many years of research and development, pattern recognition has become an advanced technology widely applied to the aspects of voice recognition, fingerprint recognition, remote sensing image recognition, face recognition, character recognition, handwritten font recognition, industrial fault detection and the like.
A common method for solving the multi-classification problem by using a neural network is to set n output nodes, where n is the number of classes. The probability of any event occurring is between 0 and 1, and there is always one event occurring (the sum of the probabilities is 1). The Softmax regression can be used as a learning algorithm to optimize the classification result, and is an additional processing layer in the neural network, so that the output of the neural network is changed into a probability distribution.
Through simple analysis, when the recognition performance of the neural network is not high, namely no prominent probability is output, most probability values are similar; when the recognition performance of the neural network is high, the network outputs a maximum probability value to a certain port. Therefore, the identification precision of the network can be evaluated by judging the maximum probability, and then whether the adjustment of the calculation bit width of the circuit for realizing the neural network is needed or not can be determined, the rationality of the adjustment of the calculation bit width of the network by people can be detected according to the characteristic, and the error correction is carried out on the abnormal and unreasonable adjustment.
Disclosure of Invention
The invention aims to solve the technical problem that the recognition accuracy is unreasonable due to the change of the classification accuracy of the neural network along with the change of input data, and provides a selection method for calculating the bit width of a multi-bit wide PE array and a calculation accuracy control circuit.
The invention adopts the following technical scheme for realizing the aim of the invention:
the method for selecting the calculation bit width of the multi-bit width PE array is characterized in that probability distribution output by a neural network Softmax layer is input to a confidence coefficient comparison module. The confidence coefficient comparison module distributes corresponding confidence coefficient comparison units according to the number of the input probabilities, and the confidence coefficient comparison units compare pairwise to output the maximum probability value. The confidence coefficient comparison module outputs the compared maximum value to the confidence coefficient threshold judgment module. The confidence threshold judgment module is provided with two probability thresholds with one larger probability threshold and one smaller probability threshold, and if the screened maximum probability value is larger than the larger probability threshold or smaller than the smaller probability threshold, the threshold comparison signal is output as '0'; if the maximum probability value selected is between the lower probability threshold and the higher probability threshold, the threshold comparison signal is output as "1". The bit width dynamic selection module judges whether the calculation bit width of the current processing element array needs to be changed or not according to the threshold comparison signal, and if the output of the threshold comparison signal is '1', the bit width does not need to be changed; if the threshold comparison signal output is "0", the current calculated bit width is changed. And finally, the processing element array performs calculation according to the corresponding calculation bit width to control the identification precision of the neural network.
The application also provides a calculation precision control circuit for realizing the method for selecting the calculation bit width of the multi-bit-width PE array, which comprises the following steps: the device comprises a confidence coefficient comparison module for realizing probability maximum value screening, a confidence coefficient threshold value judgment module for judging the numerical relationship between the probability maximum value and the minimum threshold value as well as the maximum threshold value, and a bit width dynamic selection module for dynamically selecting the bit width satisfying the neural network identification precision calculation bit width according to the numerical relationship between the probability maximum value and the minimum threshold value as well as the maximum threshold value.
Furthermore, the confidence coefficient comparison module is composed of a plurality of confidence coefficient comparison units, and the function of the confidence coefficient comparison module is to compare the output probability values of the neural network Softmax layer in pairs and output the maximum probability value in the classification probability. For example, the neural network classification probability output of 16 classifications has 16 probability values with the sum of "1", and at this time, the confidence degree comparison module needs 16 confidence degree comparison units to form, and the maximum probability value of the 16 classification probabilities can be output by pairwise comparison.
Furthermore, the confidence degree comparison unit is composed of a comparator and an alternative selector. The comparator outputs a comparison result signal of the magnitude of the two numbers, the comparison result signal of the magnitude is input into the alternative selector, and the alternative selector outputs the maximum value of the two numbers according to the comparison result signal of the magnitude.
Furthermore, the confidence threshold judging module consists of two comparators and an exclusive-or gate. Two comparators are respectively provided with a larger probability threshold value Vth1And a smaller probability threshold Vth2And the other input of the two comparators is the maximum probability value output by the confidence degree comparison module. If the confidence coefficient is output by the comparison moduleThe maximum probability value being greater than a larger probability threshold Vth1If the two comparators output 1 and 1, the exclusive-or gate outputs a threshold comparison signal 0; if the maximum probability value output by the confidence coefficient comparison module is smaller than the smaller probability threshold value Vth2If the two comparators output '0' and '0', the exclusive-or gate outputs a threshold comparison signal '0'; if the maximum probability value output by the confidence coefficient comparison module is larger than the smaller probability threshold value Vth2Less than a larger probability threshold Vth1Then, the two comparators output "0" and "1", and the exclusive or gate outputs the threshold comparison signal "1".
Furthermore, the bit width dynamic selection module is composed of a one-bit register, two inverters and two tri-state gates. When the threshold comparison signal is '0', indicating that the working mode of the current bit width processing element array does not meet the functional requirement, possibly having the problem of insufficient neural network identification precision or redundant power consumption of the whole computing circuit, and the working mode of the bit width processing element array needing to be replaced, outputting the value stored by the last state register through an inverter as a computing precision control signal; when the threshold comparison signal is "1", which indicates that the working mode of the current bit width processing element array meets the condition again, the value in the register is output as the calculation precision control signal.
Based on the inventive concept of the calculation precision control circuit, the application also provides an intelligent calculation circuit, wherein the multi-bit wide PE array in the circuit switches the PE arrays with different calculation bit widths according to the control signal output by the calculation precision circuit, and the switching operation is not executed when the control signal output by the calculation precision circuit indicates that the PE array with the current bit width meets the requirement of the neural network identification precision.
By adopting the technical scheme, the invention has the following beneficial effects:
(1) aiming at the situation that input data under different environments affect the recognition accuracy of a neural network, the method for selecting the calculation bit width evaluates the recognition accuracy of the network by utilizing the maximum probability value recognized from the probability distribution output by the neural network in real time, dynamically adjusts the calculation bit width of the network according to an evaluation result, selects a high-bit-width PE array with high recognition accuracy when the lowest recognition accuracy requirement is not met so as to improve the recognition accuracy, selects a low-bit-width PE array with low recognition accuracy when the highest recognition accuracy requirement is met so as to reduce power consumption, and maintains the calculation bit width unchanged when the recognition accuracy requirement is met and the maximum accuracy is not exceeded.
(2) The calculation precision control circuit designed according to the bit width calculation method takes the real-time probability distribution output by the neural network as the data to be processed, can screen out the maximum probability value, and can more accurately evaluate the recognition precision of the neural network in the current environment.
(3) The calculation accuracy control circuit provided by the application is adopted to realize the switching of the working modules of the multi-bit-width PE array, the intelligent adjustment of the calculation bit width of the PE array is used for maintaining the recognition accuracy of the neural network, and the power consumption of the whole calculation circuit is reduced while the recognition accuracy is maintained.
Drawings
FIG. 1 is a block diagram of an architecture according to the present invention.
FIG. 2 is a functional classification basis of the present invention.
Fig. 3 is a detailed overall structural diagram of the present invention.
FIG. 4 is a confidence comparison module of the present invention.
FIG. 5 is a confidence comparison unit of the present invention.
FIG. 6 is a block diagram of a confidence threshold decision module according to the present invention.
FIG. 7 is a block diagram of dynamic bit width selection according to the present invention.
FIG. 8 shows the specific steps of the intelligent computing circuit of the present invention.
Detailed Description
The present invention is further illustrated by the following examples, which are intended to be purely exemplary and are not intended to limit the scope of the invention, as various equivalent modifications of the invention will occur to those skilled in the art upon reading the present disclosure and fall within the scope of the appended claims.
The intelligent computing circuit analyzes whether the maximum probability value output by the neural network is within a set threshold range or not under the coordination control of the internal modules, evaluates whether the identification precision of the neural network meets the functional requirement or not, and dynamically selects the computing bit width of the processing element array (namely the PE array). As shown in fig. 1, the overall circuit includes a confidence-based computational precision control module and a multi-bit wide processing element array module.
The multi-bit wide element array module is divided into a high-bit wide array of processing elements and a low-bit wide array of processing elements. In practice the computational bit widths for the two arrays of processing elements may be set to 8 bits and 4 bits. The 8-bit processing element array can provide relatively high calculation precision, and the recognition precision of the neural network is improved; the 4-bit processing element array provides relatively low calculation precision, and the 4-bit processing element array can reduce the calculation power consumption of the whole calculation circuit under the condition of meeting the recognition precision of the neural network.
The confidence-based calculation precision control module comprises a confidence comparison module, a confidence threshold judgment module and a bit width dynamic selection module. As shown in fig. 3 and 4, the probability distribution output by the neural network may be filtered out to have the maximum probability value by the confidence comparison unit through the confidence comparison module. In practice, if the neural network performs 16 classifications, 16 confidence comparison units may be used to perform the screening comparison of the maximum probability value, and the structure of the confidence comparison unit is shown in fig. 5.
As shown in fig. 6, the confidence threshold judging module analyzes and compares the output maximum probability value with the set probability threshold, and the threshold outputs a comparison output signal to provide an evaluation result signal. In practice, two thresholds can be set to 0.9 and 0.6. If the output maximum probability value is less than 0.6, the identification precision of the network is low, the calculation bit width of the processing element array needs to be improved, the results output by the two comparators are '0' and '0', and the threshold comparison signal is '0' after the exclusive-or gate is passed; if the output maximum probability value is greater than the threshold value of 0.9, the identification precision of the network is over high, the calculation bit width can be reduced to reduce the calculation power consumption, the results output by the two comparators are '1' and '1', and the threshold value comparison signal is '0' after the exclusive-or gate is passed; if the output maximum probability value is greater than 0.6 and less than 0.9, the identification rate of the network is shown to meet the functional requirement, the calculation bit width of the processing element array is not required to be changed, the output results of the two comparators are '1' and '0', and the signal is '1' through the threshold comparison after the exclusive-or gate. The functional classification is according to the graph shown in fig. 2.
As shown in fig. 7, the bit width dynamic selection module determines whether to change the calculated bit width of the processing element array according to the threshold comparison signal. If the threshold comparison signal is '1', the corresponding bit width processing element array meets the functional requirement, and the register in the bit width dynamic selection module maintains the last output; if the threshold comparison signal is "0", the corresponding bit width processing element array does not meet the functional requirement, the value output by the register in the dynamic bit width module is inverted by the inverter and then output, and the output signal can change the currently used processing element array.
The work flow of the intelligent computing circuit shown in fig. 1 is described with reference to fig. 8, and the specific work flow includes the following steps:
step 101: the probability distribution value output by the Softmax layer is used as an input signal of the confidence coefficient comparison module;
step 102: the confidence coefficient comparison module is configured with a corresponding confidence coefficient comparison unit to screen out the maximum probability value in the probability distribution;
step 103: the confidence threshold comparison module compares the screened maximum probability value with the two set probability thresholds, and if the screened maximum probability value is larger than a larger probability threshold Vth1Or less than a small probability threshold Vth2If yes, the threshold comparison signal is output as '0'; if the maximum probability value screened out is at a smaller probability threshold value Vth2And a larger probability threshold Vth1In between, the threshold comparison signal output is "1";
step 104: the bit width dynamic selection module takes a threshold comparison signal output by the confidence threshold comparison module as input, if the threshold comparison signal is '0', the calculation bit width of the current bit width calculation can not meet the functional requirement, the calculation bit width of the processing element array needs to be adjusted, the threshold comparison signal opens a three-state gate to enable a signal in the last state in the register to be processed through an inverter and output as a calculation precision control signal, if the threshold comparison signal is '1', the calculation of the current bit width satisfies the functional requirement, the calculation bit width of the processing element array does not need to be adjusted, and the threshold comparison signal opens another three-state gate to enable the signal in the last state in the register to be output as the calculation precision control signal as usual;
step 105: the multi-bit wide processing element array module obtains a calculation precision control signal output by the bit width dynamic selection module, and dynamically selects the required bit width processing element array in time to perform circuit calculation.
Claims (8)
1. The method for selecting the calculated bit width of the multi-bit-width PE array is characterized in that the probability that input data output by a neural network softmax layer are classified results is compared pairwise, the maximum probability value is screened from the probability distribution that the data belong to the classified results, and the calculated bit width meeting the requirement of the neural network identification precision is selected according to the numerical relationship between the maximum probability value and a minimum threshold value as well as a maximum threshold value; the method for selecting the calculation bit width meeting the requirement of the neural network identification precision according to the numerical relationship between the maximum probability value and the minimum threshold value as well as the maximum threshold value comprises the following steps: and selecting a high bit width PE array when the maximum probability value is smaller than the minimum threshold value, selecting a low bit width PE array when the maximum probability value is larger than the maximum threshold value, and keeping the calculation bit width of the multi-bit width PE array unchanged when the maximum probability value is between the minimum threshold value and the maximum threshold value.
2. The method for selecting the computational bit width of the multi-bit width PE array according to claim 1, wherein the method for selecting the computational bit width meeting the requirement of the neural network identification precision according to the numerical relationship between the probability maximum value and the minimum threshold value and the maximum threshold value comprises the following steps: and comparing the probability maximum value with the minimum threshold value, comparing the probability maximum value with the maximum threshold value, and carrying out XOR logical operation on the two comparison results.
3. A calculation accuracy control circuit, comprising:
the confidence coefficient comparison module compares the probability of each classification result of the input data output by the neural network softmax layer pairwise, screens out the maximum probability value from the probability distribution of the data belonging to each classification result,
a confidence threshold judgment module for judging the numerical relationship between the maximum probability and the minimum threshold and the maximum threshold, and,
and the bit width dynamic selection module selects the high bit width PE array when the maximum probability value is smaller than the minimum threshold value, selects the low bit width PE array when the maximum probability value is larger than the maximum threshold value, keeps the calculation bit width of the multi-bit width PE array unchanged when the maximum probability value is between the minimum threshold value and the maximum threshold value, and outputs a control signal representing the calculation bit width selection result to the multi-bit width PE array.
4. The calculation accuracy control circuit of claim 3, wherein the confidence comparison module comprises a plurality of confidence comparison units for pairwise comparison of the probability values at the respective input terminals, each confidence comparison unit comprising:
a comparator, the input of which is connected with the two probability values and outputs the comparison result, and,
the data input end of the alternative data selector is connected with the two probability values input into the comparator, and the alternative data selector controls the comparison result output by the comparator to output the larger value of the two probability values.
5. The calculation accuracy control circuit according to claim 3, wherein the confidence threshold judging module comprises:
a first comparator having an input for receiving the maximum probability and the minimum threshold and an output for comparing the maximum probability and the minimum threshold
A second comparator having an input for receiving the maximum probability value and the maximum threshold value, and outputting a result of comparing the maximum probability value and the maximum threshold value, and,
and the output end of the exclusive-OR gate is connected with the comparison results output by the two comparators, and the threshold comparison results representing the numerical relationship between the maximum probability value and the minimum threshold value and the maximum threshold value are output.
6. The calculation accuracy control circuit according to claim 3, wherein the bit width dynamic selection module comprises:
a first inverter, the input of which is connected with the threshold comparison result and outputs the inverted threshold comparison result,
a first tri-state gate, the input of which is connected with the last state control signal output by the register, the control end of which is connected with the output end of the first inverter, and the last state control signal is output when the probability maximum value is between the minimum threshold value and the maximum threshold value,
a second inverter, the input end of which is connected with the last state control signal output by the register and outputs the inverted signal of the last state control signal,
a second tri-state gate having an input terminal connected to the output terminal of the second inverter, and a control terminal connected to the threshold comparison result, and outputting the inverted signal of the previous state control signal when the probability maximum value is smaller than the minimum threshold or larger than the maximum threshold, and,
and the register buffers the last state control signal and updates data when the second tri-state gate outputs the inverted signal of the last state control signal.
7. An intelligent computing circuit, comprising: the multi-bit wide PE array and the calculation precision control circuit as claimed in any one of claims 3 to 6, wherein the multi-bit wide PE array switches PE arrays with different calculation bit widths or maintains the calculation bit widths unchanged under the action of a control signal output by the calculation precision control circuit.
8. The intelligent computing circuit of claim 7, wherein the multi-bit wide PE arrays comprise a high-bit wide PE array and a low-bit wide PE array, each power circuit connected to the PE arrays comprises a MOS transistor for power supply and a MOS transistor for power feed, the MOS transistors for power supply and power feed are connected with inverted control signals, and the control signals are provided by the computing precision control circuit.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107783935A (en) * | 2017-09-26 | 2018-03-09 | 东南大学 | The approximate calculation reconfigurable arrays of computing can be matched somebody with somebody based on dynamic accuracy |
| CN107992329A (en) * | 2017-07-20 | 2018-05-04 | 上海寒武纪信息科技有限公司 | A kind of computational methods and Related product |
| CN110135086A (en) * | 2019-05-20 | 2019-08-16 | 合肥工业大学 | The variable softmax function hardware circuit of computational accuracy and its implementation |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11507624B2 (en) * | 2014-11-18 | 2022-11-22 | Yahoo Assets Llc | Method and system for providing query suggestions based on user feedback |
| US10262259B2 (en) * | 2015-05-08 | 2019-04-16 | Qualcomm Incorporated | Bit width selection for fixed point neural networks |
| CN114004349A (en) * | 2016-08-05 | 2022-02-01 | 中科寒武纪科技股份有限公司 | Arithmetic unit, method and device capable of supporting different bit width arithmetic data |
| CN108256642B (en) * | 2016-12-29 | 2021-08-31 | 上海寒武纪信息科技有限公司 | Circuit design method for non-precise calculation neural network |
| CN109376845B (en) * | 2017-08-09 | 2021-10-22 | 上海寒武纪信息科技有限公司 | Dynamic adjustment method and dynamic adjustment coprocessor |
| US10573295B2 (en) * | 2017-10-27 | 2020-02-25 | Salesforce.Com, Inc. | End-to-end speech recognition with policy learning |
| CN109726809B (en) * | 2017-10-30 | 2020-12-08 | 赛灵思公司 | Hardware implementation circuit of deep learning softmax classifier and control method thereof |
| CN108647779B (en) * | 2018-04-11 | 2021-06-04 | 复旦大学 | Reconfigurable computing unit of low-bit-width convolutional neural network |
| CN109325590B (en) * | 2018-09-14 | 2020-11-03 | 中国科学院计算技术研究所 | Device for realizing neural network processor with variable calculation precision |
| CN109871896B (en) * | 2019-02-26 | 2022-03-25 | 北京达佳互联信息技术有限公司 | Data classification method and device, electronic equipment and storage medium |
| CN110728365B (en) * | 2019-09-12 | 2022-04-01 | 东南大学 | Method for selecting calculation bit width of multi-bit-width PE array and calculation precision control circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107992329A (en) * | 2017-07-20 | 2018-05-04 | 上海寒武纪信息科技有限公司 | A kind of computational methods and Related product |
| CN107783935A (en) * | 2017-09-26 | 2018-03-09 | 东南大学 | The approximate calculation reconfigurable arrays of computing can be matched somebody with somebody based on dynamic accuracy |
| CN110135086A (en) * | 2019-05-20 | 2019-08-16 | 合肥工业大学 | The variable softmax function hardware circuit of computational accuracy and its implementation |
Non-Patent Citations (2)
| Title |
|---|
| E＇douard Grave et al..Efficient softmax approximation for GPUs.《arXiv》.2017,第1-9页. * |
| 卷积神经网络的FPGA并行加速方案设计;方睿等;《计算机工程与应用》;20141029;第32-36页 * |
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