CN110727628A - Isolated time system source input/output device based on PCIE interface - Google Patents
Isolated time system source input/output device based on PCIE interface Download PDFInfo
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- CN110727628A CN110727628A CN201911028270.2A CN201911028270A CN110727628A CN 110727628 A CN110727628 A CN 110727628A CN 201911028270 A CN201911028270 A CN 201911028270A CN 110727628 A CN110727628 A CN 110727628A
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- pcie interface
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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Abstract
The invention discloses an isolated time system source input and output device based on a PCIE interface, which comprises: the system comprises a time system source input isolation level conversion circuit, an FPGA logic circuit, a high-precision clock source circuit, a multi-channel time system output isolation level conversion circuit, a PCIE interface conversion Local bus circuit, an RTC circuit and a fault output circuit. The invention has the advantages and beneficial effects that: the invention not only realizes the uniformity of time and system of the whole system, but also provides the functions of reading clock information and error reporting and correcting faults for the host. The method has the characteristics of clear target, strong operability, simplicity and practicability.
Description
Technical Field
The invention relates to the field of industrial control, in particular to an isolated time system source input and output device based on a PCIE interface.
Background
The PCIE bus is a high-speed serial computer expansion bus standard. It is proposed by intel in 2001, aiming at replacing the old PCI and PCI-X bus standards, belonging to high-speed serial point-to-point dual-channel high-bandwidth transmission, and the current PCIE standard reaches version 4.0, and the transmission rate can reach 16 GT/S.
The clock is the pulse of the embedded system, and the processor core completes instruction execution, state conversion and the like under the drive of the clock. The external device completes various operations such as serial communication, AD conversion, timer counting and the like under the driving of the clock. For a complex system, the clock homology unification can be realized, and stable, accurate and simultaneous operation can be realized, so that the time unification is very important.
The electrical isolation mainly reduces mutual interference between different circuits. Not only can protect the electrical structure of the system, but also can keep the accuracy of the signal.
Disclosure of Invention
The technical problem to be solved by the invention is to provide an isolated time system source input and output device based on a PCIE interface.
In order to achieve the purpose, the technical scheme of the invention is as follows:
an isolated time system source input and output device based on a PCIE interface comprises: the system comprises a time system source input isolation level conversion circuit, an FPGA logic circuit, a high-precision clock source circuit, a multi-channel time system output isolation level conversion circuit, a PCIE interface conversion Local bus circuit, an RTC circuit and a fault output circuit.
The device also comprises a high-precision clock circuit and an RTC circuit, if no external input exists, the on-board high-precision clock circuit is used as a time system source to generate clock signals, state information is generated, and the RTC circuit is used for obtaining time information.
The invention has the advantages and beneficial effects that: the invention not only realizes the uniformity of time and system of the whole system, but also provides the functions of reading clock information and error reporting and correcting faults for the host.
Drawings
Fig. 1 is a block diagram of an isolated timing system source input/output device based on a PCIE interface according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the detailed description.
As shown in fig. 1, the present invention relates to an isolated timing system source input/output device based on a PCIE interface, including: the system comprises a time system source input isolation level conversion circuit, an FPGA logic circuit, a high-precision clock circuit, a multi-channel time system output isolation level conversion circuit, a PCIE interface conversion Local bus circuit and a fault output circuit, wherein the time system source input isolation level conversion circuit, the high-precision clock source circuit, the multi-channel time system output isolation level conversion circuit, the PCIE interface conversion Local bus circuit and the fault output circuit are all connected with the FPGA logic circuit; an external input system source generates a group of RS422A level signals through a system source input isolation level conversion circuit and transmits the signals to an FPGA logic circuit, the FPGA logic circuit processes data to generate multi-path system signals, and the multi-path system signals are transmitted to each subsystem through a multi-path system output isolation level conversion circuit; the FPGA logic circuit converts a Local bus circuit through a PCIE interface to enable an upper computer to acquire processing information of the FPGA logic circuit.
The device also comprises a high-precision clock circuit and an RTC circuit, if no external input exists, the on-board high-precision clock circuit is used as a time system source to generate clock signals, state information is generated, and the RTC circuit is used for obtaining time information.
The FPGA logic processing circuit adopts an EP3C5144 chip of ALTERA company to perform logic processing, generate multi-channel time system output, generate working state information, read time information of an RTC circuit, and communicate with an upper computer through a PCIE conversion Local bus circuit. When a fault occurs, the alarm is given, an upper computer fault register is provided, and a fault alarm indicator lamp is onboard.
The time system source input isolation level conversion circuit adopts an ADM2682 chip of ADI company to convert an input signal into an isolation RS422A level signal.
The multi-output time system signal isolation circuit adopts an ADM2682 chip of ADI company to convert time system signals generated by FPGA into RS422A isolation signals for use by each level of system.
The PCIE to Local bus circuit adopts a PEX8311 chip of PERICOM company, converts the PCIE circuit into Local bus and enables an upper computer to directly communicate with the FPGA.
The onboard high-precision clock circuit adopts a Tangshan sharp high-precision oscillation crystal oscillator, and the error can reach 3 ppm. And when no external clock source exists, the clock source is used by the FPGA to generate clock signals.
The RTC circuit adopts PCF8563 chip of NXP company, carries button cell on-board, also can record time information when whole system is not powered, can let FPGA read time information, makes all grades of systems unify time information.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (8)
1. An isolated timing system source input and output device based on a PCIE interface comprises: the system comprises a time system source input isolation level conversion circuit, an FPGA logic circuit, a high-precision clock circuit, a multi-channel time system output isolation level conversion circuit, a PCIE interface conversion Localbus circuit and a fault output circuit, wherein the time system source input isolation level conversion circuit, the high-precision clock source circuit, the multi-channel time system output isolation level conversion circuit, the PCIE interface conversion Local bus circuit and the fault output circuit are all connected with the FPGA logic circuit; an external input system source generates a group of RS422A level signals through a system source input isolation level conversion circuit and transmits the signals to an FPGA logic circuit, the FPGA logic circuit processes data to generate multi-path system signals, and the multi-path system signals are transmitted to each subsystem through a multi-path system output isolation level conversion circuit; the FPGA logic circuit converts a Local bus circuit through a PCIE interface to enable an upper computer to acquire processing information of the FPGA logic circuit.
2. The isolated timing system source input-output device based on a PCIE interface of claim 1, further comprising an onboard high precision clock circuit and an RTC circuit, and if there is no external input timing source, the onboard high precision clock circuit is used as the timing system source to generate a clock signal and generate status information, and the RTC circuit is used to obtain time information.
3. The isolated timing system source input-output device based on the PCIE interface of claim 1, wherein the FPGA logic processing circuit performs logic processing by using an EP3C5144 chip, generates multiple timing system outputs, generates operating state information, reads time information of an RTC circuit, and communicates with an upper computer through a PCIE switch Local bus circuit.
4. The isolated timing system source input-output device based on PCIE interface of claim 1, wherein the timing system source input isolation level conversion circuit employs an ADM2682 chip of ADI corporation, for converting an input signal into an isolated RS422A level signal.
5. The isolated timing system source input-output device based on PCIE interface of claim 1, wherein the multiple output timing system signal isolation circuit uses an ADM2682 chip, and is configured to convert a timing system signal generated by the FPGA logic circuit into an RS422A isolation signal for use by each stage of system.
6. The isolated timing system source input-output device based on PCIE interface of claim 1, wherein the PCIE-to-Localbus bus circuit uses a PEX8311 chip to convert the PCIE circuit into Localbus, so that an upper computer can directly communicate with the FPGA.
7. The isolated timing system source input-output device based on PCIE interface of claim 2, wherein the onboard high-precision clock circuit uses a high-precision oscillation crystal oscillator with an error of 3ppm, and is used by an FPGA to generate timing system signals when there is no external timing system source.
8. The isolated timing system source input-output device based on a PCIE interface of claim 2, wherein the RTC circuit employs a PCF8563 chip, and further comprises an on-board button battery.
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CN201911028270.2A CN110727628A (en) | 2019-10-28 | 2019-10-28 | Isolated time system source input/output device based on PCIE interface |
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Citations (4)
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---|---|---|---|---|
CN204270025U (en) * | 2014-12-16 | 2015-04-15 | 天津天保电力有限公司 | There is the clock system of IRIG-B time adjustment function |
CN106527576A (en) * | 2016-12-01 | 2017-03-22 | 郑州云海信息技术有限公司 | Clock separation designing method and system for PCIE device |
CN108008623A (en) * | 2017-12-08 | 2018-05-08 | 北京强度环境研究所 | Timing System and the method that Timing Signal is provided |
CN109189706A (en) * | 2018-09-28 | 2019-01-11 | 天津市英贝特航天科技有限公司 | A kind of multichannel programmable differential timing interface module and working method based on OpenVPX |
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2019
- 2019-10-28 CN CN201911028270.2A patent/CN110727628A/en not_active Withdrawn
Patent Citations (4)
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---|---|---|---|---|
CN204270025U (en) * | 2014-12-16 | 2015-04-15 | 天津天保电力有限公司 | There is the clock system of IRIG-B time adjustment function |
CN106527576A (en) * | 2016-12-01 | 2017-03-22 | 郑州云海信息技术有限公司 | Clock separation designing method and system for PCIE device |
CN108008623A (en) * | 2017-12-08 | 2018-05-08 | 北京强度环境研究所 | Timing System and the method that Timing Signal is provided |
CN109189706A (en) * | 2018-09-28 | 2019-01-11 | 天津市英贝特航天科技有限公司 | A kind of multichannel programmable differential timing interface module and working method based on OpenVPX |
Non-Patent Citations (2)
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唐彬: "基于PCI-E的嵌入式B码时统终端研究与设计", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
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