CN110727583B - Method for constructing verification environment based on extensible verification component - Google Patents
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Abstract
The invention relates to the technical field of chip verification, in particular to a method for constructing a verification environment based on an extensible verification component. The invention is realized by the following technical scheme: a method for building a verification environment based on extensible verification components comprises the following steps: and an environment component sorting step: analyzing the environment components, and sequencing according to the expandability and universality of the components; element layering: the system is divided into a plurality of element layers from bottom to bottom, and the element with the best expandability and universality is placed at the bottom layer; a verification component forming step; a verification environment framework definition step: and filling the verification components by using a script component library to form a verification environment for actual operation. The invention aims to provide a method for constructing a verification environment based on an extensible verification component, which can be used for rapidly constructing the verification environment in a targeted manner even in the face of verification of a complex chip, and greatly improving the construction efficiency of the verification environment.
Description
Technical Field
The invention relates to the technical field of chip verification, in particular to a method for constructing a verification environment based on an extensible verification component.
Background
The SOC, i.e. the System on Chip, is called a System on Chip or a System on Chip, and the design verification process of the SOC is very important, which affects not only the successful design of the Chip, but also the Time To Market (TTM) of the Chip, and the correct completion of verification and the reduction of Time consumption become the keys of SOC design. The basic work in the chip verification field of the chip verification environment improves the verification efficiency of the SoC chip and shortens the research and development time; the design risk of the complex chip is reduced, and the correctness of the chip is ensured.
The verification process of the complex chip is large in scale, and the verification TTR (Time To Result) is also required To be as small as possible. Therefore, the verification environment needs to be constructed quickly, and the correctness of the environment needs to be high, so that errors in design can be found more quickly and better, and the development time of a chip is shortened.
In conventional chip functional verification, a verification engineer needs to develop a large number of tests to observe and check errors in the chip design by a manual method. However, when the chip scale is developed to a certain extent, this method is obviously no longer satisfactory for the product. At this stage, as a chip verification platform disclosed in chinese patent document No. 106202638A, a UVM platform of a chip to be verified is built using a UVM, i.e., a universal verification methodology. The method is a more common verification technical means in the industry, and the virtual model is developed, and the incentive has better reusability and inheritance, but the technical scheme still has a defect in the link of how to construct a verification environment.
In different projects, elements of a verification environment, such as a target design, a verification tool, a verification method, and the like, are different. Often, the verification engineer needs to build a customized verification environment to match the design and verification elements by means of the verification elements. Therefore, the technical defect of poor expansibility is formed, and particularly, when a complex chip is used by adopting hierarchical and various verification technical means, a plurality of verification environments need to be constructed, and the environment construction efficiency is particularly important.
Disclosure of Invention
The invention aims to provide a method for constructing a verification environment based on an extensible verification component, which can be used for rapidly constructing the verification environment in a targeted manner even in the face of verification of a complex chip, and greatly improving the construction efficiency of the verification environment.
The technical purpose of the invention is realized by the following technical scheme: a method for constructing a verification environment based on extensible verification components comprises the following steps:
s01, an environment component element sorting step:
analyzing the desired environment components, and sequencing according to the expandability and universality of all the components;
s02, element layering:
the system is divided into a plurality of element layers from top to bottom, and the element with the best expandability and universality is placed at the bottom layer;
s03, verifying component forming:
converting all the constituent elements of each element layer into independent verification components;
s04, defining a verification environment framework:
and filling the verification components by using a script component library to form a verification environment for actual operation.
In the step of S02 and element layering, the element is preferably divided into three element layers, namely, a bottom layer, a middle layer and an upper layer.
Preferably, the verification component at the bottom layer comprises a simulation tool component and a waveform tracking component.
Preferably, the verification component located at the bottom layer further comprises a coverage rate collection analysis component and a result retrieval component.
Preferably, the verification component located in the middle layer includes a virtual model component, an excitation component, a verification component and a parameter component.
Preferably, the verification component located at the upper layer includes a design component to be tested and a testbench component.
As the optimization of the invention, different verification environments are set up, and the verification assemblies in the bottom layer are directly used; the verification component of the middle layer is reconstructed into a customized component according to requirements; the verification component of the upper layer is redesigned as required.
In conclusion, the invention has the following beneficial effects:
when the complex chip is verified, various verification environments can be quickly established and verified, functions of different simulation tools, different verification scenes, different verification requirements and the like are comprehensively supported, and by utilizing good expandability and inheritance of the verification assembly, a user-defined verification assembly can be quickly developed according to requirements, functions of the verification environment are expanded, and the establishment efficiency of the verification environment is greatly improved.
Description of the drawings:
FIG. 1 is a schematic diagram of the first embodiment.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
The present embodiment is only for explaining the present invention, and it is not limited to the present invention, and those skilled in the art can make modifications without inventive contribution to the present embodiment as required after reading the present specification, but all of them are protected by patent law within the scope of the present invention.
Embodiment 1, a method for constructing a verification environment based on an extensible verification component, first, an environment component ordering step. The environment composition elements of the verification environment are many, for example, the elements comprise a design to be tested, excitation, verification, a virtual model, waveform tracking, coverage rate collection analysis, a simulation tool and the like, and the elements are layered according to the expandability and the universal capability of the elements, wherein the elements with high universality are used as the bottom layer, the elements with low expandability are used as the bottom layer, and the elements with low universality are used as the top layer.
As shown in fig. 1, in the present case, it is divided into three layers, a bottom layer, a middle layer and an upper layer. And the environment constituents of each layer are transformed into independent verification components. The process may adopt object-oriented, UVM and other technologies in the prior art, which are contents in the prior art, and detailed description is not given in the present application. The verification components have independence and do not depend on each other.
The verification components in different layers differ. As shown in FIG. 1, the verification components at the bottom layer include a simulation tool component, a waveform tracking component, a coverage collection analysis component, and a result retrieval component. These components need not be modified in any verification environment and can be used directly.
The simulation tool component comprises the calling of various simulation tools and supports the currently common VCS, IES and MODELSIM, and the waveform tracking component comprises a generated waveform file format, a name, a waveform recording size, waveform recording time, a waveform recording signal type, a waveform recording design level and the like. The coverage collection analysis component can specify a coverage type, a coverage generation module. The result retrieval component is responsible for retrieving the operation result, judges the correctness of the operation result through the printing standard of each component in the retrieval operation process, and supports the user to specify any information needing to be retrieved.
In fig. 1, the middle, intermediate layer assembly. The system comprises four components, namely a virtual model component, an excitation component, a verification component and a parameter component. The four components are realized based on object-oriented or UVM, have good inheritance and expandability, and can be quickly reconstructed into corresponding customized components according to requirements in different verification environments.
And the top layer in fig. 1 is the upper assembly. In this embodiment, the device under test and the TestBench component are included. These two components are related to the actual verification object and need to be written by the software designer.
And after the steps are completed, entering the last step, and verifying the environment framework definition step. In this step, each verification component has a corresponding position in the frame, and all the verification components are filled by using the script component library, so that a verification environment capable of being actually operated is formed. When different verification environments are built, different verification environments can be derived quickly only by replacing different verification components, different functions can be called for the component library at the bottom layer through command parameters during environment operation, and redevelopment is not needed.
The technical scheme abstracts the constituent elements of the verification environment into verification components, defines a set of verification environment framework and accommodates all the verification components. By adopting the object-oriented technology, a series of verification components with good development expansibility and strong inheritance can be developed, and the script component can be realized by python, so that a verification environment framework is realized, and each verification component can be automatically filled to construct a verification environment. Therefore, when the complex chip verification is faced, various verification environments can be quickly constructed and verified, functions of different simulation tools, different verification scenes, different verification requirements and the like are comprehensively supported, the user-defined verification component can be quickly developed according to the requirements by utilizing the good expandability and inheritance of the verification component, the functions of the verification environment are expanded, and the construction efficiency of the verification environment is greatly improved.
Claims (5)
1. A method for building a verification environment based on extensible verification components is characterized by comprising the following steps: s01, environment component sorting: analyzing all environment components, and sequencing according to the expandability and universality of the components; s02, element layering: the system is divided into a plurality of element layers from top to bottom, and the element with the best expandability and universality is placed at the bottom layer; s03, verifying component formation: converting all the constituent elements of each of the element layers into independent verification components; s04, defining a verification environment framework: filling the verification assemblies by using a script assembly library to form a verification environment for actual operation, wherein in the step of S02 element layering, the verification assemblies are divided into three element layers, namely a bottom layer, a middle layer and an upper layer, different verification environments are set up, and the verification assemblies in the bottom layer are directly used; the verification component of the middle layer is reconstructed into a customized component according to requirements; the verification component of the upper layer is redesigned as required.
2. The method for building a verification environment based on extensible verification components according to claim 1, wherein: the verification component at the bottom layer includes a simulation tool component and a waveform tracking component.
3. The method for building a verification environment based on extensible verification components according to claim 2, wherein: the verification component at the bottom layer also includes a coverage component and a result retrieval component.
4. The method for building a verification environment based on extensible verification components according to claim 1, wherein: the verification component located in the middle layer comprises a virtual model component, an excitation component, a verification component and a parameter component.
5. The method for building a verification environment based on extensible verification components according to claim 1, wherein: the verification component positioned on the upper layer comprises a design component to be tested and a testbench component.
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| CN107563025A (en) * | 2017-08-18 | 2018-01-09 | 北京东土军悦科技有限公司 | A kind of verification platform management method and device |
| CN108038294A (en) * | 2017-12-06 | 2018-05-15 | 北京松果电子有限公司 | UVM environmental structure method and systems |
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| CN107563025A (en) * | 2017-08-18 | 2018-01-09 | 北京东土军悦科技有限公司 | A kind of verification platform management method and device |
| CN108038294A (en) * | 2017-12-06 | 2018-05-15 | 北京松果电子有限公司 | UVM environmental structure method and systems |
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