CN110718587B - Semiconductor device and manufacturing method - Google Patents
Semiconductor device and manufacturing method Download PDFInfo
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- CN110718587B CN110718587B CN201810768931.4A CN201810768931A CN110718587B CN 110718587 B CN110718587 B CN 110718587B CN 201810768931 A CN201810768931 A CN 201810768931A CN 110718587 B CN110718587 B CN 110718587B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 193
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000002955 isolation Methods 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000002161 passivation Methods 0.000 claims abstract description 50
- 239000000463 material Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 13
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910002704 AlGaN Inorganic materials 0.000 claims description 4
- BYFGZMCJNACEKR-UHFFFAOYSA-N aluminium(i) oxide Chemical compound [Al]O[Al] BYFGZMCJNACEKR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229910004541 SiN Inorganic materials 0.000 claims 1
- 229910005883 NiSi Inorganic materials 0.000 abstract description 7
- 230000002829 reductive effect Effects 0.000 abstract description 7
- 150000001875 compounds Chemical class 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 14
- 238000010586 diagram Methods 0.000 description 9
- 229910002601 GaN Inorganic materials 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 5
- 238000000926 separation method Methods 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
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- 125000006850 spacer group Chemical group 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
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- 150000004767 nitrides Chemical class 0.000 description 1
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- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
- H01L29/475—Schottky barrier electrodes on AIII-BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The embodiment of the application provides a semiconductor device and a manufacturing method. The semiconductor device includes: a substrate; a semiconductor layer disposed on the substrate; the first electrode and the second electrode are arranged on one side of the semiconductor layer, which is far away from the substrate; the surface passivation dielectric layer is arranged on one side, far away from the substrate, of the semiconductor layer and is positioned between the first electrode and the second electrode; and the isolation layer is arranged on one side of the semiconductor layer, which is far away from the substrate, is positioned between the first electrode and the surface passivation dielectric layer and is used for isolating the first electrode from the surface passivation dielectric layer. The surface passivation dielectric layer is isolated from the first electrode through the isolation layer, so that the formation of a NiSi compound can be well inhibited, the Schottky junction quality of the first electrode is improved, the electric leakage is reduced, and the reliability of the device is improved.
Description
Technical Field
The application relates to the technical field of semiconductor and semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method.
Background
The reliability requirements of high electron mobility devices widely applied to the fields of radio frequency, microwave and power electronics are high. Especially, the study on the reliability of high temperature, high frequency, high voltage and high power devices has become one of the research hotspots in the field of semiconductor devices at present. Such as gallium nitride high electron mobility devices and gallium arsenide high electron mobility devices, the process design of the metal electrode in schottky contact with the semiconductor layer is related to the reliability level of the electronic device. Because the performance of the metal electrode is mainly influenced by the electric field at the edge of the electrode and the ambient temperature, the performance of the metal electrode of the electronic device is easily degraded, the Schottky leakage is increased, and the pressure-bearing capacity of the electronic device is inhibited.
In the prior art, a nickel-gold-NiAu metal lamination process is often used to form a good schottky contact with a semiconductor interface. In order to improve the quality of the semiconductor surface, a surface passivation layer of a silicide, such as silicon nitride (SiN), is often used. However, the contact between nickel Ni and silicon nitride easily forms silicide NiSi of Ni, the work function of NiSi is lower than that of metal Ni and can reduce the dielectric constant of the original silicon nitride, thereby resulting in the reduction of schottky performance of the metal electrode, the increase of leakage current of the metal electrode, even the failure of the metal electrode, and the serious influence on the reliability of the device.
Therefore, how to isolate Ni in the metal electrode from the surface passivation dielectric layer, but ensure high-quality schottky contact and passivation performance of the semiconductor surface, is a technical problem to be solved urgently.
Disclosure of Invention
In view of the above, it is an object of the present application to provide a semiconductor device and a method for manufacturing the same, so as to solve the above problems.
In a first aspect, embodiments of the present application provide a semiconductor device, including:
a substrate;
a semiconductor layer disposed on the substrate;
the first electrode and the second electrode are arranged on one side of the semiconductor layer, which is far away from the substrate;
the surface passivation dielectric layer is arranged on one side, far away from the substrate, of the semiconductor layer and is positioned between the first electrode and the second electrode; and
and the isolation layer is arranged on one side of the semiconductor layer, which is far away from the substrate, and is positioned between the first electrode and the surface passivation dielectric layer and used for isolating the first electrode from the surface passivation dielectric layer.
Optionally, in this embodiment, a height of the isolation layer in a direction perpendicular to the semiconductor layer is greater than a height of the passivation dielectric layer in the direction perpendicular to the semiconductor layer.
Optionally, in this embodiment, a width of the isolation layer between the first electrode and the surface passivation dielectric layer is not less than 50 nm.
Optionally, in this embodiment, the isolation layer extends toward the first electrode at a position close to the semiconductor layer to reduce a contact surface between the first electrode and the semiconductor layer.
Optionally, in this embodiment, the isolation layer extends completely towards the first electrode at a position close to the semiconductor layer, and the first electrode and the semiconductor layer are completely isolated by the isolation layer.
Optionally, a thickness of a portion of the isolation layer extending toward the first electrode at a position close to the semiconductor layer is in a range of 5nm to 50 nm.
Optionally, the isolation layer and the semiconductor layer form a PN junction.
Optionally, in this embodiment, the isolation layer is made of a P-type semiconductor material, and the P-type semiconductor material includes P-GaN and P-AlGaN.
Optionally, in this embodiment, the material of the first electrode is Ni or Ni/Au, or a combination of Ni and a single or multiple metals.
Optionally, in this embodiment, the material of the surface passivation layer is one or more of SiN, SiO2, SiON, and Al2O 3.
Optionally, in this embodiment, the semiconductor device is a diode, the first electrode is an anode of the diode, the second electrode is a cathode of the diode, and the surface passivation dielectric layer is disposed between the anode and the cathode.
Optionally, in this embodiment, the semiconductor device is a triode, the first electrode is a gate of the triode, the second electrode is a source and a drain of the triode, and the surface passivation dielectric layer is disposed between the source and the gate and between the drain and the gate.
In a second aspect, an embodiment of the present application further provides a method for manufacturing a semiconductor device, where the method includes:
providing a substrate;
depositing a semiconductor layer comprising a first semiconductor layer and a second semiconductor layer in sequence on one side of the substrate;
forming an isolation layer on one side of the semiconductor layer far away from the substrate;
removing the appointed part in the isolation layer through an etching process, and reserving the isolation layer for Schottky with the first electrode;
forming a second electrode in ohmic contact with the semiconductor layer on the side of the semiconductor layer away from the substrate;
forming the first electrode in the isolation layer or between the isolation layer and the semiconductor layer, wherein the first electrode is in schottky contact with the isolation layer or the semiconductor layer;
and forming a surface passivation dielectric layer on the surface of the semiconductor layer between the isolation layer and the second electrode.
The embodiment of the application provides a semiconductor device and a manufacturing method. The semiconductor device includes: a substrate; a semiconductor layer disposed on the substrate; the first electrode and the second electrode are arranged on one side of the semiconductor layer, which is far away from the substrate; the surface passivation dielectric layer is arranged on one side, far away from the substrate, of the semiconductor layer and is positioned between the first electrode and the second electrode; and the isolation layer is arranged on one side of the semiconductor layer, which is far away from the substrate, is positioned between the first electrode and the surface passivation dielectric layer and is used for isolating the first electrode from the surface passivation dielectric layer. The surface passivation dielectric layer is isolated from the first electrode through the isolation layer, so that the formation of a NiSi compound can be well inhibited, the Schottky junction quality of the first electrode is improved, the electric leakage is reduced, and the reliability of the device is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below. It is appreciated that the following drawings depict only certain embodiments of the application and are therefore not to be considered limiting of its scope, for those skilled in the art will be able to derive additional related drawings therefrom without the benefit of the inventive faculty.
Fig. 1 is a schematic structural diagram of a first semiconductor device according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a second semiconductor device according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a third semiconductor device provided in an embodiment of the present application;
fig. 4 is a schematic structural diagram of a fourth semiconductor device provided in an embodiment of the present application;
FIG. 5 is a flowchart illustrating a process of fabricating a semiconductor device according to an embodiment of the present disclosure;
fig. 6A to fig. 6E are process diagrams of the semiconductor device according to the embodiment of the present invention.
Icon: 11-a substrate; 12-a semiconductor layer; 121-a first semiconductor layer; 122-a second semiconductor layer; 123-two-dimensional electron gas; 13-a first electrode; 14-a second electrode; 15-surface passivation dielectric layer; 16-isolating layer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the described embodiments are merely a few embodiments of the present application and not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "upper", "lower", and the like refer to orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the present invention are conventionally placed in use, and are used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used solely to distinguish one from another, and are not to be construed as indicating or implying relative importance.
With the development of semiconductor device technology, the third generation wide bandgap semiconductor device technology with high frequency, high voltage and high reliability gradually becomes the core technology of the present semiconductor equipment system. The high-quality schottky junction or MIS (metal-insulator-semiconductor) structure gate is one of the key technologies for obtaining low leakage current and high reverse breakdown voltage characteristics, and also becomes the basic basis for judging the quality of semiconductor devices. Although various techniques for improving the quality of schottky junction or MIS structure gate of a device, and for improving reverse leakage and breakdown voltage have been reported in the semiconductor technology field, there is still a great technical space for further optimization.
Therefore, how to further inhibit the performance degradation of the schottky junction or the MIS structure gate, improve the reliability of the schottky junction or the MIS structure gate, reduce the leakage current of the semiconductor device under the reverse bias voltage, improve the withstand voltage characteristic, and improve the reliability becomes a technical problem to be solved urgently.
In order to solve the above problem, embodiments of the present application provide a semiconductor device described below. The semiconductor device includes: a substrate;
a semiconductor layer disposed on the substrate;
the first electrode and the second electrode are arranged on one side of the semiconductor layer, which is far away from the substrate;
the surface passivation dielectric layer is arranged on one side of the semiconductor layer, which is far away from the substrate, and is positioned between the first electrode and the second electrode; and
and the isolation layer is arranged on one side of the semiconductor layer, which is far away from the substrate, and is positioned between the first electrode and the surface passivation dielectric layer and used for isolating the first electrode from the surface passivation dielectric layer.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device is a triode and comprises a substrate 11, a semiconductor layer 12, a first electrode 13, a second electrode 14, a surface passivation dielectric layer 15 and an isolation layer 16.
The material of the substrate 11 may be gallium nitride, Silicon, sapphire, Silicon nitride, aluminum nitride, SOI (Silicon-On-Insulator), or other material that can epitaxially grow a III-V nitride.
The semiconductor layer 12 includes a first semiconductor layer 121 and a second semiconductor layer 122. The first semiconductor layer 121 is located on one side of the substrate 11, and it is understood that a combination of one or more of a nucleation layer, a buffer layer, or a back barrier layer may also be sequentially deposited between the first semiconductor layer 121 and the substrate 11. The embodiment of the present application does not limit the specific structure between the substrate 11 and the first semiconductor layer 121.
The second semiconductor layer 122 is located on a side of the first semiconductor layer 121 away from the substrate 11, a forbidden bandwidth of the first semiconductor layer 121 is smaller than a forbidden bandwidth of the second semiconductor layer 122, the first semiconductor layer 121 may be gallium nitride (GaN), the second semiconductor layer 122 may be aluminum gallium nitride (AlGaN), and a two-dimensional electron gas 123 is formed at an interface between the first semiconductor layer 121 and the second semiconductor layer 122.
The isolation layer 16 is located on the surface of the second semiconductor layer 122 far from the substrate 11, and the material of the isolation layer 16 may be a P-type material, P-gallium nitride or P-aluminum gallium nitride, which is opposite in electrical property to the first semiconductor layer 121 and the second semiconductor layer 122. In the present embodiment, the isolation layer 16 and the second semiconductor layer 122 form a recess.
In the semiconductor device structure, the first electrode 13 is a gate electrode, and the second electrode 14 includes a source electrode of a transistor and a drain electrode of the transistor. The source of the transistor and the drain of the transistor are disposed on opposite sides of the second semiconductor layer 122.
The first electrode 13 is disposed in a recess formed by the isolation layer 16 and the second semiconductor layer 122, and it is understood that the surface of the first electrode 13 and/or the isolation layer 16 near the substrate side may extend into the second semiconductor layer 122, and the first electrode 13 is in schottky contact with the isolation layer 16 or/and the second semiconductor layer 122, respectively. The first electrode may be formed of a metal stack of Ni, Ni/Au, or Ni/Au/Ti.
The surface passivation dielectric layer 15 is disposed on the second semiconductor layer 122 between the isolation layer 16 and the source, and between the isolation layer 16 and the drain. The material of the surface passivation dielectric layer 15 may be a silicide dielectric, such as SiN, SiO2, etc.
The height of the isolation layer 16 in the direction vertical to the semiconductor layer 12 is higher than that of the surface passivation dielectric layer 15, and preferably, the height in the direction vertical to the semiconductor layer 12 is at least 5nm higher. The height of the isolation layer 16 is set higher than that of the surface passivation dielectric layer 15, so that the surface passivation dielectric layer 15 can be prevented from contacting the first electrode.
In the embodiment of the present application, the isolation layer 16 is made of P-gan or P-algan, which can effectively isolate the contact between the surface passivation dielectric layer 15 and the first electrode 13. Further, in the present embodiment, the width of the isolation layer 16 between the first electrode 13 and the surface passivation dielectric layer 15 is not less than 50 nm. The above arrangement ensures that the isolation layer 16 adequately isolates the first electrode 13 from the surface passivation dielectric layer 15. So that the Ni metal element in the first electrode 13 and the Si element in the surface passivation dielectric layer 15 can not react to form a compound NiSi, thereby inhibiting the formation of the NiSi compound, improving the quality of a Schottky junction formed by the first electrode 13 and the semiconductor layer 12, reducing electric leakage and improving the reliability of the device. Meanwhile, as the P-type isolation layer 16 forms a PN junction with the second semiconductor layer 12, the electron leakage of the schottky junction or the interface between the edge of the first electrode and the second semiconductor layer 12 can be effectively inhibited, the quality of the first electrode 13 is further improved, the leakage is reduced, and the pressure-bearing capacity of the semiconductor device is improved.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating a second structure of a semiconductor device according to an embodiment of the present disclosure.
The second semiconductor device has a triode structure, and is different from the first semiconductor device in that the spacer 16 extends toward the first electrode 13 in a direction parallel to the semiconductor layer at a position close to the semiconductor layer 12, and a portion of the spacer 16 extending toward the first electrode 13 is in surface schottky contact with the first electrode 13 in contact with the extended portion. In this embodiment, the isolation layer 16 extends toward the first electrode 13 at a position close to the semiconductor layer 12 to reduce the contact area between the first electrode 13 and the semiconductor layer 12, and the portion of the isolation layer 16 extending toward the first electrode 13 never isolates the first electrode to completely isolate the first electrode.
The second semiconductor device structure improvement has the advantages that: the extension of the isolation layer 16 relative to the first electrode 13 and the second semiconductor layer 122 form a PN junction, so that leakage of electrons on the first electrode 13 can be better suppressed. Compared with the first structure, on the basis of ensuring and inhibiting the performance degradation of the first electrode 13, the leakage of the Schottky junction formed by the first electrode 13 and the semiconductor layer 12 can be further reduced, and the pressure bearing capacity of the whole semiconductor device is improved.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating a third structure of a semiconductor device according to an embodiment of the present disclosure.
The third semiconductor device is also a triode structure, and unlike the second schematic structure, the third embodiment provides a semiconductor device structure in which the isolation layer 16 extends toward the first electrode 13 at a position close to the semiconductor layer 12 to completely isolate the contact between the first electrode 13 and the semiconductor layer 12, that is, the isolation layer 16 is located between the first electrode 13 and the semiconductor layer 12, and is used for isolating the first electrode 13 from the semiconductor layer 12. In this structure, the thickness of the separation layer 16 between the first electrode 13 and the semiconductor layer 12 is in the range of 5nm to 50 nm.
The third structural modification of the semiconductor device has the advantages that the first electrode 13 is completely separated from the second semiconductor layer 122 and the surface passivation dielectric layer 15 by the separation layer 16, the separation layer 16 forms a PN junction with the second semiconductor layer 122, and the first electrode 13 forms a schottky contact with the separation layer 16. Compared with the second semiconductor device structure, on the basis of ensuring and inhibiting the performance degradation of the first electrode 13, the leakage current of the Schottky junction is further reduced due to the PN junction, and the bearing capacity of the semiconductor device is improved.
Referring to fig. 4, fig. 4 shows a fourth structural diagram of the semiconductor device according to the embodiment of the present application.
As shown in fig. 4, unlike the three semiconductor device structures, the fourth semiconductor device structure is a schottky diode structure, and the first electrode 13 corresponds to an anode of the diode and the second electrode corresponds to a cathode of the diode. The first electrode 13 is effectively isolated from the surface passivation dielectric layer 15 by the isolation layer 16, and the isolation layer 16 and the second semiconductor layer 122 form a PN junction. The invention adopts the isolation layer 16 to improve the anode performance of the Schottky diode device and improve the bearing capacity and reliability of the Schottky diode.
The embodiment of the present application further provides a method for manufacturing a semiconductor device, which is explained below by taking the manufacturing of the semiconductor device in fig. 1 as an example, and the method includes the following steps:
in step S501, a substrate 11 is provided.
In step S502, referring to fig. 6A, a semiconductor layer 12 including a first semiconductor layer 121 and a second semiconductor layer 122 is sequentially deposited on one side of a substrate 11.
In step S503, referring to fig. 6B, an isolation layer 16 is formed on the semiconductor layer 12 at a side away from the substrate 11.
In step S504, referring to fig. 6C, a specific portion of the isolation layer 16 is removed by an etching process, and the isolation layer 16 for contacting the first electrode 13 is remained.
In step S505, referring to fig. 6D, a second electrode 14 in ohmic contact with the semiconductor layer is formed on the semiconductor layer 12 at a side away from the substrate 11.
Step S506, referring to fig. 6E or fig. 1, forming the first electrode 13 in the isolation layer 16 or between the isolation layer 16 and the semiconductor layer 12, wherein the first electrode 13 is in schottky contact with the isolation layer 16 or the semiconductor layer 12;
in step S507, referring to fig. 6E or fig. 1 again, a surface passivation dielectric layer 15 is formed on the surface of the semiconductor layer 12 between the isolation layer 16 and the second electrode 14.
The embodiment of the application provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate; a semiconductor layer disposed on the substrate. The first electrode and the second electrode are arranged on one side, far away from the substrate, of the semiconductor layer, the first electrode is in Schottky contact with the semiconductor layer, and the second electrode is in ohmic contact with the semiconductor layer. And the surface passivation dielectric layer is arranged on one side of the semiconductor layer, which is far away from the substrate, and is positioned between the first electrode and the second electrode. And the isolation layer is arranged on one side of the semiconductor layer, which is far away from the substrate, is positioned between the first electrode and the surface passivation dielectric layer and is used for isolating the first electrode from the surface passivation dielectric layer. The isolation layer (such as P-GaN or P-AlGaN) is adopted to isolate the surface passivation dielectric layer of the silicide from the first electrode containing Ni metal elements, so that the formation of NiSi compounds can be well inhibited, the quality of Schottky junctions formed by the first electrode and the semiconductor layer is improved, the electric leakage is reduced, and the reliability of the device is improved. Meanwhile, as the P-type isolation layer and the semiconductor layer form a PN junction, the electron leakage of the Schottky junction or the interface between the edge of the first electrode and the semiconductor layer can be effectively inhibited, the quality of the Schottky junction MIS structure is further improved, the electric leakage is reduced, and the pressure bearing capacity of the device is improved.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (11)
1. A semiconductor device, comprising:
a substrate;
a semiconductor layer disposed on the substrate;
the first electrode and the second electrode are arranged on one side of the semiconductor layer, which is far away from the substrate;
the surface passivation dielectric layer is arranged on one side, far away from the substrate, of the semiconductor layer and is positioned between the first electrode and the second electrode; and
the isolation layer is arranged on one side, far away from the substrate, of the semiconductor layer and is positioned between the first electrode and the surface passivation dielectric layer and used for isolating the first electrode from the surface passivation dielectric layer;
the isolation layer and the semiconductor layer form a PN junction, the isolation layer is made of a P-type semiconductor material, and the P-type semiconductor material comprises P-GaN and P-AlGaN.
2. The semiconductor device of claim 1, wherein a height of the isolation layer in a direction perpendicular to the semiconductor layer is greater than a height of the passivation dielectric layer in a direction perpendicular to the semiconductor layer.
3. The semiconductor device according to claim 1, wherein a width of the isolation layer between the first electrode and the surface passivation dielectric layer is not less than 50 nm.
4. The semiconductor device according to claim 1, wherein the isolation layer extends toward the first electrode at a position close to the semiconductor layer to reduce a contact surface of the first electrode with the semiconductor layer.
5. The semiconductor device according to claim 4, wherein the isolation layer extends completely toward the first electrode at a position close to the semiconductor layer, and the first electrode is completely isolated from the semiconductor layer by the isolation layer.
6. The semiconductor device according to claim 4, wherein a thickness of a portion of the isolation layer extending toward the first electrode at a position near the semiconductor layer is in a range of 5nm to 50 nm.
7. The semiconductor device according to claim 1, wherein a material of the first electrode is Ni or Ni/Au, or a combination of Ni and a single or a plurality of metals.
8. The semiconductor device of claim 1, wherein the material of the surface passivation layer is one or more of SiN, SiO2, SiON, Al2O 3.
9. The semiconductor device according to any one of claims 1 to 8, wherein the semiconductor device is a diode, the first electrode is an anode of the diode, the second electrode is a cathode of the diode, and the surface passivation dielectric layer is disposed between the anode and the cathode.
10. The semiconductor device according to any one of claims 1 to 8, wherein the semiconductor device is a transistor, the first electrode is a gate electrode of the transistor, the second electrode is a source electrode and a drain electrode of the transistor, and the surface passivation dielectric layer is provided between the source electrode and the gate electrode and between the drain electrode and the gate electrode.
11. A method of fabricating a semiconductor device, the method comprising:
providing a substrate;
depositing a semiconductor layer comprising a first semiconductor layer and a second semiconductor layer in sequence on one side of the substrate;
forming an isolation layer on one side of the semiconductor layer far away from the substrate;
removing a designated part in the isolation layer through an etching process, and reserving the isolation layer for contacting with the first electrode;
forming a second electrode in ohmic contact with the semiconductor layer on the side far away from the substrate;
forming the first electrode in the isolation layer or between the isolation layer and the semiconductor layer, wherein the first electrode is in schottky contact with the isolation layer or the semiconductor layer;
forming a surface passivation dielectric layer on the surface of the semiconductor layer between the isolation layer and the second electrode;
the isolation layer and the semiconductor layer form a PN junction, the isolation layer is made of a P-type semiconductor material, and the P-type semiconductor material comprises P-GaN and P-AlGaN.
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| US20150318387A1 (en) * | 2014-04-30 | 2015-11-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Sidewall Passivation for HEMT Devices |
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| US20150318387A1 (en) * | 2014-04-30 | 2015-11-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Sidewall Passivation for HEMT Devices |
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