CN110718262A - Method, device and storage medium for positioning rank where fault memory particles are located - Google Patents
Method, device and storage medium for positioning rank where fault memory particles are located Download PDFInfo
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- G—PHYSICS
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
Abstract
The application relates to a method, a device and a storage medium for positioning rank where a fault memory particle is located, wherein the method comprises the following steps: acquiring a rank mapping table, acquiring an error reporting address corresponding to a target fault memory granule on a target dual rank memory strip, acquiring rank address bits in the error reporting address according to the rank mapping table, acquiring values corresponding to the rank address bits in the error reporting address to obtain rank addresses corresponding to ranks where the target fault memory granule is located, and locating the ranks where the target fault memory granule is located on the target dual rank memory strip according to the rank addresses corresponding to the ranks where the target fault memory granule is located and the rank mapping table. By the method, which rank the fault memory particles on the fault memory bank are on the fault memory bank can be quickly positioned.
Description
Technical Field
The present application relates to the field of storage device technologies, and in particular, to a method, an apparatus, and a storage medium for locating rank where a failure memory granule is located.
Background
In the process of testing dual rank (dual rank) memory banks, such as DDR production, a motherboard is often used for memory bank testing. However, when one dual rank memory bank tests and reports errors on one main board, the CPU only records the logic address where the fault occurs, and for the same dual rank memory bank, when memory particles at corresponding positions on different ranks have faults, values corresponding to rows, columns, and banks in the logic address sent by the CPU are the same, and only values corresponding to ranks are different.
Disclosure of Invention
In order to solve the above technical problems or at least partially solve the above technical problems, the present application provides a method, an apparatus, and a storage medium for locating rank where a failed memory granule is located.
In a first aspect, the present application provides a method for locating rank where a fault memory granule is located, where the method includes:
acquiring a rank mapping table, wherein the rank mapping table represents a one-to-one mapping relation among ranks, rank address bits and rank addresses on a dual rank memory bank tested on the same mainboard;
acquiring an error reporting address corresponding to a target fault memory particle on a target dual rank memory bank;
acquiring rank address bits in the error reporting address according to the rank mapping table;
obtaining a value corresponding to a rank address bit in the error reporting address to obtain a rank address corresponding to a rank where the target fault memory granule is located;
and positioning the rank of the target fault memory granule on the target dual rank memory strip according to the rank address corresponding to the rank of the target fault memory granule and the rank mapping table.
Preferably, the obtaining a rank mapping table, where the rank mapping table represents a one-to-one mapping relationship among ranks, rank address bits, and rank addresses on a dual rank memory bank tested on the same motherboard, includes:
acquiring a fault memory bank, wherein the fault memory bank is a dual rank memory bank and only has one fault memory granule, the fault memory granule only has one minimum storage unit which makes a fault, and the fault memory bank and the target dual rank memory bank use the same mainboard and CPU to carry out testing;
acquiring rank address bits of rank on the fault memory bank;
obtaining values corresponding to rank address bits when the fault memory granules are located in different ranks of the fault memory bank, and taking the values corresponding to the rank address bits as rank addresses corresponding to the ranks;
and mapping rank, rank address bits and rank addresses on the fault memory bank one by one to generate a rank mapping table, wherein the rank mapping table represents the one-to-one mapping relation of the rank, the rank address bits and the rank addresses on the dual rank memory banks tested on the same mainboard, and the rank address bits and the rank addresses corresponding to the same rank are the same when different dual rank memory banks are tested on the mainboard.
Preferably, the acquiring a failed memory bank, where the failed memory bank is a dual rank memory bank and has only one failed memory granule, and the failed memory granule has only one smallest storage unit which has an error, includes:
simultaneously writing data into each memory particle of a memory bank to be tested, wherein the memory bank to be tested is a single rank memory bank;
simultaneously reading data of each memory particle of the memory bank to be tested, in which data are written, to obtain read data;
respectively comparing the write-in data and the corresponding read-out data of each memory particle of the memory bank to be tested;
taking the memory particles with the written data and the corresponding read data with only one different bit as the fault memory particles with only one error of the minimum storage unit;
and acquiring a fault-free dual rank memory bank, and replacing any fault-free memory granule of the fault-free dual rank memory bank by the fault memory granule to change the fault-free dual rank memory bank into a fault memory bank with only one fault memory granule.
Preferably, the acquiring a failed memory bank, where the failed memory bank is a dual rank memory bank and has only one failed memory granule, and the failed memory granule has only one smallest storage unit which has an error, includes:
obtaining a plurality of single memory particles to be tested, and respectively writing data into the plurality of memory particles to be tested;
respectively reading data of the plurality of to-be-detected memory particles with written data to obtain read data;
respectively comparing the written data of the memory particles to be detected with the corresponding read data;
taking the memory particles with the written data and the corresponding read data with only one different bit as the fault memory particles with only one error of the minimum storage unit;
and acquiring a fault-free dual rank memory bank, and replacing any fault-free memory granule of the fault-free dual rank memory bank by the fault memory granule to change the fault-free dual rank memory bank into a fault memory bank with only one fault memory granule.
Preferably, the acquiring a fault-free dual rank memory bank includes:
respectively performing data writing operation on a plurality of dual rank memory banks to be tested;
respectively reading data from the multiple dual rank to-be-tested memory banks with written data to obtain read data;
respectively comparing the written data and the corresponding read data of each dual rank memory bank to be tested;
and taking the dual rank memory bank to be tested with the same write-in data and the corresponding read-out data as a fault-free dual rank memory bank.
Preferably, the obtaining the rank address bit of the rank on the failed memory bank includes:
taking a rank where the fault memory granule is currently located on the fault memory bank as a first rank, taking another rank on the fault memory bank as a second rank, and taking the position of the fault memory granule on the first rank as a first position;
respectively acquiring error reporting addresses corresponding to positions, corresponding to the first position, of the fault memory granules on the first rank and the second rank of the first rank to obtain a first error reporting address and a second error reporting address;
and obtaining a difference bit of the first error reporting address and the second error reporting address, and using the difference bit as a rank address bit of a rank on the faulty memory bank, where the difference bit is a bit with a changed value corresponding to a same bit in the first error reporting address and the second error reporting address, and the rank address bits are the same when different memory banks are tested on the same motherboard.
Preferably, the obtaining the value corresponding to the rank address bit when the faulty memory granule is located in different ranks of the faulty memory bank, and using the value corresponding to the rank address bit as the rank address corresponding to the rank includes:
respectively obtaining values corresponding to the rank address bits in the first error reporting address and the second error reporting address obtained when the fault memory granule is located in different ranks of the fault memory bank, and respectively taking the values corresponding to the rank address bits as rank addresses corresponding to ranks on the fault memory bank, wherein the rank addresses corresponding to the same ranks of different memory banks are tested on the same mainboard by different memory banks, and the rank addresses corresponding to the same ranks of different memory banks are the same.
Preferably, the obtaining error reporting addresses corresponding to positions, corresponding to the first position, of the faulty memory particle on the first rank and the second rank of the first rank respectively to obtain a first error reporting address and a second error reporting address includes:
respectively acquiring the fault memory granules at the first position of a first rank and the memory granules at the position corresponding to the first position on a second rank to exchange, so that when the fault memory granules are at the corresponding positions of different ranks of the fault memory bank, the fault memory granules respectively detect a first error reporting address and a second error reporting address sent by a CPU (Central processing Unit) when the fault memory bank is detected.
Preferably, the locating the rank where the target failure memory granule is located on the target dual-rank memory strip according to the rank address corresponding to the rank where the target failure memory granule is located and the rank mapping table includes:
if the rank address corresponding to the rank where the target failure memory granule is located corresponds to the first rank in the rank mapping table, the target failure memory granule on the target dual rank memory bank is located on the first rank;
and if the rank address corresponding to the rank where the target fault memory granule is located corresponds to a second rank in the rank mapping table, the target fault memory granule on the target dual rank memory bank is located on the second rank.
In a second aspect, the present application further provides an apparatus for locating rank where a fault memory granule is located, where the apparatus includes:
the system comprises a mapping table obtaining unit, a mapping table obtaining unit and a mapping table determining unit, wherein the mapping table obtaining unit is used for obtaining a rank mapping table, and the rank mapping table represents a one-to-one mapping relation of ranks, rank address bits and rank addresses on a dual rank memory bank tested on the same mainboard;
the error reporting address acquisition unit is used for acquiring an error reporting address corresponding to a target fault memory particle on a target dual rank memory bank;
an address bit obtaining unit, configured to obtain a rank address bit in the error reporting address according to the rank mapping table;
an address obtaining unit, configured to obtain a value corresponding to a rank address bit in the error reporting address to obtain a rank address corresponding to a rank where the target faulty memory granule is located;
and the positioning unit is used for positioning the rank of the target fault memory granule on the target dual rank memory strip according to the rank address corresponding to the rank of the target fault memory granule and the rank mapping table.
In a third aspect, the present application also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, causes the processor to perform the steps of any of the methods described above.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:
the method for locating rank where a fault memory granule is located includes the steps that a first error reporting address and a second error reporting address sent by a CPU when the same fault memory granule on a fault memory strip is located at corresponding positions on different ranks on the fault memory strip are obtained, bits with the same bit value change in the first error reporting address and the second error reporting address are used as rank address bits corresponding to the rank, values corresponding to the rank address bits in the first error reporting address and the second error reporting address obtained by the fault memory granule on different ranks are used as rank addresses corresponding to the rank, and therefore the same corresponding relation among the memory strip rank, the rank address bits and the rank addresses tested on the same main board is obtained, and a rank mapping table is generated; when the memory banks are tested on the same mainboard, rank address bits and rank addresses corresponding to the same rank of different memory banks are the same, so that the generated rank mapping table is universal for the memory banks tested on the same mainboard; after the error reporting address of the target fault memory granule on the target fault memory bank is obtained, the rank of the target fault memory granule on the target fault memory bank can be quickly located through the error reporting address and the rank mapping table, so that the target fault memory granule can be conveniently and quickly found, and the fault memory bank can be maintained.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a flowchart of a method for locating rank where a fault memory granule is located according to the present application;
fig. 2 is a flowchart of another method for locating rank where a faulty memory granule is located according to the present application;
fig. 3 is a flowchart of another method for locating rank where a faulty memory granule is located according to the present application;
fig. 4 is a block diagram of a structure of an apparatus for locating rank where a fault memory granule is located according to the present application;
fig. 5 is an application scenario diagram provided in the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a flowchart of a method for locating rank where a fault memory granule is located according to the present application; referring to fig. 1, the method comprises the steps of:
s0100: acquiring a rank mapping table, wherein the rank mapping table represents a one-to-one mapping relation among ranks, rank address bits and rank addresses on a dual rank memory bank tested on the same mainboard;
s0200: acquiring an error reporting address corresponding to a target fault memory particle on a target dual rank memory bank;
s0300: acquiring rank address bits in the error reporting address according to the rank mapping table;
s0400: obtaining a value corresponding to a rank address bit in the error reporting address to obtain a rank address corresponding to a rank where the target fault memory granule is located;
s0500: and positioning the rank of the target fault memory granule on the target dual rank memory strip according to the rank address corresponding to the rank of the target fault memory granule and the rank mapping table.
Fig. 2 is a flowchart of another method for locating rank where a faulty memory granule is located according to the present application; referring to fig. 1 and fig. 2, based on the method for locating rank where a faulty memory granule is located provided in fig. 1, the step S0100 includes the following steps:
s0110: acquiring a fault memory bank, wherein the fault memory bank is a dual rank memory bank and only has one fault memory granule, the fault memory granule only has one minimum storage unit which makes a fault, and the fault memory bank and the target dual rank memory bank use the same mainboard and CPU to carry out testing;
s0120: acquiring rank address bits of rank on the fault memory bank;
s0130: obtaining values corresponding to rank address bits when the fault memory granules are located in different ranks of the fault memory bank, and taking the values corresponding to the rank address bits as rank addresses corresponding to the ranks;
s0140: and mapping rank, rank address bits and rank addresses on the fault memory bank one by one to generate a rank mapping table, wherein the rank mapping table represents the one-to-one mapping relation of the rank, the rank address bits and the rank addresses on the dual rank memory banks tested on the same mainboard, and the rank address bits and the rank addresses corresponding to the same rank are the same when different dual rank memory banks are tested on the mainboard.
Fig. 3 is a flowchart of another method for locating rank where a faulty memory granule is located according to the present application; referring to fig. 1, 2 and 3, based on the method for locating rank where the faulty memory particle is located provided in fig. 2, the step S0120 includes the following steps:
s0121: taking a rank where the fault memory granule is currently located on the fault memory bank as a first rank, taking another rank on the fault memory bank as a second rank, and taking the position of the fault memory granule on the first rank as a first position;
s0122: respectively acquiring error reporting addresses corresponding to positions, corresponding to the first position, of the fault memory granules on the first rank and the second rank of the first rank to obtain a first error reporting address and a second error reporting address;
s0123: and obtaining a difference bit of the first error reporting address and the second error reporting address, and using the difference bit as a rank address bit of a rank on the faulty memory bank, where the difference bit is a bit with a changed value corresponding to a same bit in the first error reporting address and the second error reporting address, and the rank address bits are the same when different memory banks are tested on the same motherboard.
Fig. 4 is a block diagram of a structure of an apparatus for locating rank where a fault memory granule is located according to the present application; the device comprises:
a mapping table obtaining unit 10, configured to obtain a rank mapping table, where the rank mapping table represents a one-to-one mapping relationship between ranks, rank address bits, and rank addresses on a dual rank memory bank tested on the same motherboard;
an error reporting address obtaining unit 20, configured to obtain an error reporting address corresponding to a target failure memory granule on a target dual rank memory bank;
an address bit obtaining unit 30, configured to obtain a rank address bit in the error reporting address according to the rank mapping table;
an address obtaining unit 40, configured to obtain a value corresponding to a rank address bit in the error reporting address to obtain a rank address corresponding to a rank where the target faulty memory granule is located;
and a positioning unit 50, configured to position the rank where the target failure memory granule is located on the target dual rank memory strip according to the rank address corresponding to the rank where the target failure memory granule is located and the rank mapping table.
In the production test of the memory bank, a main board is generally used to test the memory bank to detect whether the memory bank has a fault, when memory particles at corresponding positions on different ranks of the same memory bank have faults, values corresponding to rows, columns and banks in the error-reporting address generated by the CPU are the same, and the difference is the value corresponding to rank, so that it is necessary to determine which rank the faulty memory particle is located in order to locate the faulty memory particle. The method comprises the steps of obtaining an error reporting address corresponding to a fault memory particle sent by a CPU, and positioning which rank the fault memory particle is on through the error reporting address and a rank mapping table.
The Rank mapping table represents a one-to-one mapping relation among Rank, Rank address bits and Rank addresses on a dual Rank memory bank tested on the same mainboard, wherein the Rank addresses are values of Rank address bits of corresponding ranks on the dual Rank memory bank, and the Rank address bits and the Rank addresses corresponding to the same Rank of different dual Rank memory banks are the same as long as the memory bank test is performed on the same mainboard.
The error reporting address corresponding to the fault memory granule refers to a logic address corresponding to the fault memory granule sent by a memory controller of a CPU in the process of testing the memory bank, and when the memory bank is tested on the same mainboard, rank address bits in the error reporting address corresponding to the fault memory granules on the same rank position of different memory banks are the same, and rank addresses are the same.
The method comprises the steps that fault memory particles on a known fault memory bank respectively traverse corresponding positions of different ranks on the fault memory bank to obtain a first error reporting address and a second error reporting address, the first error reporting address and the second error reporting address are compared, and bits with changed values corresponding to the same bits in the error reporting addresses are used as rank address bits; the rank address bits may have 1 bit and 2 bits for different motherboards. And taking the value of the rank address bit corresponding to different ranks as the rank address corresponding to the rank, and mapping the rank address, the rank address bit and the rank one by one to generate a rank mapping table. This rank mapping table is common to dual rank memory banks tested on the same motherboard.
FIG. 5 is a diagram of a scene application provided by the present application; referring to fig. 1 to 5, a DDR memory bank having only one failed memory granule is obtained as a failed memory bank, where the failed memory granule has only one minimum memory cell with an error, and the minimum memory cell corresponds to one bit.
Specifically, data writing and data reading operations are independently performed on a plurality of DDR memory banks, the written data and the corresponding read data of each DDR memory bank are respectively compared, and the DDR memory bank with the same written data and the same corresponding read data is taken as a fault-free memory bank.
And simultaneously performing write-in data operation on each memory particle of the DDR memory bank, wherein the write-in data corresponding to each memory particle is known, simultaneously performing read-out data operation on each memory particle with the written-in data to obtain read-out data, respectively comparing the write-in data of each memory particle with the corresponding read-out data, and taking the memory particle with the write-in data and the corresponding read-out data which only has one bit different from each other as a fault memory particle with only one minimum storage unit error.
Or performing data writing operation and data reading operation on a plurality of single memory particles to be tested to obtain the written data and the corresponding read data of each memory particle to be tested, comparing the written data and the corresponding read data of each memory particle to be tested, and taking the memory particle with the written data and the corresponding read data which only have one bit difference as a fault memory particle with only one minimum storage unit error.
And replacing any one fault-free memory particle of the fault-free DDR memory bank by the fault memory particle to change the fault-free DDR memory bank into a fault memory bank with only one fault memory particle.
When different fault memory banks are tested on the same mainboard, rank address bits are the same, and rank addresses of the same ranks of different memory banks are also the same, where the same ranks of different memory banks refer to the same ranks judged according to the unified specification in the prior art, but are not limited to this.
For the same dual rank memory bank, when the memory particles at the corresponding positions on different ranks have faults, the values corresponding to the rows, the columns and the banks in the logic address sent by the CPU are the same, and only the values corresponding to the ranks are different.
Referring to fig. 5, there are 8 memory granules on each rank of the faulty memory bank, the rank where the faulty memory granule is currently located is defined as rank1, the current memory granule position of the faulty memory granule on rank1 is defined as U1, and 8 memory granules are located on rank1, and the memory granule positions are defined as U1-U8, respectively; defining another rank of the fault memory bank as rank2, wherein 8 memory granules are arranged on rank2, and the positions of the memory granules are respectively defined as U9-U16; the memory particles at the positions U1 and U9, U2 and U10, U3 and U11, U4 and U12, U5 and U13, U6 and U14, U7 and U15, and U8 and U16 are memory particles at corresponding positions of different ranks, respectively.
The method comprises the steps of installing a fault memory bank on a mainboard for memory bank detection, operating memory test software, writing data into all storage units of the fault memory bank through the memory test software, enabling the storage units of the memory bank to correspond to logical addresses in a system where a CPU is located, reading data corresponding to all the logical addresses through the test software to serve as read data, comparing all the written data with corresponding read data, selecting logical addresses different from the written data and the corresponding read data by the CPU to serve as error reporting addresses, and enabling the error reporting addresses to be the logical addresses corresponding to fault memory particles. At this time, the error Address sent by the CPU when the fault memory granule is at the position U1 of rank1 is obtained as Address1:0x4E5D12a 30.
Exchanging the fault memory granules located at the position U1 of rank1 with the non-fault memory granules located at the position U9 of rank2, wherein the position U1 and the position U9 are corresponding positions of different ranks; and operating memory test software to obtain the Address2:0x4E5D1AA30 of the error reporting Address sent by the CPU when the fault memory particle is at the position U9 of rank 2.
The Address1 and the Address2 are converted into binary systems for comparison, in the 36-bit logic Address, the difference bit is bit16 (from right to left, the first bit is bit1), and it can be determined that bit16 in the error reporting Address is the rank Address bit in the logic Address sent by the CPU system corresponding to the mainboard; when the fault memory granule is located at the position U1 of rank1, the value corresponding to the rank address bit16 is 0; when the fault memory granule is located at the position U9 of rank2, the value corresponding to the rank address bit16 is 1; when the value of bit16 is 0, it is rank1, that is, the rank address of rank1 is 0; when bit16 takes a value of 1, it is rank2, i.e. rank address of rank2 is 1.
The following rank mapping table is obtained:
preferably, the failed memory particles can be respectively replaced to any group of positions of U2 and U10, U3 and U11, U4 and U12, U5 and U13, U6 and U14, U7 and U15, and U8 and U16 for memory test, and the obtained corresponding error-reporting addresses are compared. And another failed memory bank can be used for testing for further verification.
When the memory bank test is performed on the same mainboard, if the memory bank has a fault, the rank where the fault particle in the fault memory bank is located can be located according to the value of bit16 in the fault address corresponding to the fault memory bank sent by the CPU and the rank mapping table.
The rank address bit corresponding to the mainboard test memory bank in the application scenario is bit16, and if different mainboards are replaced to perform the memory bank test, the rank address bit and the rank address corresponding to each rank need to be found out again.
By the method, the rank with the fault or the rank where the fault memory particle is located can be quickly positioned, detection time is saved, workers can conveniently and correctly position and maintain the fault memory particle, and the method has wide application prospect in production test of the memory bank.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for locating rank where a fault memory granule is located is characterized by comprising the following steps:
acquiring a rank mapping table, wherein the rank mapping table represents a one-to-one mapping relation among ranks, rank address bits and rank addresses on a dual rank memory bank tested on the same mainboard;
acquiring an error reporting address corresponding to a target fault memory particle on a target dual rank memory bank;
acquiring rank address bits in the error reporting address according to the rank mapping table;
obtaining a value corresponding to a rank address bit in the error reporting address to obtain a rank address corresponding to a rank where the target fault memory granule is located;
and positioning the rank of the target fault memory granule on the target dual rank memory strip according to the rank address corresponding to the rank of the target fault memory granule and the rank mapping table.
2. The method according to claim 1, wherein the obtaining a rank mapping table, which represents a one-to-one mapping relationship between ranks, rank address bits, and rank addresses on dual rank memory banks tested on the same motherboard, comprises:
acquiring a fault memory bank, wherein the fault memory bank is a dual rank memory bank and only has one fault memory granule, the fault memory granule only has one minimum storage unit which makes a fault, and the fault memory bank and the target dual rank memory bank use the same mainboard and CPU to carry out testing;
acquiring rank address bits of rank on the fault memory bank;
obtaining values corresponding to rank address bits when the fault memory granules are located in different ranks of the fault memory bank, and taking the values corresponding to the rank address bits as rank addresses corresponding to the ranks;
and mapping rank, rank address bits and rank addresses on the fault memory bank one by one to generate a rank mapping table, wherein the rank mapping table represents the one-to-one mapping relation of the rank, the rank address bits and the rank addresses on the dual rank memory banks tested on the same mainboard, and the rank address bits and the rank addresses corresponding to the same rank are the same when different dual rank memory banks are tested on the mainboard.
3. The method according to claim 2, wherein the obtaining a faulty memory bank, the faulty memory bank being a dual rank memory bank and having only one faulty memory granule, the faulty memory granule having only one smallest storage unit error comprises:
simultaneously writing data into each memory particle of a memory bank to be tested, wherein the memory bank to be tested is a single rank memory bank;
simultaneously reading data of each memory particle of the memory bank to be tested, in which data are written, to obtain read data;
respectively comparing the write-in data and the corresponding read-out data of each memory particle of the memory bank to be tested;
taking the memory particles with the written data and the corresponding read data with only one different bit as the fault memory particles with only one error of the minimum storage unit;
and acquiring a fault-free dual rank memory bank, and replacing any fault-free memory granule of the fault-free dual rank memory bank by the fault memory granule to change the fault-free dual rank memory bank into a fault memory bank with only one fault memory granule.
4. The method of claim 3, wherein said obtaining a fault-free dual rank memory bank comprises:
respectively performing data writing operation on a plurality of dual rank memory banks to be tested;
respectively reading data from the multiple dual rank to-be-tested memory banks with written data to obtain read data;
respectively comparing the written data and the corresponding read data of each dual rank memory bank to be tested;
and taking the dual rank memory bank to be tested with the same write-in data and the corresponding read-out data as a fault-free dual rank memory bank.
5. The method of claim 2, wherein the obtaining rank address bits of the rank on the failing memory bank comprises:
taking a rank where the fault memory granule is currently located on the fault memory bank as a first rank, taking another rank on the fault memory bank as a second rank, and taking the position of the fault memory granule on the first rank as a first position;
respectively acquiring error reporting addresses corresponding to positions, corresponding to the first position, of the fault memory granules on the first rank and the second rank of the first rank to obtain a first error reporting address and a second error reporting address;
and obtaining a difference bit of the first error reporting address and the second error reporting address, and using the difference bit as a rank address bit of a rank on the faulty memory bank, where the difference bit is a bit with a changed value corresponding to a same bit in the first error reporting address and the second error reporting address, and the rank address bits are the same when different memory banks are tested on the same motherboard.
6. The method according to claim 5, wherein the obtaining the value corresponding to the rank address bit when the faulty memory granule is located in different ranks of the faulty memory bank, and using the value corresponding to the rank address bit as the rank address corresponding to the rank comprises:
respectively obtaining values corresponding to the rank address bits in the first error reporting address and the second error reporting address obtained when the fault memory granule is located in different ranks of the fault memory bank, and respectively taking the values corresponding to the rank address bits as rank addresses corresponding to ranks on the fault memory bank, wherein the rank addresses corresponding to the same ranks of different memory banks are tested on the same mainboard by different memory banks, and the rank addresses corresponding to the same ranks of different memory banks are the same.
7. The method according to claim 6, wherein the obtaining error reporting addresses corresponding to positions of the failed memory granule on a first rank and a second rank of the first rank and corresponding to the first position respectively to obtain a first error reporting address and a second error reporting address comprises:
respectively acquiring the fault memory granules at the first position of a first rank and the memory granules at the position corresponding to the first position on a second rank to exchange, so that when the fault memory granules are at the corresponding positions of different ranks of the fault memory bank, the fault memory granules respectively detect a first error reporting address and a second error reporting address sent by a CPU (Central processing Unit) when the fault memory bank is detected.
8. The method according to claim 7, wherein the locating the rank where the target failed memory granule is located on the target dual-rank memory strip according to the rank address corresponding to the rank where the target failed memory granule is located and the rank mapping table comprises:
if the rank address corresponding to the rank where the target failure memory granule is located corresponds to the first rank in the rank mapping table, the target failure memory granule on the target dual rank memory bank is located on the first rank;
and if the rank address corresponding to the rank where the target fault memory granule is located corresponds to a second rank in the rank mapping table, the target fault memory granule on the target dual rank memory bank is located on the second rank.
9. An apparatus for locating a failing memory bank rank, the apparatus comprising:
the system comprises a mapping table obtaining unit, a mapping table obtaining unit and a mapping table determining unit, wherein the mapping table obtaining unit is used for obtaining a rank mapping table, and the rank mapping table represents a one-to-one mapping relation of ranks, rank address bits and rank addresses on a dual rank memory bank tested on the same mainboard;
the error reporting address acquisition unit is used for acquiring an error reporting address corresponding to a target fault memory particle on a target dual rank memory bank;
an address bit obtaining unit, configured to obtain a rank address bit in the error reporting address according to the rank mapping table;
an address obtaining unit, configured to obtain a value corresponding to a rank address bit in the error reporting address to obtain a rank address corresponding to a rank where the target faulty memory granule is located;
and the positioning unit is used for positioning the rank of the target fault memory granule on the target dual rank memory strip according to the rank address corresponding to the rank of the target fault memory granule and the rank mapping table.
10. A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, causes the processor to carry out the steps of the method according to any one of claims 1 to 6.
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Denomination of invention: Method, device, and storage medium for locating the rank of faulty memory particles Granted publication date: 20210427 Pledgee: Bank of Communications Limited Shenzhen Branch Pledgor: SHENZHEN TIGO SEMICONDUCTOR Co.,Ltd. Registration number: Y2024980008455 |