CN110707116A

CN110707116A - Image sensor unit

Info

Publication number: CN110707116A
Application number: CN201910986798.4A
Authority: CN
Inventors: 黄晓橹; 张盛鑫; 魏代龙; 金子贵昭
Original assignee: Huaian Imaging Device Manufacturer Corp
Current assignee: Huaian Xide Industrial Design Co ltd
Priority date: 2019-10-17
Filing date: 2019-10-17
Publication date: 2020-01-17
Anticipated expiration: 2039-10-17
Also published as: CN110707116B

Abstract

The invention relates to an image sensor unit, comprising a substrate; a photosensitive element formed in the substrate and generating charges in response to incident light; a floating diffusion region for receiving and storing charge from the photosensitive element; and a transfer transistor configured to be capable of transferring charge remaining in the photosensitive element to the floating diffusion region for later use in forming an image. The transfer transistor comprises a grid electrode dielectric layer formed on a substrate and a grid electrode layer formed on the grid electrode dielectric layer, wherein the grid electrode dielectric layer further comprises a tunnel oxide layer, a charge storage layer formed on the tunnel oxide layer and a blocking oxide layer formed on the charge storage layer.

Description

Image sensor unit

Technical Field

The present invention relates to an image sensor unit, and more particularly, to an image sensor unit capable of reducing image lag.

Background

In recent years, a solid-state image sensor such as a video camera or a digital still camera generally uses a CMOS (complementary metal oxide semiconductor) image sensor.

Conventional CMOS image sensors may suffer from a phenomenon known as image lag (image lag). As is known in the art, incomplete charge transfer from the photodiode PD to the readout node of a given pixel produces image lag. The performance of a CMOS image sensor to completely transfer charge between two regions depends on the strength of the electric field between the regions and the barrier profile between the two regions.

In this regard, because CMOS image sensor devices are designed to operate with lower power supply voltages to meet the need for reduced power consumption, it is desirable to minimize image lag due to incomplete charge transfer.

Disclosure of Invention

In order to solve the above technical problems, the present invention provides an improved image sensor unit so as to minimize image lag. The present invention employs a SONOS structure similar to a memory in a transfer transistor of an image sensor cell, for example, a gate dielectric layer of the transfer transistor is composed of a tunnel oxide layer-a charge storage layer-a blocking oxide layer (e.g., oxide-nitride-oxide (ONO)) to change a threshold voltage of the transfer transistor by applying a tuning voltage to trap charge in the charge storage layer or to drain charge from the charge storage layer, so that the threshold voltage of the transfer transistor can be individually programmed.

In one embodiment of the present invention, an image sensor unit is disclosed, including a substrate; a photosensitive element formed in the substrate and generating charges in response to incident light; a floating diffusion region for receiving and storing charge from the photosensitive element; a transfer transistor configured to be capable of transferring charge remaining in the photosensitive element to the floating diffusion region for subsequent use in forming an image; the transfer transistor comprises a grid dielectric layer formed on a substrate and a grid electrode layer formed on the grid dielectric layer, the grid dielectric layer further comprises a tunnel oxide layer, a charge storage layer formed on the tunnel oxide layer and a blocking oxide layer formed on the charge storage layer, and the charge storage layer adjusts charges in the charge storage layer after the transfer transistor is applied with an adjusting voltage so as to program the threshold voltage of the transfer transistor.

Preferably, when a positive adjustment voltage is applied to the transfer transistor, the charge storage layer traps charge that passes through the tunnel oxide layer and the blocking oxide layer prevents further movement of charge to the gate electrode layer.

Preferably, when a negative adjustment voltage is applied to the transfer transistor, the charges in the charge storage layer are discharged into the substrate through the tunnel oxide layer and the blocking oxide layer prevents the loss of the charges in the gate electrode layer.

Preferably, the transfer transistor is configured to include a SONOS (Silicon-oxide-Nitride-oxide-Silicon) memory structure.

Preferably, the charge storage layer is a SIN layer, a Si3N4 layer, or a HfO2 layer.

Preferably, the tunnel oxide layer and the blocking oxide layer have a thickness of 5 to 10nm, the charge storage layer has a thickness of 5 to 10nm, and the gate electrode layer has a thickness of 30 to 50 nm.

Preferably, in the case where the adjustment voltage is not applied again, the electric charges trapped in the charge storage layer will exist in the charge storage layer for a long period of time to change the threshold voltage of the transfer transistor.

Preferably, without reapplying an adjustment voltage, charge that is removed from the charge storage layer will not return to the charge storage layer for a long period of time to change the threshold voltage of the transfer transistor.

Preferably, in the wafer test stage, an adjustment voltage is applied to the individual image sensor cells so as to increase uniformity of threshold voltages of the image sensor cells on the wafer.

Preferably, the positive adjustment voltage is much higher than the threshold voltage.

Preferably, the magnitude and the sign of the adjustment voltage are changeable for different transfer transistors.

Preferably, the transfer transistor, after being applied with the adjustment voltage to change the threshold voltage: when the transfer transistor is turned on, a barrier height of the transfer transistor is higher than a barrier height of the floating diffusion region and lower than a barrier height of the photosensitive element, so that charges move from the photosensitive element to the floating diffusion region; when the transfer transistor is turned off, the barrier height of the transfer transistor is higher than the barrier height of the floating diffusion region and the photosensitive element, so that the charge stops moving from the photosensitive element to the floating diffusion region and remains in the photosensitive element.

In another embodiment of the present disclosure, there is also disclosed a method of forming an image sensor unit, including forming a substrate; forming a photosensitive element in the substrate, the photosensitive element generating charge in response to incident light; forming a floating diffusion region in the substrate for receiving and storing charge from the photosensitive element; forming a transfer transistor on the substrate and between the photosensitive element and the floating diffusion region, the transfer transistor configured to be capable of transferring charge remaining in the photosensitive element to the floating diffusion region for later use in forming an image; the transfer transistor comprises a grid dielectric layer formed on a substrate and a grid electrode layer formed on the grid dielectric layer, the grid dielectric layer further comprises a tunnel oxide layer, a charge storage layer formed on the tunnel oxide layer and a blocking oxide layer formed on the charge storage layer, and the charge storage layer adjusts charges in the charge storage layer after the transfer transistor is applied with an adjusting voltage so as to program the threshold voltage of the transfer transistor.

Preferably, the transfer transistor is formed with a SONOS (Silicon-oxide-Nitride-oxide-Silicon) memory structure.

Preferably, the method further comprises forming a tunnel oxide layer and the blocking oxide layer having a thickness of 5-10nm, forming the charge storage layer having a thickness of 5-10nm, and forming a gate electrode layer having a thickness of 30-50 nm.

In another embodiment of the invention, a method for testing and adjusting a wafer is also disclosed, which comprises applying a wafer test voltage to the transfer transistors of the image sensor units comprising the image sensor units as described above, and separately applying an adjustment voltage to the transfer transistors of the single image sensor units in which imaging lag occurs.

In another embodiment of the present invention, an electronic device is also disclosed, comprising the image sensor unit as described above.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure. For purposes of simplicity and clarity in representing elements in the figures, the elements in the figures are not drawn to scale.

The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:

fig. 1 is a schematic circuit diagram of a conventional image sensor unit;

fig. 2 is a schematic view illustrating a conventional image sensor unit depicted in fig. 1;

FIG. 3 is a diagram of the expected potential barriers of an image sensor cell during charge accumulation and during charge transfer;

FIG. 4 is an undesirable potential barrier diagram of an image sensor cell during charge accumulation and during charge transfer;

FIG. 5 is a schematic diagram of an image sensor cell according to one embodiment of the invention;

fig. 6 is a flow chart of manufacturing an image sensor according to an embodiment of the present invention.

Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In this specification, like reference numerals and letters are used to designate like items, and therefore, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings.

For convenience of understanding, the positions, sizes, ranges, and the like of the respective structures shown in the drawings and the like do not sometimes indicate actual positions, sizes, ranges, and the like. Therefore, the disclosed invention is not limited to the positions, dimensions, ranges, etc., disclosed in the drawings and the like.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.

Fig. 1 is a circuit schematic diagram of a conventional image sensor cell in which the unit pixel may be constructed with non-planar transistors according to an exemplary embodiment of the present invention. In particular, fig. 1 schematically depicts a unit pixel having a 4-transistor active pixel sensor architecture. In general, an exemplary unit pixel includes a light sensing element PD, a transfer transistor TX, a floating diffusion FD, a reset transistor RX, an amplifier DX (or source follower amplifier), and a selection transistor SX.

The light sensing element PD may be, for example, a photodiode or a PIN photodiode, which is formed in a light receiving area of the unit pixel. The photosensitive element PD is coupled/decoupled to/from the floating diffusion region FD by the operation of the transfer transistor TX. The reset transistor RX has a gate electrode connected to the RS control signal line. The transfer transistor TX has a gate electrode connected to a TG control signal line. The selection transistor SX has a gate electrode connected to the SEL control signal line and a source electrode connected to the output line OUT.

The reset transistor RX, transfer transistor TX, amplifier DX and select transistor SX are operated to perform functions such as resetting the pixel, transferring the accumulated charge from the photosensitive element PD to the floating diffusion region FD, and converting the accumulated charge in the floating diffusion region FD into a measurable voltage that is amplified and transferred to the output line OUT. More specifically, the exemplary unit pixel operates as follows.

Initially, during the integration period (or charge collection period), the unit pixel is illuminated with incident light, and photo-generated charges are accumulated in the potential well (or charge accumulation region) of the photosensitive element PD. After the integration period is completed, the reset transistor RX is activated by a reset control signal applied to the RS control signal line to drain charges from the floating diffusion region FD and set the floating diffusion region FD to a reference potential (e.g., the floating diffusion region FD is charged to about a source voltage VDD, which is less than a threshold voltage of the reset transistor RX). After the reset operation, the transfer transistor TX is activated by a control signal applied to the TG control signal line to transfer the accumulated photo-generated charges from the photosensitive element PD to the floating diffusion FD. The amplification transistor DX amplifies the voltage of the floating diffusion FD, and the amplified voltage is buffered/coupled to the output line OUT via a selection transistor SX activated by a row selection signal applied to a SEL control signal line.

Fig. 2 is a schematic diagram illustrating a unit pixel in the related art described in fig. 1. Which illustrates a PD region (110a) and a partial transistor region (110b), wherein the partial transistor region (110b) includes a transfer transistor TX, a floating diffusion FD, and a reset transistor RX. Other devices, such as amplifier DX and select transistor SX, are not shown for simplicity.

Referring to fig. 2, the PD region (110a) includes a light receiving element (or photodetector element) formed in the semiconductor substrate (100). In one exemplary embodiment, the substrate (100) is a p-doped layer (e.g., a p-well or p-epitaxial layer) formed on a semiconductor substrate in which active pixel elements are formed. In this exemplary embodiment, the light receiving element formed in the PD region (110a) includes a p + layer (111) and a buried n-well layer (112) formed below the p + layer (111). The transfer transistor TX includes a gate electrode (121) having a sidewall spacer (122) and a gate insulating layer (120), wherein the gate insulating layer (120) is formed between the substrate (100) and the gate electrode (121). The floating diffusion region FD (130) is formed between the transfer transistor TX and the reset transistor RX. Isolation regions 101 are formed between the image sensor cells.

Fig. 3 is a diagram of the expected potential barrier of an image sensor cell during charge accumulation and during charge transfer.

During the charge accumulation period, the pixel is illuminated with incident light, and the transfer transistor TX is turned off by a control signal applied to the TG control signal line (i.e., a ground potential or other potential lower than a threshold voltage is applied to the gate of the transfer transistor TX) to cut off the flow of charges from the photosensitive element PD to the floating diffusion region FD, thereby storing charges generated by the photosensitive element PD in response to the incident light in the photosensitive element PD. It follows that, during the charge accumulation period in which the transfer transistor TX is turned off, the potential barrier of the transfer transistor needs to be much higher than the potential barriers of the photosensitive element PD and the floating diffusion FD, thereby shutting off the flow of charges from the photosensitive element PD to the floating diffusion FD.

During charge transfer, the transfer transistor TX is activated (i.e., a threshold voltage is applied to the gate of the transfer transistor TX) by a control signal applied to the TG control signal line to transfer the accumulated photo-generated charge from the photosensitive element PD to the floating diffusion region FD. It can be seen that during the charge transfer in which the transfer transistor TX is turned on, the potential barrier of the transfer transistor is desirably located between the photosensitive element PD and the potential barrier of the floating diffusion region FD, thereby causing a potential difference such that charges smoothly flow from the photosensitive element PD to the floating diffusion region FD.

Fig. 4 is an undesirable barrier diagram of an image sensor cell during charge accumulation and during charge transfer. The illustrated undesired barrier diagrams are just a few of many undesired states.

Due to defects or other abnormal conditions of the transfer transistor TX during manufacturing, the potential barrier of the transfer transistor TX when it is turned on and off may not satisfy the above listed conditions, that is, the potential barrier of the transfer transistor is desirably much higher than the potential barrier of the photosensitive element PD and the floating diffusion FD during the charge transfer when the transfer transistor TX is turned off; and the potential barrier of the transfer transistor is desirably positioned between the photosensitive element PD and the potential barrier of the floating diffusion region FD during the charge transfer in which the transfer transistor TX is turned on.

As shown in fig. 4, in the case where the transfer transistor has a manufacturing defect, during the charge accumulation, the potential barrier of the transfer transistor may be undesirably positioned between the potential barriers of the photosensitive element PD and the floating diffusion FD, so that the charges generated during the charge accumulation continuously flow from the photosensitive element PD to the floating diffusion FD, resulting in an undesirable loss of the charges; alternatively, during the charge transfer, the potential barrier of the transfer transistor may be lower than that of the floating diffusion FD, so that the charge cannot smoothly flow from the photosensitive element PD to the floating diffusion FD during the charge transfer; alternatively, during the charge transfer, the potential barrier of the transfer transistor may be higher than that of the photosensitive element PD, so that the charge is trapped in the PD element and cannot smoothly flow from the PD element to the floating diffusion FD. This undesired flow of charge constitutes an image lag (image lag) of the image sensor cell

It is generally possible to know which particular image sensor unit on the wafer has image lag through wafer testing. However, even if it is tested in the wafer test which image unit has image lag, it is difficult to implement the remedial measure. Image sensor elements that exhibit image lag can only be eliminated, thereby reducing the yield of the sensor device. It is therefore desirable to propose a method that enables, after testing the image lag, also to implement improvements on the image sensor unit so as to avoid being discarded and obsolete.

Fig. 5 is a schematic diagram of an image sensor cell according to an embodiment of the present invention. The image sensor unit includes a substrate 100; a photosensitive element PD112 formed in the substrate 100 and generating charges in response to incident light; a floating diffusion FD 130 formed in the substrate 100 for receiving and storing charges from the photosensitive element PD 112; a transfer transistor TX configured to transfer charges remaining in the photosensitive element PD112 to the floating diffusion FD 130 for forming an image later, the transfer transistor TX including a gate dielectric layer 120 formed on a substrate and a gate electrode layer 121 formed on the gate dielectric layer, the gate dielectric layer 120 further including a tunnel oxide layer 120-1, a charge storage layer 120-2 formed on the tunnel oxide layer, and a blocking oxide layer 120-3 formed on the charge storage layer.

Preferably, the tunnel oxide layer and the blocking oxide layer have a thickness of 5 to 10nm, and the charge storage layer has a thickness of 5 to 10The thickness of the nm and gate electrode layers is 30-50 nm. Preferably, the charge storage layer is an SIN layer, Si₃N₄Layer or HfO₂And (3) a layer. Preferably, the charge storage layer has a predetermined density of trap sites therein at which charge can be trapped in the charge storage layer. Preferably, the blocking oxide layer is an insulating layer having a high dielectric constant, such as Al₂O₃Or SiO₂And (3) a layer.

The substrate 100, the tunnel oxide layer 120-1, the charge storage layer 120-2, the blocking oxide layer 120-3, and the gate electrode layer 121 in fig. 5 constitute a SONOS (Silicon-oxide-Nitride-oxide-Silicon) memory structure. After wafer testing, the transfer transistor TX that fails to meet the threshold voltage can be dynamically programmed with the SONOS memory structure.

Specifically, the charge storage layer 120-2 adjusts the charge in the charge storage layer after the transfer transistor TX is applied with a sufficient voltage (i.e., an adjustment voltage) to program the threshold voltage of the transfer transistor TX.

In particular, when the transfer transistor TX is applied with a sufficiently positive voltage, the charge storage layer traps the charge e-passing through the tunnel oxide layer 120-1 and the blocking oxide layer 120-3 prevents the charge e-from moving further to the gate electrode layer 121, and the threshold voltage of the transfer transistor TX can thus be raised since the tunnel oxide layer 120-1 now stores the additional charge e-.

Conversely, when the transfer transistor TX is applied with a sufficient negative voltage, if there happens to be an excess of charges e "in the charge storage layer, these charges e" are discharged through the tunnel oxide layer 120-1 into the substrate 100; if there is no excess charge e-in the charge storage layer, electrons of the charge storage layer itself are discharged out of the charge storage layer through the tunnel oxide layer 120-1 into the substrate 100 to cause additional holes; in either case (reduction of the charge e-or increase of the holes), the threshold voltage of the transfer transistor TX can thus be lowered.

The electric charge e-trapped in the charge storage layer will exist in the charge storage layer for a long period of time without applying the adjustment voltage again; the charge e-leaving the charge storage layer will also not return back into the charge storage layer for a long period of time, permanently changing the threshold voltage of the transfer transistor.

Since the positive adjustment voltage capable of drawing charge from the substrate and trapping in the charge storage layer is much higher than the threshold voltage, applying the threshold voltage to the gate does not affect the charge e-trapped in the charge storage layer. In addition, adjustment voltages with different polarities and different sizes can be applied to different transfer transistors according to the degree of deviation of the different transfer transistors on the wafer from the expected threshold voltage.

Finally, the transfer transistor, after being applied with the adjustment voltage to change the threshold voltage: when the transfer transistor is turned on (i.e., during charge transfer), the barrier height of the transfer transistor will be adjusted to be higher than the barrier height of the floating diffusion region and lower than the barrier height of the photosensitive element PD, so that charges move from the photosensitive element PD to the floating diffusion region; when the transfer transistor is turned off (i.e., during charge accumulation), the barrier height of the transfer transistor will be adjusted to be higher than the barrier height of the floating diffusion region and the photosensitive element PD, so that the charges stop moving from the photosensitive element PD to the floating diffusion region and remain in the photosensitive element PD.

Therefore, in the wafer test stage, different adjusting voltages can be respectively applied to the individual image sensor units, so that the threshold voltage of the individual image sensor units is basically the same as that of other image sensor units on the wafer, and the uniformity of the threshold voltage of the image sensor units on the wafer is improved. It is to be noted that the dynamic adjustment of the threshold voltage of the transfer transistor TX is also applicable to the dynamic adjustment of the threshold voltage of the reset transistor RX.

In step 601, a substrate is formed;

in step 602, forming a photosensitive element PD in the substrate, the photosensitive element PD generating charges in response to incident light;

in step 603, forming a floating diffusion region in the substrate, the floating diffusion region for receiving and storing charges from the photosensitive element PD;

in step 604, a transfer transistor is formed on the substrate and between the photosensitive element PD and the floating diffusion region, the transfer transistor being configured to transfer charges remaining in the photosensitive element PD to the floating diffusion region for later use in forming an image, the transfer transistor including a gate dielectric layer formed on the substrate and a gate electrode layer formed on the gate dielectric layer, the gate dielectric layer further including a tunnel oxide layer, a charge storage layer formed on the tunnel oxide layer, a blocking oxide layer formed on the charge storage layer, the charge storage layer adjusting charges in the charge storage layer after an adjustment voltage is applied to the transfer transistor to program a threshold voltage of the transfer transistor.

In another embodiment of the invention, an electronic device is also disclosed, comprising an image sensor unit as claimed in claim 1.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

Unless the context clearly dictates otherwise, the following terms take the meanings explicitly associated herein throughout the specification and claims. The meaning of "a" and "the" includes plural references, and the meaning of "in …" includes "in …" and "on …". The term "couple" refers to a direct electrical connection between the items coupled, or an indirect connection via one or more passive or active intermediary devices. The term "circuit" refers to a single component, or a plurality of components (active or passive) connected together to provide a desired function. The term "signal" refers to at least one current, voltage, or data signal.

In addition, directional terminology, such as "on …," "over …," "top," "bottom," etc., is used with reference to the orientation of the figure(s) being described. Because components of exemplary embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration only and is in no way limiting. The directional terms, when used in connection with an image sensor wafer or layers of a corresponding image sensor, are intended to be broadly interpreted, and thus should not be interpreted to preclude the presence of one or more intervening layers or other intervening image sensor features or elements. Thus, a given layer described herein as being formed on or over another layer may be separated from the other layer by one or more additional layers.

The terms "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the exemplary embodiments of the disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

As used herein, the word "exemplary" means "serving as an example, instance, or illustration," and not as a "model" that is to be replicated accurately. Any implementation exemplarily described herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the disclosure is not limited by any expressed or implied theory presented in the preceding technical field, background, brief summary or the detailed description.

As used herein, the term "substantially" is intended to encompass any minor variation resulting from design or manufacturing imperfections, device or component tolerances, environmental influences, and/or other factors. The word "substantially" also allows for differences from a perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in a practical implementation.

The above description may indicate elements or nodes or features being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/node/feature is directly connected to (or directly communicates with) another element/node/feature, either electrically, mechanically, logically, or otherwise. Similarly, unless expressly stated otherwise, "coupled" means that one element/node/feature may be mechanically, electrically, logically, or otherwise joined to another element/node/feature in a direct or indirect manner to allow for interaction, even though the two features may not be directly connected. That is, coupled is intended to include both direct and indirect joining of elements or other features, including connection with one or more intermediate elements.

In addition, certain terminology may also be used in the following description for the purpose of reference only, and thus is not intended to be limiting. For example, the terms "first," "second," and other such numerical terms referring to structures or elements do not imply a sequence or order unless clearly indicated by the context.

It will be further understood that the terms "comprises/comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

In the present disclosure, the term "providing" is used broadly to encompass all ways of obtaining an object, and thus "providing an object" includes, but is not limited to, "purchasing," "preparing/manufacturing," "arranging/setting," "installing/assembling," and/or "ordering" the object, and the like.

Those skilled in the art will appreciate that the boundaries between the above described operations merely illustrative. Multiple operations may be combined into a single operation, single operations may be distributed in additional operations, and operations may be performed at least partially overlapping in time. Moreover, alternative exemplary embodiments may include multiple instances of a particular operation, and the order of operations may be altered in other various exemplary embodiments. However, other modifications, variations, and alternatives are also possible. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Although some specific exemplary embodiments of the present disclosure have been described in detail by way of illustration, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. The various exemplary embodiments disclosed herein may be combined in any combination without departing from the spirit and scope of the present disclosure. Those skilled in the art will also appreciate that various modifications may be made to the exemplary embodiments without departing from the scope and spirit of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. An image sensor unit comprising:

a substrate;

a photosensitive element formed in the substrate and generating charges in response to incident light;

a floating diffusion region for receiving and storing charge from the photosensitive element;

a transfer transistor configured to be capable of transferring charge remaining in the photosensitive element to the floating diffusion region for subsequent use in forming an image;

the transfer transistor comprises a grid dielectric layer formed on a substrate and a grid electrode layer formed on the grid dielectric layer, the grid dielectric layer further comprises a tunnel oxide layer, a charge storage layer formed on the tunnel oxide layer and a blocking oxide layer formed on the charge storage layer, and the charge storage layer adjusts charges in the charge storage layer after the transfer transistor is applied with an adjusting voltage so as to program the threshold voltage of the transfer transistor.

2. The image sensor cell of claim 1, wherein when a positive adjustment voltage is applied to the transfer transistor, a charge storage layer traps charge that passes through the tunnel oxide layer and the blocking oxide layer prevents further charge movement to a gate electrode layer.

3. The image sensor cell of claim 1, wherein when a negative trim voltage is applied to the transfer transistor, charge in a charge storage layer is drained through the tunnel oxide layer into the substrate and the blocking oxide layer prevents loss of charge in a gate electrode layer.

4. The image sensor cell of claim 1, wherein the transfer transistor is configured to include a SONOS (Silicon-oxide-Nitride-oxide-Silicon) memory structure.

5. The image sensor cell of claim 1, wherein the charge storage layer is a SIN layer, Si₃N₄Layer or HfO₂And (3) a layer.

6. The image sensor cell of claim 1, wherein the tunnel oxide layer and the blocking oxide layer are 5-10nm thick, the charge storage layer is 5-10nm thick, and the gate electrode layer is 30-50nm thick.

7. The image sensor cell of claim 2, wherein charge trapped in the charge storage layer will be present in the charge storage layer for a long period of time without applying the adjustment voltage again to change the threshold voltage of the transfer transistor.

8. The image sensor cell of claim 3, wherein without reapplying an adjustment voltage, charge that escapes from the charge storage layer will not return to the charge storage layer for long periods of time thereby changing the threshold voltage of the transfer transistor.

9. The image sensor unit of claim 1, wherein during a wafer test phase, an adjustment voltage is applied to individual image sensor units to increase uniformity of threshold voltages of the image sensor units on the wafer.

10. The image sensor cell of claim 2, wherein the positive adjustment voltage is much higher than the threshold voltage.