CN110706726A - Power-on reset circuit with stable power-on reset voltage - Google Patents
Power-on reset circuit with stable power-on reset voltage Download PDFInfo
- Publication number
- CN110706726A CN110706726A CN201910062248.3A CN201910062248A CN110706726A CN 110706726 A CN110706726 A CN 110706726A CN 201910062248 A CN201910062248 A CN 201910062248A CN 110706726 A CN110706726 A CN 110706726A
- Authority
- CN
- China
- Prior art keywords
- power
- reset
- pmos tube
- tube
- pmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
Landscapes
- Electronic Switches (AREA)
Abstract
The invention discloses a power-on reset circuit with stable power-on reset voltage, which comprises: the power-on reset module is used for providing power-on reset voltage required by power-on reset for the nonvolatile memory chip; and the negative feedback module is connected with the power-on reset module and used for sending a negative feedback signal to the power-on reset module according to the temperature and the process angle, and the negative feedback signal is used for controlling the power-on reset voltage output by the power-on reset module to be within a preset range. According to the invention, the negative feedback module is added in the power-on reset circuit, and sends a negative feedback signal to the power-on reset circuit according to the temperature and the process angle, and the negative feedback signal is used for controlling the power-on reset voltage output by the power-on reset circuit to be within a preset range, so that the influence of the temperature and the process angle on the power-on reset voltage can be effectively reduced, the accurate detection of the power-on reset voltage is realized, the stable power-on reset signal is generated, the accurate power-on reset function is realized, and the stable and normal work of a chip is ensured.
Description
Technical Field
The invention relates to the technical field of circuit resetting, in particular to a power-on reset circuit with stable power-on reset voltage.
Background
Non-volatile memory chips, which do not lose data after power is lost, are commonly Read Only Memory (ROM), electrically erasable programmable memory (EEPROM), NOR FLASH memory (NOR FLASH), and NAND FLASH memory (NAND FLASH).
In order to ensure the correct operation and stability of a chip, each circuit module in the chip needs to be powered on and reset before the chip starts to operate. The reset voltage detection of the conventional power-on reset circuit is greatly influenced by temperature and process angle, and the normal power-on reset function may not be achieved under certain conditions.
Disclosure of Invention
In order to solve the problems in the prior art, embodiments of the present invention provide a power-on reset circuit with stable power-on reset voltage. The technical scheme is as follows:
in one aspect, an embodiment of the present invention provides a power-on reset circuit with stable power-on reset voltage, including:
the power-on reset module is used for providing power-on reset voltage required by power-on reset for the nonvolatile memory chip;
and the negative feedback module is connected with the power-on reset module and used for sending a negative feedback signal to the power-on reset module according to the temperature and the process angle, and the negative feedback signal is used for controlling the power-on reset voltage output by the power-on reset module to be within a preset range.
In the above power-on reset circuit according to the embodiment of the present invention, the power-on reset module includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS tube, a second NMOS tube, a first capacitor, a second capacitor, a first phase inverter, a second phase inverter, a first resistor,
the grid electrode of the first PMOS tube is grounded, the source electrode of the first PMOS tube is connected with a power supply, the drain electrode of the first PMOS tube is respectively connected with the grid electrode of the second PMOS tube and the drain electrode and the grid electrode of the first NMOS tube, and the source electrode of the first NMOS tube is grounded; the source electrode of the second PMOS tube is connected with a power supply, the drain electrode of the second PMOS tube is respectively connected with the upper polar plate of the first capacitor and the input end of the first phase inverter, the lower polar plate of the first capacitor is grounded, and the output end of the first phase inverter is respectively connected with the grid electrode of the third PMOS tube, the grid electrode of the second NMOS tube and the negative feedback module; the source electrode of the second NMOS tube is connected with one end of the first resistor, the other end of the first resistor is grounded, and the drain electrode of the second NMOS tube is respectively connected with the drain electrode of the third PMOS tube, the drain electrode of the fourth PMOS tube, the drain electrode of the fifth PMOS tube, the upper polar plate of the second capacitor and the input end of the second phase inverter; the grid electrode of the fourth PMOS tube is grounded, and the source electrode of the fourth PMOS tube is connected with a power supply; the source electrode of the fifth PMOS tube is connected with the power supply, and the grid electrode of the fifth PMOS tube is connected with the negative feedback module; the lower pole plate of the second capacitor is grounded; the output end of the second phase inverter is shaped by a plurality of phase inverters and then is connected with the nonvolatile memory chip to be used as the output end of the power-on reset module.
In the above power-on reset circuit according to the embodiment of the present invention, the negative feedback module includes: a sixth PMOS tube, a second resistor, a third NMOS tube,
the source electrode of the sixth PMOS tube is connected with the power supply, the grid electrode of the sixth PMOS tube is grounded, and the drain electrode of the sixth PMOS tube is respectively connected with the grid electrode of the fifth PMOS tube and one end of the second resistor; the other end of the second resistor is connected with the drain electrode of the third NMOS tube, the source electrode of the third NMOS tube is grounded, and the grid electrode of the third NMOS tube is connected with the output end of the first phase inverter.
In the power-on reset circuit according to the embodiment of the present invention, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are all PMOS transistors of the same type.
In the power-on reset circuit according to the embodiment of the present invention, the first resistor and the second resistor are both resistors of the same type and having the same temperature coefficient.
In the power-on reset circuit in the embodiment of the present invention, the power-on reset voltage of the power-on reset circuit is between 1.3V and 1.6V at a temperature of-40 ℃ to +85 ℃ under the condition of a full process corner.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
the negative feedback module is added in the power-on reset circuit and sends a negative feedback signal to the power-on reset circuit according to the temperature and the process angle, and the negative feedback signal is used for controlling the power-on reset voltage output by the power-on reset circuit to be within a preset range, so that the influence of the temperature and the process angle on the power-on reset voltage can be effectively reduced, accurate power-on reset voltage detection is realized, a stable power-on reset signal is generated, an accurate power-on reset function is realized, and the stable and normal work of a chip is ensured.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a circuit diagram of a power-on reset circuit with stable power-on reset voltage according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a power-on reset circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Example one
An embodiment of the present invention provides a power-on reset circuit with stable power-on reset voltage, which is suitable for providing stable and reliable power-on reset voltage for a nonvolatile memory chip to ensure stable and normal operation of the chip, and referring to fig. 2, the power-on reset circuit may include:
and a power-on reset module 100, configured to provide a power-on reset voltage required for power-on reset to the nonvolatile memory chip.
And the negative feedback module 200 is connected to the power-on reset module 100, and is configured to send a negative feedback signal to the power-on reset module according to the temperature and the process angle, where the negative feedback signal is used to control the power-on reset voltage output by the power-on reset module to be within a preset range.
It should be noted that, the conventional power-on reset circuit has no negative feedback module, and the power-on reset voltage provided by the conventional power-on reset circuit is easily affected by temperature and process angle, so that the power-on reset voltage may deviate from a normal use range, and a situation that a power-on reset signal cannot realize a correct power-on reset function occurs, thereby seriously affecting the normal operation of the nonvolatile memory chip. The power-on reset circuit provided by the embodiment is additionally provided with the negative feedback module 200, which sends a negative feedback signal to the power-on reset module according to the temperature and the process angle, wherein the negative feedback signal is used for controlling the power-on reset voltage output by the power-on reset module to be within a preset range, so that the influence of the temperature and the process angle on the power-on reset voltage can be effectively reduced, and the stable and normal operation of a chip is further ensured.
Specifically, referring to fig. 2, the power-on reset module includes: the circuit comprises a first PMOS tube P0, a second PMOS tube P1, a third PMOS tube P2, a fourth PMOS tube P3, a fifth PMOS tube P4, a first NMOS tube N1, a second NMOS tube N2, a first capacitor C1, a second capacitor C2, a first inverter D1, a second inverter D2 and a first resistor RS 1.
The grid electrode of the first PMOS tube P0 is grounded, the source electrode thereof is connected with a power supply VDD, the drain electrode thereof is respectively connected with the grid electrode of the second PMOS tube P1 and the drain electrode and the grid electrode of the first NMOS tube N1, and the source electrode of the first NMOS tube N1 is grounded; the source electrode of the second PMOS tube P1 is connected with a power supply VDD, the drain electrode of the second PMOS tube P1 is respectively connected with the upper polar plate of the first capacitor C1 and the input end of the first inverter D1, the lower polar plate of the first capacitor C1 is grounded, and the output end of the first inverter D1 is respectively connected with the grid electrode of the third PMOS tube P2, the grid electrode of the second NMOS tube N2 and the grid electrode of the third NMOS tube N3 in the negative feedback module; (ii) a The source electrode of the second NMOS tube N2 is connected with one end of a first resistor RS1, the other end of the first resistor RS1 is grounded, the drain electrode of the second NMOS tube N2 is respectively connected with the drain electrode of a third PMOS tube P2, the drain electrode of a fourth PMOS tube P3, the drain electrode of a fifth PMOS tube P4, the upper polar plate of a second capacitor C2 and the input end of a second inverter D2; the grid electrode of the fourth PMOS pipe P3 is grounded, and the source electrode thereof is connected with a power supply VDD; the source electrode of the fifth PMOS tube P4 is connected with a power supply VDD, and the grid electrode of the fifth PMOS tube P4 is connected with the drain electrode of a sixth PMOS tube P5 in the negative feedback module; the lower plate of the second capacitor C2 is grounded; the output end of the second inverter D2 is shaped by a plurality of inverters and then is connected with the nonvolatile memory chip to be used as the output end of the power-on reset module. It should be noted that the inverter may invert the phase of the input signal by 180 degrees, and one second inverter D2 may be installed at the second inverter D2, or three second inverters D2 connected in series (as shown in fig. 1) may be installed, which is not limited herein.
Further, referring to fig. 1, the negative feedback module may include: a sixth PMOS transistor P5, a second resistor RS2, and a third NMOS transistor N3.
The source electrode of the sixth PMOS transistor P5 is connected to the power supply VDD, the gate electrode thereof is grounded, and the drain electrode thereof is respectively connected to the gate electrode of the fifth PMOS transistor P4 and one end of the second resistor RS 2; the other end of the second resistor RS2 is connected to the drain of the third NMOS transistor N3, the source of the third NMOS transistor N3 is grounded, and the gate of the third NMOS transistor N3 is connected to the output of the first inverter D1.
Optionally, referring to fig. 1, the fourth PMOS transistor P3, the fifth PMOS transistor P4, and the sixth PMOS transistor P5 are all PMOS transistors of the same type.
Optionally, referring to fig. 1, the first resistor RS1 and the second resistor RS2 are both the same type of resistor with the same temperature coefficient.
In the present embodiment, the power-on reset voltage outputted by the power-on reset circuit is mainly determined by P3, P4, and RS 1. The gate of the P4 is connected to a signal with negative feedback information of temperature and process angle (i.e. controlled by the negative feedback signal of the negative feedback module), the P3 can be regarded as a resistor, the P4 can be regarded as a resistor negatively fed back by temperature and process angle, the RS2 is a resistor of the same type as the RS1, and the temperature coefficient of the resistor is the same. That is, the resistance of P3, the resistance of P4, and the resistance of RS1 are used to detect the power supply voltage, and the ratio of the resistances of P3 and P4 connected in parallel to the resistance of RS1 determines the power-on reset voltage.
In the present embodiment, referring to fig. 1, at room temperature, it is assumed that the node NOD4 needs to be 0.7V to flip the level of the INV0 to generate the power-on reset signal, and the power voltage (i.e. the voltage provided by the power VDD) is about 1.5V.
Under the condition of certain temperature (high temperature or low temperature) or process angle, the resistance ratio of the P3 to the RS1 is smaller than that of the room temperature, if the change of the resistance value of the P4 along with the temperature and the process angle is not considered, the NOD4 can reach 0.7V by the power supply voltage lower than 1.5V, the inversion of the INV0 is realized, a power-on reset signal is generated, namely the power-on reset voltage is lower than 1.5V, but the RS _ CON voltage generated by a negative feedback circuit overcoming the temperature and the process angle is higher than the room temperature (because the P5, the P3 and the P4 are the same in type, the RS2 and the RS1 are the same in type and have the same temperature coefficient, and the ratio of the P5 to the RS2 is also smaller than that of the room temperature), so that the resistance value of the P4 is increased, the resistance ratio of the P3 to the P4 is increased after the P4 is connected in parallel, the resistance ratio of the RS1 in the temperature condition is reduced, and the resistance, thereby achieving the effect of reducing the power-on reset voltage caused by temperature and process corner.
Under the condition of certain temperature (high temperature or low temperature) or process angle, the resistance ratio of the P3 to the RS1 is larger than that of the room temperature, if the change of the resistance value of the P4 along with the temperature and the process angle is not considered, the NOD4 can reach 0.7V by the power supply voltage higher than 1.5V, the inversion of the INV0 is realized, the power-on reset signal is generated, namely the power-on reset voltage is higher than 1.5V, but the RS _ CON voltage generated by a negative feedback circuit for overcoming the temperature and the process angle is lower than the room temperature (because the resistance values of the P5, the P3, the P4 are the same, the RS2 and the RS1 are the same in type and temperature coefficient, and the resistance ratios of the P5 resistance and the RS2 resistance are also higher than the room temperature), so that the resistance value of the P4 is reduced, the resistance value of the P3 resistance and the P4 resistance after the parallel connection is reduced, the resistance ratio of the RS1 resistance after the parallel connection is reduced under the temperature condition, and the deviation of the room, thereby achieving the effect of reducing the power-on reset voltage caused by temperature and process corner.
Optionally, the power-on reset voltage of the power-on reset circuit is between 1.3V and 1.6V under the conditions of-40 ℃ to +85 ℃ and the full process angle.
In this embodiment, the power-on reset circuit has a power-on reset voltage between 1.3V and 1.6V under the conditions of-40 ℃ to +85 ℃ and a full process angle, which is much narrower than the range (0.9V to 1.8V) of the power-on reset voltage of the power-on reset circuit without negative feedback with temperature and process angle, so that accurate power-on reset voltage detection can be realized, a stable power-on reset signal can be generated, an accurate power-on reset function can be realized, and stable and normal operation of a chip can be ensured.
According to the embodiment of the invention, the negative feedback module is added in the power-on reset circuit, and sends the negative feedback signal to the power-on reset circuit according to the temperature and the process angle, and the negative feedback signal is used for controlling the power-on reset voltage output by the power-on reset circuit to be within the preset range, so that the influence of the temperature and the process angle on the power-on reset voltage can be effectively reduced, the accurate detection of the power-on reset voltage is realized, the stable power-on reset signal is generated, the accurate power-on reset function is realized, and the stable and normal work of a chip is ensured.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (6)
1. A power-on-reset circuit with stable power-on-reset voltage, comprising:
the power-on reset module is used for providing power-on reset voltage required by power-on reset for the nonvolatile memory chip;
and the negative feedback module is connected with the power-on reset module and used for sending a negative feedback signal to the power-on reset module according to the temperature and the process angle, and the negative feedback signal is used for controlling the power-on reset voltage output by the power-on reset module to be within a preset range.
2. The power-on-reset circuit of claim 1, wherein the power-on-reset module comprises: a first PMOS tube (P0), a second PMOS tube (P1), a third PMOS tube (P2), a fourth PMOS tube (P3), a fifth PMOS tube (P4), a first NMOS tube (N1), a second NMOS tube (N2), a first capacitor (C1), a second capacitor (C2), a first inverter (D1), a second inverter (D2) and a first resistor (RS1),
the grid electrode of the first PMOS tube (P0) is grounded, the source electrode of the first PMOS tube is connected with a power supply (VDD), the drain electrode of the first PMOS tube is respectively connected with the grid electrode of the second PMOS tube (P1) and the drain electrode and the grid electrode of the first NMOS tube (N1), and the source electrode of the first NMOS tube (N1) is grounded; the source electrode of the second PMOS tube (P1) is connected with a power supply (VDD), the drain electrode of the second PMOS tube is respectively connected with the upper polar plate of the first capacitor (C1) and the input end of the first inverter (D1), the lower polar plate of the first capacitor (C1) is grounded, and the output end of the first inverter (D1) is respectively connected with the grid electrode of the third PMOS tube (P2), the grid electrode of the second NMOS tube (N2) and the negative feedback module; the source electrode of the second NMOS tube (N2) is connected with one end of the first resistor (RS1), the other end of the first resistor (RS1) is grounded, and the drain electrode of the second NMOS tube (N2) is respectively connected with the drain electrode of the third PMOS tube (P2), the drain electrode of the fourth PMOS tube (P3), the drain electrode of the fifth PMOS tube (P4), the upper polar plate of the second capacitor (C2) and the input end of the second inverter (D2); the source end of the third PMOS pipe (P2) is connected with a power supply (VDD); the grid electrode of the fourth PMOS tube (P3) is grounded, and the source electrode of the fourth PMOS tube is connected with the power supply (VDD); the source electrode of the fifth PMOS tube (P4) is connected with a power supply (VDD), and the grid electrode of the fifth PMOS tube is connected with the negative feedback module; the lower plate of the second capacitor (C2) is grounded; the output end of the second inverter (D2) is shaped by a plurality of inverters and then is connected with the nonvolatile memory chip to be used as the output end of the power-on reset module.
3. The power-on-reset circuit of claim 2, wherein the negative feedback module comprises: a sixth PMOS tube (P5), a second resistor (RS2), a third NMOS tube (N3),
the source electrode of the sixth PMOS tube (P5) is connected with a power supply (VDD), the grid electrode of the sixth PMOS tube is grounded, and the drain electrode of the sixth PMOS tube is respectively connected with the grid electrode of the fifth PMOS tube (P4) and one end of a second resistor (RS 2); the other end of the second resistor (RS2) is connected with the drain electrode of the third NMOS tube (N3), the source electrode of the third NMOS tube (N3) is grounded, and the grid electrode of the third NMOS tube (N3) is connected with the output end of the first phase inverter (D1).
4. The power-on reset circuit according to claim 3, wherein the fourth PMOS transistor (P3), the fifth PMOS transistor (P4) and the sixth PMOS transistor (P5) are all the same type of PMOS transistors.
5. The power-on reset circuit according to claim 3, wherein the first resistor (RS1) and the second resistor (RS2) are both the same type of resistor with the same temperature coefficient.
6. A power-on reset circuit according to any one of claims 1 to 5, wherein the power-on reset voltage is between 1.3V and 1.6V at-40 ℃ to +85 ℃ under the full process corner condition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910062248.3A CN110706726B (en) | 2019-01-23 | 2019-01-23 | Power-on reset circuit with stable power-on reset voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910062248.3A CN110706726B (en) | 2019-01-23 | 2019-01-23 | Power-on reset circuit with stable power-on reset voltage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110706726A true CN110706726A (en) | 2020-01-17 |
| CN110706726B CN110706726B (en) | 2020-07-28 |
Family
ID=69193076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910062248.3A Active CN110706726B (en) | 2019-01-23 | 2019-01-23 | Power-on reset circuit with stable power-on reset voltage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110706726B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113364441A (en) * | 2021-06-30 | 2021-09-07 | 芯天下技术股份有限公司 | POR circuit of high power down POR voltage |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020005740A1 (en) * | 1998-02-27 | 2002-01-17 | Hong Seok Kim | Power-up/power-down detection circuit |
| US20040041601A1 (en) * | 2002-08-30 | 2004-03-04 | Payne James E. | Power-on reset circuit |
| US20040263222A1 (en) * | 2003-06-27 | 2004-12-30 | Chien-Chung Tseng | Power-on reset circuit with supply voltage and temperature immunity, ultra-low DC leakage current, and fast power crash reaction |
| CN102291110A (en) * | 2011-06-21 | 2011-12-21 | 东南大学 | Power-on-reset circuit with zero steady state current consumption and stable pull-up voltage |
| CN103427812A (en) * | 2012-05-25 | 2013-12-04 | 国家电网公司 | Power-on reset circuit and method thereof |
| US20150236689A1 (en) * | 2012-10-24 | 2015-08-20 | Stmicroelectronics International N.V. | Power-on-Reset and Supply Brown Out Detection Circuit with Programmability |
| CN106200846A (en) * | 2016-06-28 | 2016-12-07 | 珠海市杰理科技有限公司 | Power on and off reset circuit and chip |
| CN107066018A (en) * | 2017-06-29 | 2017-08-18 | 英麦科（厦门）微电子科技有限公司 | A kind of accurate por circuit |
| US9899065B1 (en) * | 2016-11-24 | 2018-02-20 | SK Hynix Inc. | Power-on reset circuit and semiconductor memory device having the same |
-
2019
- 2019-01-23 CN CN201910062248.3A patent/CN110706726B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020005740A1 (en) * | 1998-02-27 | 2002-01-17 | Hong Seok Kim | Power-up/power-down detection circuit |
| US20040041601A1 (en) * | 2002-08-30 | 2004-03-04 | Payne James E. | Power-on reset circuit |
| US20040263222A1 (en) * | 2003-06-27 | 2004-12-30 | Chien-Chung Tseng | Power-on reset circuit with supply voltage and temperature immunity, ultra-low DC leakage current, and fast power crash reaction |
| CN102291110A (en) * | 2011-06-21 | 2011-12-21 | 东南大学 | Power-on-reset circuit with zero steady state current consumption and stable pull-up voltage |
| CN103427812A (en) * | 2012-05-25 | 2013-12-04 | 国家电网公司 | Power-on reset circuit and method thereof |
| US20150236689A1 (en) * | 2012-10-24 | 2015-08-20 | Stmicroelectronics International N.V. | Power-on-Reset and Supply Brown Out Detection Circuit with Programmability |
| CN106200846A (en) * | 2016-06-28 | 2016-12-07 | 珠海市杰理科技有限公司 | Power on and off reset circuit and chip |
| US9899065B1 (en) * | 2016-11-24 | 2018-02-20 | SK Hynix Inc. | Power-on reset circuit and semiconductor memory device having the same |
| CN108109653A (en) * | 2016-11-24 | 2018-06-01 | 爱思开海力士有限公司 | Electrification reset circuit and the semiconductor memory system with the electrification reset circuit |
| CN107066018A (en) * | 2017-06-29 | 2017-08-18 | 英麦科（厦门）微电子科技有限公司 | A kind of accurate por circuit |
Non-Patent Citations (2)
| Title |
|---|
| JIN ZHANG等: "Design of a Novel Power-on-Reset Circuit Based on Power Supply Detector", 《2009 INTERNATIONAL CONFERENCE ON SCALABLE COMPUTING AND COMMUNICATIONS》 * |
| TORU TANZAWA: "A process- and temperature-tolerant power-on reset circuit with a flexible detection level higher than the bandgap voltage", 《 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113364441A (en) * | 2021-06-30 | 2021-09-07 | 芯天下技术股份有限公司 | POR circuit of high power down POR voltage |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110706726B (en) | 2020-07-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0584597B2 (en) | ||
| US7750703B2 (en) | Duty cycle correcting circuit | |
| CN111030647B (en) | Double-sided delay circuit | |
| ITMI20002529A1 (en) | CONTROL CIRCUIT OF AN EXIT PILOTING STAGE OF AN INTEGRATED CIRCUIT | |
| US9360877B2 (en) | Negative voltage regulation circuit and voltage generation circuit including the same | |
| US6344766B1 (en) | Voltage level converter circuit improved in operation reliability | |
| CN110706726B (en) | Power-on reset circuit with stable power-on reset voltage | |
| US10482966B2 (en) | Block decoder of nonvolatile memory and level shifter | |
| US7126434B2 (en) | Oscillator circuit for semiconductor device | |
| US8767485B1 (en) | Operation method of a supply voltage generation circuit used for a memory array | |
| US10651732B2 (en) | Charge pumps and methods of operating charge pumps | |
| US8405428B2 (en) | Semiconductor integrated circuit | |
| CN105405466B (en) | Data reading circuit | |
| US11249118B2 (en) | Current sensing circuit | |
| US9571101B2 (en) | Semiconductor device | |
| CN110943610B (en) | Charge pump system and nonvolatile memory | |
| US7652524B2 (en) | Voltage source for gate oxide protection | |
| US6781891B2 (en) | Half power supply voltage generator and semiconductor memory device using the same | |
| CN111091853B (en) | Timing generation circuit for sense amplifier in EEPROM | |
| KR100459946B1 (en) | Stabilization output apparatus of flag cell data, especially outputting stable data of flag cell and fuse cell | |
| US20110090000A1 (en) | Signal transmission circuit | |
| KR20010041910A (en) | Circuit for powering down unused configuration bits to minimize power consumption | |
| JPH0222477B2 (en) | ||
| US20150069519A1 (en) | Semiconductor device | |
| KR20000042865A (en) | Output buffer circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 518000 Room 101, building 10, Dayun software Town, 8288 Longgang Avenue, he'ao community, Yuanshan street, Longgang District, Shenzhen City, Guangdong Province Patentee after: XTX Technology Inc. Address before: 518000 1st floor, building 10, Dayun software Town, 8288 Longgang Avenue, Henggang street, Longgang District, Shenzhen City, Guangdong Province Patentee before: Paragon Technology (Shenzhen) Ltd. |
|
| CP03 | Change of name, title or address |