CN110703999A - Scheduling method for read operation of memory and memory - Google Patents
Scheduling method for read operation of memory and memory Download PDFInfo
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- CN110703999A CN110703999A CN201910941972.3A CN201910941972A CN110703999A CN 110703999 A CN110703999 A CN 110703999A CN 201910941972 A CN201910941972 A CN 201910941972A CN 110703999 A CN110703999 A CN 110703999A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Abstract
The invention discloses a scheduling method of read operation of a memory and the memory, wherein the memory comprises two read ports, the memory consists of two 1RW memories, and the method comprises the following steps: in the same time period, two read operation requests of a read operation 0 and a read operation 1 exist in two read ports of the memory respectively; if the two read requests need to access different 1RW memories respectively, a Mutual scheduling mode is adopted, and the two read requests are responded simultaneously in the same time period. Compared with the prior art, the invention flexibly selects different scheduling modes under different conditions by adding the scheduling mechanism into the two read ports of the 2ROr1W memory under the combined working mode, thereby optimizing the read performance of the 2ROr1W memory, and particularly realizing the effect of doubling the capacity but not changing the read performance under the Mutual scheduling mode.
Description
Technical Field
The present invention relates to the field of network communication technologies, and in particular, to a method for scheduling a read operation of a memory and a memory.
Background
The 2ROr1W memory is widely used in the design of dynamic table entries of an ethernet chip, and the memory can provide two read ports or1 write port simultaneously. For internal implementation, it is usually built using two 1RW memories (RAM Block0 and RAM Block1) of the same capacity, as shown in fig. 1.
In the non-joint working mode, the RAM Block0 and the RAM Block1 store completely the same content and backup each other, so that data with the same address in the RAM Block0 and the RAM Block1 can be rewritten at the same time during a write operation, and therefore, two read operations can be completed in the same time period, and the read addresses can be different.
In the cooperative working mode, the RAM Block0 and the RAM Block1 store completely different contents, and have two independent storage structures, and there is no relationship between them, so that the write operation determines that the current write data should be written into the RAM Block0 or the RAM Block1 according to the write address. However, both RAM Block0 and RAM Block1 are 1RW memory structures, and only one write or read operation can be completed in one time period, and when two read operations (read operation 0 and read operation 1) need to access the same RAM Block at the same time, the RAM Block cannot respond to two read operations in the same period, so that it is only limited by design that two read operations cannot be responded to in the same time period.
In summary, the capacity of the 2ROr1W memory is doubled in the combined operation mode, but the read performance is halved, i.e., the two reads in one time period are reduced to one read in one time period.
Disclosure of Invention
The invention aims to provide a scheduling method for a read operation of a memory and the memory.
In order to achieve one of the above objects, an embodiment of the present invention provides a method for scheduling a read operation of a memory, where the memory includes two read ports, and the memory is composed of two 1RW memories, and the method includes:
in the same time period, two read operation requests of a read operation 0 and a read operation 1 exist in two read ports of the memory respectively;
if the two read requests need to access different 1RW memories respectively, a Mutual scheduling mode is adopted, and the two read requests are responded simultaneously in the same time period.
As a further improvement of an embodiment of the present invention, the Mutual scheduling mode specifically includes:
respectively sending the two read operation requests to the corresponding internal read ports of the 1RW memory;
each of the 1RW memories responds to a request for a read operation received by the internal read port.
As a further improvement of an embodiment of the present invention, the determining whether the two requests of the read operation respectively need to access different 1RW memories specifically includes:
acquiring addresses of requests of two read operations;
it is determined whether the two addresses point to different 1RW memories.
As a further improvement of an embodiment of the present invention, the method further comprises:
and if the two read operation requests need to access the same 1RW memory, acquiring the access frequencies of the two read ports in a fixed period, and selecting different scheduling modes according to the access frequencies.
As a further improvement of an embodiment of the present invention, the "selecting different scheduling modes according to the access frequency" specifically includes:
and if the access frequencies of the two read ports are not fixed, adopting an RR scheduling mode.
As a further improvement of an embodiment of the present invention, two read ports of the memory are a read port 0 and a read port 1, and the RR scheduling mode specifically includes:
s61: setting a reading port 0 as a patrol point;
s62: in a time period, if there is a read operation 0 request on the read port 0, responding to the read operation 0 request, and going to step S63; otherwise, if there is a request of read operation 1 in read port 1, responding to the request of read operation 1, and going to step S61; otherwise, setting the read port 1 as a patrol point in the next time period, and entering step S64;
s63: setting a reading port 1 as a patrol point;
s64: in a time period, if there is a request of read operation 1 in read port 1, responding to the request of read operation 1, and going to step S61; otherwise, if there is a request of read operation 0 in read port 0, go to step S63; otherwise, the read port 0 is set as the patrol point in the next time period, and the process proceeds to step S62.
As a further improvement of an embodiment of the present invention, the "selecting different scheduling modes according to the access frequency" specifically includes:
and if the access frequencies of the two ports are not fixed and have weights, adopting a WRR scheduling mode.
As a further improvement of an embodiment of the present invention, two read ports of the memory are a read port 0 and a read port 1, and the WRR scheduling mode specifically includes:
s81: according to the access frequency, the weight N of a read port 0 is set to be N, the weight of a read port 1 is set to be M, wherein M and N are variables, and M and N are constants of positive integers.
S82: setting a reading port 0 as a patrol point;
s83: in a time period, if there is a request of read operation 0 and n >0 in read port 0, responding to the request of read operation 0 and setting n to n-1, proceeding to step S84; otherwise, if there is a request of read operation 1 in read port 1 and m >0, responding to the request of read operation 1, and setting m to m-1, and entering step S82; if n is 0 and m is 0, proceed to step S81; otherwise, setting the read port 1 as a patrol point in the next time period, and entering step S85;
s84: setting a reading port 1 as a patrol point;
s85: in a time period, if there is a request of read operation 1 in read port 1 and m >0, responding to the request of read operation 1 and setting m to m-1, proceeding to step S82; otherwise, if there is a read operation 0 request and n >0 on read port 0, responding to the read operation 0 request and setting n to n-1, and going to step S84; if n is 0 and m is 0, proceed to step S81; otherwise, set read port 0 as the patrol point in the next time period, and proceed to step S83.
In order to achieve one of the above objects, an embodiment of the present invention provides a method for scheduling a read operation of a memory, where the memory is formed by connecting a plurality of 2ROr1W memories in parallel, the memory includes two external read ports, each of the 2ROr1W memories includes two read ports, namely read port 0 and read port 1, there are requests of read operation 0 and read operation 1 at the two external read ports of the memory, respectively, and the requests of read operation 0 and read operation 1 need to obtain a response of each of the 2ROr1W memories at the same time, and the method includes:
dividing time into time slices of slot0 and slot1 which are regularly inverted by using a slot signal;
when the slot signal is slot0, read port 0 of each 2ROr1W memory responds to a read operation 0 request;
when the slot signal is slot1, read port 1 of each 2ROr1W memory responds to a read operation 1 request.
To achieve one of the above objects, an embodiment of the present invention provides a memory, where the memory executes the steps in the scheduling method of the read operation of the memory.
Compared with the prior art, the invention flexibly selects different scheduling modes under different conditions by adding the scheduling mechanism into the two read ports of the 2ROr1W memory under the combined working mode, thereby optimizing the read performance of the 2ROr1W memory, and particularly realizing the effect of doubling the capacity but not changing the read performance under the Mutual scheduling mode.
Drawings
FIG. 1 is a schematic diagram of the internal structure of the 2ROr1W memory of the present invention.
Fig. 2 is a flowchart illustrating a scheduling method of a read operation of a memory according to an embodiment of the invention.
Fig. 3 is a flowchart illustrating RR scheduling according to the present invention.
Fig. 4 is a flow chart illustrating WRR scheduling of the present invention.
FIG. 5 is a diagram illustrating a scheduling method of a read operation of a memory according to another embodiment of the invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present invention.
The memory provided by the invention is a 2ROr1W memory (a two-read or one-write memory), the memory can simultaneously provide two read ports (a read port 0 and a read port 1) or1 write port, the memory is built by two 1RW memories (RAM Block0 and RAM Block1, RB0 and RB1) with the same capacity, and each 1RW memory is provided with an internal read port and a write port. In the 2ROr1W memory of the present invention, as shown in fig. 2, the scheduling method of the read operation of the memory according to an embodiment of the present invention includes:
step S01: in the same time period, two read operation requests of read operation 0 and read operation 1 exist in two read ports of the memory respectively.
In the same time period, there is a read operation 0 request at read port 0 and a read operation 1 request at read port 1 of the memory. It should be noted that, in this document, the request of read operation 0 refers to the read operation request received at read port 0, and the request of read operation 1 refers to the read operation request received at read port 1.
Step S02: if the two read requests need to access different 1RW memories respectively, a Mutual scheduling mode is adopted, and the two read requests are responded simultaneously in the same time period.
It is determined which 1RW memory inside is to be accessed by a request for a read operation. The maximum depth of each 1RW memory is N, namely the accessible address range is 0-N-1, under the combined working mode, the address range of the 2ROr1W memory formed by the two 1RW memories is 0-2N-1, the address range of the first 1RW memory is 0-N-1, and the address range of the second 1RW memory is N-2N-1. Therefore, after acquiring the address of the request of the read operation, it is determined which range the address falls into, and which 1RW memory it is to access (or to which 1RW the address points).
If the two read requests need to access different 1RW memories, it means that one 1RW only needs to respond to one read request in one time period, which can be implemented by the 1RW memory, so that the Mutual scheduling mode is adopted, that is, the two read requests are sent to the corresponding 1RW memories respectively, and the two read requests are responded simultaneously in the same time period.
It should be noted that the Mutual scheduling mode is also called as the exclusive scheduling mode, which means that the 1RW memories that the two read operations need to access are different.
In the embodiment, a scheduling mechanism is added to two read ports of a 2ROr1W memory in a joint working mode, so that the effect of doubling the capacity of the 2ROr1W memory but keeping the read performance unchanged can be realized in a Mutual scheduling mode.
The Mutual scheduling mode specifically includes:
respectively sending the two read operation requests to the corresponding internal read ports of the 1RW memory;
each of the 1RW memories responds to a request for a read operation received by the internal read port.
In a preferred embodiment, the method further comprises:
step S03: and if the two read operation requests need to access the same 1RW memory, acquiring the access frequencies of the two read ports in a fixed period, and selecting different scheduling modes according to the access frequencies.
When two read requests need to access the same 1RW memory, since only one read request can be processed by one RW memory in one time period, the scheduling needs to be performed according to actual requirements. Specifically, the access frequencies of two read ports in a fixed period are obtained, and different scheduling modes are selected according to the access frequencies. For example, in a fixed period, the access frequencies of two read ports are random, that is, not fixed, and if the fairness of scheduling needs to be ensured, an RR scheduling mode (also called Round-Robin or Round-Robin scheduling) is adopted; if there is a priority relationship between two ports, it is necessary to ensure that there is more chance that a read request from one of the ports will be responded to. A WRR scheduling mode (also called Weight Round-Robin or Weight-based Round-Robin) may be used, and a user may flexibly configure the Weight ratio of two read port responses to set the priority relationship. For example, the weight of the read port 0 is set to 9, and the weight of the read port 1 is set to 1, so that when two read ports receive the same number of requests for read operations, the number of responses of the read operation 0 request of the read port 0 is 9 times that of the read operation 1 request of the read port 1 in unit time.
In a specific embodiment, as shown in fig. 3, the RR scheduling mode specifically includes:
s61: setting a reading port 0 as a patrol point;
s62: in a time period, if there is a read operation 0 request on the read port 0, responding to the read operation 0 request, and going to step S63; otherwise, if there is a request of read operation 1 in read port 1, responding to the request of read operation 1, and going to step S61; otherwise, setting the read port 1 as a patrol point in the next time period, and entering step S64;
s63: setting a reading port 1 as a patrol point;
s64: in a time period, if there is a request of read operation 1 in read port 1, responding to the request of read operation 1, and going to step S61; otherwise, if there is a request of read operation 0 in read port 0, go to step S63; otherwise, the read port 0 is set as the patrol point in the next time period, and the process proceeds to step S62.
In another specific embodiment, as shown in fig. 4, the WRR scheduling mode specifically includes:
s81: according to the access frequency, the weight N of a read port 0 is set to be N, the weight of a read port 1 is set to be M, wherein M and N are variables, and M and N are constants of positive integers.
S82: setting a reading port 0 as a patrol point;
s83: in a time period, if there is a request of read operation 0 and n >0 in read port 0, responding to the request of read operation 0 and setting n to n-1, proceeding to step S84; otherwise, if there is a request of read operation 1 in read port 1 and m >0, responding to the request of read operation 1, and setting m to m-1, and entering step S82; if n is 0 and m is 0, proceed to step S81; otherwise, setting the read port 1 as a patrol point in the next time period, and entering step S85;
s84: setting a reading port 1 as a patrol point;
s85: in a time period, if there is a request of read operation 1 in read port 1 and m >0, responding to the request of read operation 1 and setting m to m-1, proceeding to step S82; otherwise, if there is a read operation 0 request and n >0 on read port 0, responding to the read operation 0 request and setting n to n-1, and going to step S84; if n is 0 and m is 0, proceed to step S81; otherwise, set read port 0 as the patrol point in the next time period, and proceed to step S83.
In the scheduling method for the read operation of the memory in the joint working mode according to the embodiment, the scheduling mechanism is added to the two read ports of the 2ROr1W memory, and different scheduling modes are flexibly selected under different conditions, so that the read performance of the 2ROr1W memory is optimized, and particularly, under the Mutual scheduling mode, the effect of doubling the capacity but not changing the read performance is realized.
As shown in fig. 5, the present invention further provides a scheduling method for read operations of a memory, where the memory is formed by connecting a plurality of 2ROr1W memories in parallel (n is shown in fig. 5), the memory includes two external read ports, and each of the 2ROr1W memories includes two read ports, namely read port 0 and read port 1. There are read 0 and read 1 requests on the two external read ports of the memory, which require simultaneous responses from each of the 2ROr1W memories. The method comprises the following steps:
dividing time into time slices of slot0 and slot1 which are regularly inverted by using a slot signal;
when the slot signal is slot0, read port 0 of each 2ROr1W memory responds to a read operation 0 request;
when the slot signal is slot1, read port 1 of each 2ROr1W memory responds to a read operation 1 request.
The requests of two read operations are fixedly distributed to two read ports by using a slot signal 0/1 which is regularly and constantly turned over, and the requests of the two read operations are completely separated from the time perspective. Thus each 2ROr1W memory can respond to read 0 requests at the same time and read 1 requests at the same time, with the entire read 0 and read 1 being responded to at approximately the same time.
The invention also provides a memory, and the memory executes the steps in the scheduling method of the read operation of the memory.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above list of details is only for the purpose of accessing the concrete description of the feasible embodiments of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent embodiments or modifications that do not depart from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method for scheduling read operations of a memory, the memory including two read ports, the memory being formed of two 1RW memories, the method comprising:
in the same time period, two read operation requests of a read operation 0 and a read operation 1 exist in two read ports of the memory respectively;
if the two read requests need to access different 1RW memories respectively, a Mutual scheduling mode is adopted, and the two read requests are responded simultaneously in the same time period.
2. The method according to claim 1, wherein the Mutual scheduling mode specifically comprises:
respectively sending the two read operation requests to the corresponding internal read ports of the 1RW memory;
each of the 1RW memories responds to a request for a read operation received by the internal read port.
3. The method for scheduling read operations of a memory according to claim 1, wherein the determining whether the two read operation requests respectively require access to different 1RW memories specifically comprises:
acquiring addresses of requests of two read operations;
it is determined whether the two addresses point to different 1RW memories.
4. The method of scheduling a read operation of the memory of claim 1, further comprising:
and if the two read operation requests need to access the same 1RW memory, acquiring the access frequencies of the two read ports in a fixed period, and selecting different scheduling modes according to the access frequencies.
5. The method according to claim 4, wherein the "selecting different scheduling modes according to the access frequency" specifically includes:
and if the access frequencies of the two read ports are not fixed, adopting an RR scheduling mode.
6. The scheduling mode of the read operation of the memory according to claim 5, wherein the two read ports of the memory are read port 0 and read port 1, and the RR scheduling mode specifically includes:
s61: setting a reading port 0 as a patrol point;
s62: in a time period, if there is a read operation 0 request on the read port 0, responding to the read operation 0 request, and going to step S63; otherwise, if there is a request of read operation 1 in read port 1, responding to the request of read operation 1, and going to step S61; otherwise, setting the read port 1 as a patrol point in the next time period, and entering step S64;
s63: setting a reading port 1 as a patrol point;
s64: in a time period, if there is a request of read operation 1 in read port 1, responding to the request of read operation 1, and going to step S61; otherwise, if there is a request of read operation 0 in read port 0, go to step S63; otherwise, the read port 0 is set as the patrol point in the next time period, and the process proceeds to step S62.
7. The method according to claim 4, wherein the "selecting different scheduling modes according to the access frequency" specifically includes:
and if the access frequencies of the two ports are not fixed and have weights, adopting a WRR scheduling mode.
8. The scheduling method of the read operation of the memory according to claim 7, wherein the two read ports of the memory are read port 0 and read port 1, and the WRR scheduling mode specifically includes:
s81: according to the access frequency, the weight N of a read port 0 is set to be N, the weight of a read port 1 is set to be M, wherein M and N are variables, and M and N are constants of positive integers.
S82: setting a reading port 0 as a patrol point;
s83: in a time period, if there is a request of read operation 0 and n >0 in read port 0, responding to the request of read operation 0 and setting n to n-1, proceeding to step S84; otherwise, if there is a request of read operation 1 in read port 1 and m >0, responding to the request of read operation 1, and setting m to m-1, and entering step S82; if n is 0 and m is 0, proceed to step S81; otherwise, setting the read port 1 as a patrol point in the next time period, and entering step S85;
s84: setting a reading port 1 as a patrol point;
s85: in a time period, if there is a request of read operation 1 in read port 1 and m >0, responding to the request of read operation 1 and setting m to m-1, proceeding to step S82; otherwise, if there is a read operation 0 request and n >0 on read port 0, responding to the read operation 0 request and setting n to n-1, and going to step S84; if n is 0 and m is 0, proceed to step S81; otherwise, set read port 0 as the patrol point in the next time period, and proceed to step S83.
9. A scheduling method for a read operation of a memory, wherein the memory is formed by connecting a plurality of 2ROr1W memories in parallel, the memory includes two external read ports, each 2ROr1W memory includes two read ports, namely a read port 0 and a read port 1, the two external read ports of the memory respectively have a read operation 0 request and a read operation 1 request, and the read operation 0 request and the read operation 1 request need to simultaneously obtain a response of each 2ROr1W memory, the method includes:
dividing time into time slices of slot0 and slot1 which are regularly inverted by using a slot signal;
when the slot signal is slot0, read port 0 of each 2ROr1W memory responds to a read operation 0 request;
when the slot signal is slot1, read port 1 of each 2ROr1W memory responds to a read operation 1 request.
10. A memory, characterized by:
the memory performs the steps in the method for scheduling a read operation of the memory of any one of claims 1-9.
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