CN110703525A - Array substrate and display panel - Google Patents
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- CN110703525A CN110703525A CN201911007452.1A CN201911007452A CN110703525A CN 110703525 A CN110703525 A CN 110703525A CN 201911007452 A CN201911007452 A CN 201911007452A CN 110703525 A CN110703525 A CN 110703525A
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- 239000000758 substrate Substances 0.000 title claims abstract description 84
- 239000002184 metal Substances 0.000 claims abstract description 76
- 238000001039 wet etching Methods 0.000 claims abstract description 34
- 239000004973 liquid crystal related substance Substances 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 16
- 230000002093 peripheral effect Effects 0.000 abstract description 15
- 239000010410 layer Substances 0.000 description 78
- 239000010408 film Substances 0.000 description 7
- 239000010409 thin film Substances 0.000 description 7
- 230000008054 signal transmission Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- Nonlinear Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides an array substrate and a display panel, wherein the array substrate comprises at least one metal layer, the metal layer is wet-etched to form an effective routing and an invalid routing, the duty ratio of the effective routing is lower than a threshold value corresponding to the setting area of the invalid routing; through wet etching the invalid line of walking on at least one metal level, make the invalid line of walking set up the region that the duty cycle of walking effectively is less than the threshold value to make the invalid line of walking improve the duty cycle of walking effectively, make the holistic duty cycle of metal level unanimous, thereby make the line width of walking effectively that the wet etching formed unanimous, it is less to have peripheral regional metal circuit line width among the current display panel to have alleviated, influences the technical problem of display effect.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a display panel.
Background
In the preparation process of the display panel, the duty ratio of the data lines and the scanning lines in the peripheral area is small, so that the data lines and the scanning lines are wet etched more, the line width of peripheral lines is small, and the display effect is affected due to large voltage drop in the signal transmission process.
Therefore, the technical problem that the display effect is influenced by the small line width of the metal circuit in the peripheral area exists in the existing display panel.
Disclosure of Invention
The invention provides an array substrate and a display panel, which are used for solving the technical problems that the display effect is influenced by the fact that the line width of a metal circuit in a peripheral area is small in the existing display panel.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
the invention provides an array substrate which comprises at least one metal layer, wherein effective routing and invalid routing are formed by wet etching of the metal layer, the duty ratio of the effective routing is lower than a threshold value corresponding to the setting area of the invalid routing.
In the array substrate provided by the invention, the metal layer comprises a source drain layer, the source drain layer is wet etched to form an effective trace, and the effective trace comprises a data line.
In the array substrate provided by the invention, the array substrate comprises a display area, a fan-out area and a binding area, the duty ratio of effective routing lines in the display area is lower than a threshold value, and the invalid routing lines are arranged in the display area.
In the array substrate provided by the invention, the array substrate comprises a display area, a fan-out area and a binding area, the duty ratio of a data line in the fan-out area is lower than that of the data line in the display area, and the invalid routing is arranged in the fan-out area.
In the array substrate provided by the invention, the invalid traces are arranged between the data lines and are insulated from the data lines.
In the array substrate provided by the invention, the invalid wirings are arranged on two sides of the data line, and the invalid wirings are insulated from the data line.
In the array substrate provided by the invention, the distance between the invalid traces and the effective traces is equal to the distance between the effective traces in the display area.
In the array substrate provided by the invention, the shape of the invalid trace comprises at least one of a straight line shape, a rectangular shape and an open rectangular shape.
In the array substrate provided by the invention, the metal layer comprises a gate layer, the gate layer is wet etched to form effective routing, and the effective routing comprises a scanning line.
Meanwhile, the invention provides a display panel which comprises an array substrate, a color film substrate and a liquid crystal layer arranged between the array substrate and the color film substrate, wherein the array substrate comprises at least one metal layer, and the metal layer is subjected to wet etching to form an effective trace and an invalid trace, wherein the duty ratio of the effective trace is lower than a threshold value corresponding to the setting area of the invalid trace.
Has the advantages that: the invention provides an array substrate and a display panel, wherein the array substrate comprises at least one metal layer, the metal layer is wet-etched to form an effective routing and an invalid routing, the duty ratio of the effective routing is lower than a threshold value corresponding to the setting area of the invalid routing; through wet etching the invalid line of walking on at least one metal level, make the invalid line of walking set up the region that the duty cycle of walking effectively is less than the threshold value to make the invalid line of walking improve the duty cycle of walking effectively, make the holistic duty cycle of metal level unanimous, thereby make the line width of walking effectively that the wet etching formed unanimous, it is less to have peripheral regional metal circuit line width among the current display panel to have alleviated, influences the technical problem of display effect.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a first schematic view of an array substrate according to an embodiment of the present invention;
fig. 2 is a second schematic view of an array substrate according to an embodiment of the invention;
fig. 3 is a schematic diagram of a display panel according to an embodiment of the invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
The embodiment of the invention is used for solving the technical problem that the display effect is influenced by smaller line width of a metal line in a peripheral area in the conventional display panel.
As shown in fig. 2, an embodiment of the invention provides an array substrate, where the array substrate includes at least one metal layer, and the metal layer is wet etched to form an effective trace 1271 and an invalid trace 1272, where a duty ratio of the effective trace 1271 is lower than a threshold corresponding to an arrangement area of the invalid trace 1272.
The embodiment of the invention provides an array substrate, which comprises at least one metal layer, wherein the metal layer is subjected to wet etching to form an effective routing and an invalid routing, the duty ratio of the effective routing is lower than a threshold value corresponding to the setting area of the invalid routing; through wet etching the invalid line of walking on at least one metal level, make the invalid line of walking set up the region that the duty cycle of walking effectively is less than the threshold value to make the invalid line of walking improve the duty cycle of walking effectively, make the holistic duty cycle of metal level unanimous, thereby make the line width of walking effectively that the wet etching formed unanimous, it is less to have peripheral regional metal circuit line width among the current display panel to have alleviated, influences the technical problem of display effect.
It should be noted that the duty ratio refers to the size of the space occupied by the metal traces in a unit area, and the metal traces include an invalid trace and an effective trace.
It should be noted that the threshold is determined according to the duty ratio of the actual effective trace, for example, when the duty ratio of the effective trace in the display of the array substrate is a, and the line width of the metal trace meets the requirement when the duty ratio is a, a may be set as the threshold.
As shown in fig. 1, an embodiment of the present invention provides an array substrate, where the array substrate includes a substrate 11, a thin film transistor 12 and a planarization layer 13, where the thin film transistor 12 includes at least one metal layer, and the metal layer is wet-etched to form an effective trace and an invalid trace, where a duty ratio of the effective trace corresponding to a setting region of the invalid trace is lower than a threshold, and in the array substrate, a region of the invalid trace is correspondingly set on a metal layer in the thin film transistor, and a duty ratio of the effective trace is lower than the threshold, so that the duty ratio of the metal trace is increased by the invalid trace, and thus the duty ratios of the metal layers are kept consistent, so that line widths of formed metal lines are kept consistent, and technical problems that a display effect is affected due to a small line width of a metal line.
In one embodiment, as shown in fig. 2, the metal layer includes a source drain layer 127, the source drain layer 127 is wet-etched to form the effective trace 1271 and the ineffective trace 1272, the effective trace 1271 includes a data line, the source drain layer serves as a metal layer in the thin film transistor, when the source, the drain and the data line are formed by wet etching, the duty ratios of the data line in different areas are different due to the arrangement mode of the data line of the metal layer, so that when the source drain layer is prepared, more wet etching solution is used in an area with a duty ratio lower than a threshold value, so that the data line is etched, the line width of the data line is smaller, even the data line is broken, and other problems affect data transmission, by arranging the ineffective trace on the source drain layer, the duty ratio of an area with a duty ratio lower than the threshold value in the source drain layer is increased, so that the line width of the data line in the source drain layer is kept consistent across the, therefore, the phenomenon that the voltage drop in the signal transmission process is caused by different line widths of the data lines in different areas of the source drain layer and even the signal cannot be transmitted because the data lines are broken is avoided.
In an embodiment, as shown in fig. 2, the array substrate includes a display area 241, a fan-out area 242, and a binding area 243, where a duty ratio of an active trace in the display area is lower than a threshold, and an inactive trace is disposed in the display area, and when the duty ratios of different areas in the display area are different, the inactive trace may be disposed in an area where the duty ratio in the display area is lower than the threshold, so that the inactive trace increases the duty ratio, and the duty ratios in the display area are substantially consistent or even consistent, so that line widths of data lines in the display area are consistent, and when signals are transmitted on the data lines, no loss occurs due to a small line width.
In one embodiment, as shown in fig. 2, the array substrate includes a display area 241, a fan-out area 242, and a bonding area 243, the source and drain electrode layers are wet-etched to form a data line 1271, an invalid line 1272, and a bonding terminal 1273, a duty ratio of the data line 1271 in the fan-out area 242 is lower than a duty ratio of the data line in the display area 241, the invalid line 1272 is disposed in the fan-out area, when the data line of the source and drain electrode layers extends to the bonding terminal 1273 from the data line to the bonding area, the data line is gathered in the fan-out area, so that the duty ratio of the data line in the fan-out area is lower than the duty ratio of the data line in the display area, when the duty ratio of the data line in the display area is not less than a threshold value and the duty ratio of the data line in the fan-out area is lower than a threshold value, an invalid line is disposed in the fan-out line, so as to increase the, therefore, the line width of the data line is improved, and the line width of the data line meets the requirement; or the duty ratio of the data lines in the display area can be used as a threshold value, so that the invalid wiring is arranged in the fan-out area, the duty ratios of the effective wiring and the invalid wiring in the fan-out area are equal to the duty ratio of the effective wiring in the display area, the line width of the prepared effective wiring is consistent in all areas of the array substrate, and the loss of signals due to the line width change can be avoided in the transmission process.
In one embodiment, when the duty ratios of the data lines in the display area and the fan-out area are lower than the threshold value, the invalid routing lines can be arranged in the display area and the fan-out area respectively, so that the duty ratios of the metal routing lines in the display area and the fan-out area are improved, the line widths of the data lines in the display area are consistent, and the line widths of the data lines in the display area and the fan-out area are kept consistent.
In an embodiment, as shown in fig. 2, the invalid traces are disposed between the data lines and insulated from the data lines, a distance between each of the data lines in the fan-out region is greater than a distance between each of the data lines in the display region, that is, a duty ratio of the data lines in the fan-out region is smaller than a duty ratio of the data lines in the display region, and the invalid traces may be disposed between the data lines, so as to increase the duty ratio of the metal lines in the fan-out region, so that the duty ratio of the metal lines in the fan-out region is consistent with the duty ratio of the data lines in the display region, so that a line width of the data lines in the fan-out region is consistent with a line width of the metal lines in the display region, and the invalid traces are insulated from the data lines, so that the invalid traces do not affect performance of the data lines.
In one embodiment, the invalid traces are disposed on two sides of the data lines and are insulated from the data lines, in the fan-out area, it is considered that the duty ratio of the metal traces can be improved by disposing the invalid traces on two sides of the data lines, the difficulty of disposing the invalid traces on two sides of the data lines is lower than the difficulty of disposing the invalid traces between the data lines, and meanwhile, the invalid traces are kept insulated from the data lines, so that the invalid traces do not interfere with the data lines.
In an embodiment, since the invalid trace is insulated, when the invalid trace is disposed in the non-light-transmitting area, the invalid trace does not generate capacitance and the like with other metal layers, so that the invalid trace does not affect a driving circuit in the array substrate.
In an embodiment, a distance between the invalid traces and the effective traces is equal to a distance between the effective traces in the display area, and the distance between the invalid traces and the effective traces is equal to the distance between the effective traces in the display area, so that a line width of the invalid traces and the effective traces in the fan-out area is equal to a line width of the effective traces in the display area, and a technical problem that a display effect is affected due to a small line width in the fan-out area in the array substrate is solved.
In one embodiment, the shape of the invalid trace includes at least one of a straight line shape, a rectangular shape and an open rectangle, when the shape of the invalid trace is a straight line shape, the invalid trace is arranged between the invalid trace and the effective trace, so that the distance between the invalid trace and the effective trace on one side is closer, when the distance between the invalid trace and the effective trace on the other side is equal to the duty ratio of the effective trace equal to the threshold value, the distance between the effective trace on the one side is equal to the distance between the invalid trace and the trace on one side, the invalid trace is wet etched by the wet etching solution, the effective trace on the one side is not excessively wet etched, so that the line width of the effective trace on the one side meets the requirement, when the distance between the effective trace and the invalid trace on the other side is equal to the duty ratio of the effective trace, the distance between the effective trace and the invalid trace meets the requirement, so that the display area of the array substrate is consistent with the duty ratio, therefore, the obtained data lines are consistent in line width, and the technical problem that the display effect is influenced by the fact that the line width of a peripheral region metal circuit in the existing display panel is small is solved.
In an embodiment, when the shape of the invalid trace is an open rectangle, as shown in fig. 2, the invalid trace is disposed between the effective traces, such that the distance between the two sides of the invalid trace and the effective trace is relatively short, and when the distance between the sides of the open rectangle is equal to the duty ratio of the effective trace equal to the threshold, the distance between the effective traces is relatively short, i.e., the invalid trace protects the effective trace, and the duty ratios of the invalid trace and the effective trace equal to the threshold, so that the line width of the formed effective trace meets the requirement, thereby avoiding the technical problem that the display effect is affected due to the fact that the peripheral region metal line width is relatively small in the existing display panel.
In one embodiment, the shape of the invalid trace is a rectangle, when an effective trace and an invalid trace are formed by wet etching, the shape of the invalid trace is a rectangle, when an effective trace is formed by wet etching of a wet etching solution between the invalid trace and the effective trace, the wet etching solution is in the rectangle formed by the invalid trace, the invalid trace is wet etched, and the invalid trace does not play a role in signal transmission in the array substrate, so that the invalid trace is wet etched by the wet etching solution, the width of the invalid trace is small, the drive circuit of the array substrate cannot be affected, wet etching cannot be performed on the effective trace by the wet etching solution in the invalid trace subsequently, the effective trace is kept to a required width, and the width of the effective trace is kept consistent.
In one embodiment, the metal layer includes a gate layer, the gate layer is wet etched to form the effective trace and the invalid trace, the effective trace includes a scan line, and when the gate layer is wet etched to form the gate and the scan line, the invalid trace may be set in a region of the gate layer where the duty ratio of the scan line is lower than a threshold value in consideration of different duty ratios of the scan lines in different regions, so that the duty ratios of the metal traces in the respective regions in the gate layer are consistent, the line widths of the scan lines in the respective regions in the gate layer are consistent, and a signal is not lost when transmitted on the scan lines.
As shown in fig. 1, an embodiment of the present invention provides an array substrate, where the array substrate includes a substrate 11, a thin film transistor 12, and a planarization layer 13, where the thin film transistor 12 includes an active layer 121, a first gate insulating layer 122, a first metal layer 123, a second gate insulating layer 124, a second metal layer 125, an interlayer insulating layer 126, and a source drain layer 127, where the first metal layer is used as a gate layer to form a gate and a scan line, the source drain layer forms a source drain and a data line, and at least one film layer of the gate layer and the source drain layer is provided with an invalid trace in an area where a duty ratio of the valid trace is lower than a threshold; in the array substrate, the problem that the duty ratio of a scanning line and a data line is smaller than a threshold value can occur in a gate layer and a source drain layer, so that an invalid line is formed in the gate layer and the source drain layer, the invalid line improves the duty ratio of the scanning line and the data line, the duty ratio of the formed scanning line and the data line on the array substrate is kept consistent, the line widths of the scanning line are kept equal, the line widths of the data line are kept equal, and therefore the scanning line and the data line cannot cause signal loss due to different line widths of all areas when conducting signals, for example, voltage drop, the technical problem that the line width of a metal line in a peripheral area is small and the display effect is influenced in the existing display panel is solved.
In one embodiment, in a fan-out region of an array substrate, a scan line of a gate electrode layer is connected to a binding terminal of a binding region through a metal routing of a source drain electrode layer, and in the fan-out region, when a duty ratio of the scan line is lower than a threshold value, an invalid routing can be arranged on the source drain electrode layer in the fan-out region, so that when the duty ratio of the scan line is lower than the threshold value, the invalid routing increases the duty ratio of the scan line, and the line widths of the scan line are consistent; in the fan-out area of the array substrate, when the duty ratio of effective wiring is smaller than the threshold value, the area where the duty ratio of the effective wiring is lower than the threshold value can be provided with the invalid wiring, so that the duty ratio on the array substrate is consistent, the line width of the effective wiring on the array substrate is consistent, and the technical problem that the display effect is influenced by the fact that the line width of a metal line in a peripheral area is small in the existing display panel is solved.
As shown in fig. 3, an embodiment of the present invention provides a display panel, which includes an array substrate, a color filter substrate 31, and a liquid crystal layer 21 disposed between the array substrate and the color filter substrate, where the array substrate includes at least one metal layer, and the metal layer is wet-etched to form an effective trace 1271 and an invalid trace 1272, where a duty ratio of the effective trace 1271 is lower than a threshold value corresponding to a disposed region of the invalid trace 1272.
The embodiment of the invention provides a display panel, which comprises an array substrate, a color film substrate and a liquid crystal layer arranged between the array substrate and the color film substrate, wherein the array substrate comprises at least one metal layer, and the metal layer is subjected to wet etching to form an effective trace and an invalid trace, wherein the duty ratio of the effective trace is lower than a threshold value corresponding to the setting area of the invalid trace; through wet etching the invalid line of walking on at least one metal level, make the invalid line of walking set up the region that the duty cycle of walking effectively is less than the threshold value to make the invalid line of walking improve the duty cycle of walking effectively, make the holistic duty cycle of metal level unanimous, thereby make the line width of walking effectively that the wet etching formed unanimous, it is less to have peripheral regional metal circuit line width among the current display panel to have alleviated, influences the technical problem of display effect.
In one embodiment, when a thin film transistor of an array substrate is prepared, a wet etching solution is used for wet etching a metal layer when a gate layer and a source drain layer are formed, due to the fact that arrangement, moving directions and the like of metal wires of the gate layer and the source drain layer are different, the duty ratios of effective wires corresponding to different areas can be different, in the area where the duty ratio of the effective wires is lower than a threshold value, due to the fact that spaces among the effective wires or on one side of the effective wires are too large, wet etching solution in the area is more, the effective wires are continuously wet etched by the wet etching solution in the area, and the line width of the effective wires in the area where the duty ratio is lower than the threshold value is reduced; in the embodiment of the invention, the invalid wire is arranged in the area where the duty ratio of the valid wire is lower than the threshold value, so that the amount of solution for wet etching is reduced, and meanwhile, the solution for wet etching is used for wet etching the invalid wire, so that the invalid wire protects the valid wire, the wire widths of the valid wire are kept consistent, and the technical problem that the display effect is influenced because the wire width of a metal circuit in a peripheral area is smaller in the conventional display panel is solved.
According to the above embodiment:
the embodiment of the invention provides an array substrate and a display panel, wherein the display panel comprises an array substrate, a color film substrate and a liquid crystal layer arranged between the array substrate and the color film substrate, the array substrate comprises at least one metal layer, and the metal layer is subjected to wet etching to form an effective trace and an invalid trace, wherein the duty ratio of the effective trace is lower than a threshold value corresponding to a setting area of the invalid trace; through wet etching the invalid line of walking on at least one metal level, make the invalid line of walking set up the region that the duty cycle of walking effectively is less than the threshold value to make the invalid line of walking improve the duty cycle of walking effectively, make the holistic duty cycle of metal level unanimous, thereby make the line width of walking effectively that the wet etching formed unanimous, it is less to have peripheral regional metal circuit line width among the current display panel to have alleviated, influences the technical problem of display effect.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (10)
1. The array substrate is characterized by comprising at least one metal layer, wherein effective wires and invalid wires are formed by wet etching of the metal layer, the duty ratio of the effective wires is lower than a threshold value corresponding to the setting area of the invalid wires.
2. The array substrate of claim 1, wherein the metal layer comprises a source drain layer, the source drain layer is wet etched to form an active trace and an inactive trace, and the active trace comprises a data line.
3. The array substrate of claim 2, wherein the array substrate comprises a display area, a fan-out area and a bonding area, a duty cycle of active traces in the display area is lower than a threshold, and the inactive traces are disposed in the display area.
4. The array substrate of claim 2, wherein the array substrate comprises a display area, a fan-out area and a bonding area, a duty cycle of a data line in the fan-out area is lower than a duty cycle of a data line in the display area, and the invalid trace is disposed in the fan-out area.
5. The array substrate of claim 4, wherein the inactive traces are disposed between the data lines and are insulated from the data lines.
6. The array substrate of claim 4, wherein the inactive traces are disposed on two sides of the data lines and are insulated from the data lines.
7. The array substrate of claim 6, wherein a distance between the inactive traces and the active traces is equal to a distance between active traces in the display area.
8. The array substrate of claim 6, wherein the shape of the inactive trace comprises at least one of a straight line shape, a rectangular shape, and an open rectangular shape.
9. The array substrate of claim 1, wherein the metal layer comprises a gate layer, and the gate layer is wet etched to form active traces, the active traces comprising scan lines.
10. The display panel is characterized by comprising an array substrate, a color film substrate and a liquid crystal layer arranged between the array substrate and the color film substrate, wherein the array substrate comprises at least one metal layer, effective routing and invalid routing are formed by wet etching of the metal layer, the duty ratio of the effective routing is lower than a threshold value corresponding to a setting area of the invalid routing.
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| CN106597765A (en) * | 2016-12-08 | 2017-04-26 | 深圳市华星光电技术有限公司 | Display device, display panel, and packaging method for display panel |
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2019
- 2019-10-22 CN CN201911007452.1A patent/CN110703525A/en active Pending
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| EP1164621A2 (en) * | 2000-06-14 | 2001-12-19 | Fujitsu Hitachi Plasma Display Limited | Electrode structure of display panel and electrode forming method |
| TWM410891U (en) * | 2010-10-27 | 2011-09-01 | Chunghwa Picture Tubes Ltd | Active device array substrate and liquid crystal display panel |
| CN106597765A (en) * | 2016-12-08 | 2017-04-26 | 深圳市华星光电技术有限公司 | Display device, display panel, and packaging method for display panel |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
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