CN110690281A - Semiconductor device and manufacturing method - Google Patents

Semiconductor device and manufacturing method Download PDF

Info

Publication number
CN110690281A
CN110690281A CN201810731422.4A CN201810731422A CN110690281A CN 110690281 A CN110690281 A CN 110690281A CN 201810731422 A CN201810731422 A CN 201810731422A CN 110690281 A CN110690281 A CN 110690281A
Authority
CN
China
Prior art keywords
floating gate
grounded
gate
semiconductor device
isolation layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810731422.4A
Other languages
Chinese (zh)
Other versions
CN110690281B (en
Inventor
裴风丽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SUZHOU JIEXINWEI SEMICONDUCTOR TECHNOLOGY Co Ltd
Original Assignee
SUZHOU JIEXINWEI SEMICONDUCTOR TECHNOLOGY Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SUZHOU JIEXINWEI SEMICONDUCTOR TECHNOLOGY Co Ltd filed Critical SUZHOU JIEXINWEI SEMICONDUCTOR TECHNOLOGY Co Ltd
Priority to CN201810731422.4A priority Critical patent/CN110690281B/en
Publication of CN110690281A publication Critical patent/CN110690281A/en
Application granted granted Critical
Publication of CN110690281B publication Critical patent/CN110690281B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/40FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/015Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

本申请实施例提供的半导体器件及制造方法。所述半导体器件包括:衬底;设置于所述衬底上的半导体层;设置于所述半导体层远离所述衬底一侧的隔离层;设置于隔离层上的源极和漏极,所述源极和漏极与所述隔离层欧姆接触;以及设置在所述隔离层上的栅极和至少一个接地或经过接地处理的接地浮栅。通过在源极与漏极之间设置至少一个接地或经过接地处理的接地浮栅,避免浮栅中的漏电流对浮栅产生的电场尖峰峰值的影响,从而使基于电场尖峰的电场积分增大,提高半导体器件的工作电压,从而提高半导体器件的整体可靠性。

Figure 201810731422

The semiconductor device and the manufacturing method provided by the embodiments of the present application. The semiconductor device comprises: a substrate; a semiconductor layer disposed on the substrate; an isolation layer disposed on the side of the semiconductor layer away from the substrate; source and drain electrodes disposed on the isolation layer, the the source electrode and the drain electrode are in ohmic contact with the isolation layer; and a gate electrode and at least one grounded or grounded floating gate disposed on the isolation layer. By arranging at least one grounded or grounded floating gate between the source and the drain, the effect of the leakage current in the floating gate on the peak value of the electric field generated by the floating gate is avoided, thereby increasing the electric field integral based on the electric field peak , improve the working voltage of the semiconductor device, thereby improving the overall reliability of the semiconductor device.

Figure 201810731422

Description

半导体器件及制造方法Semiconductor device and manufacturing method

技术领域technical field

本申请涉及半导体及半导体制造技术领域,具体而言,涉及一种半导体器件及制造方法。The present application relates to the technical field of semiconductors and semiconductor manufacturing, and in particular, to a semiconductor device and a manufacturing method.

背景技术Background technique

高电子迁移率晶体管(High Electron Mobility Transistor,HEMT)中的平面沟道场效应晶体管,如氮化镓高电子迁移率晶体管(GaNHEMT)和砷化镓高电子迁移率晶体管(GaAs HEMT)等器件,其包括源极(Source,S)、栅极(Gate,G)和漏极(Drain,D),电场会聚集在栅极靠近漏极的边沿,形成一个电场尖峰。当栅极和漏极之间施加的电压逐步增加,并导致这个电场尖峰峰值处的电场高于半导体材料的临界电场时,器件就会被击穿而失效。同时,由于器件承受的击穿电压(承压)是栅极和漏极之间电场的积分,与均匀分布的电场相比较,器件位于栅极边沿的电场尖峰峰值越尖锐,器件承受的击穿电压就越小。Planar channel field effect transistors in High Electron Mobility Transistor (HEMT), such as Gallium Nitride High Electron Mobility Transistor (GaNHEMT) and Gallium Arsenide High Electron Mobility Transistor (GaAs HEMT) and other devices. Including the source (Source, S), gate (Gate, G) and drain (Drain, D), the electric field will gather at the edge of the gate close to the drain, forming an electric field peak. When the voltage applied between the gate and the drain is gradually increased and the electric field at the peak value of this electric field is higher than the critical electric field of the semiconductor material, the device will break down and fail. At the same time, since the breakdown voltage (stressed) of the device is the integral of the electric field between the gate and the drain, compared with a uniformly distributed electric field, the sharper the peak value of the electric field at the gate edge of the device, the higher the breakdown voltage of the device. the lower the voltage.

为了提高器件工作电压,几种常用的缓解栅极边沿的电场尖峰的方法包括:采用场板结构的栅极、在栅极和漏极之间添加浮栅等。开关器件经常使用在栅极和漏极之间添加浮栅的方法来提高工作电压。如图1所示,增加浮栅后,在栅极和漏极之间增加了几个电场尖峰,增加的电场尖峰扩大了栅极和漏极之间的电场积分,升高了器件的击穿电压。如果不使用浮栅,电场就只会在栅极边沿形成一个尖峰,其对应的能承受的最高电压就是如图1所示的灰色三角区域的面积,也就是电场的积分。但是,在采用浮栅结构的器件中,由于浮栅上存在漏电流,使得浮栅产生的电场尖峰峰值小于理论预期,见图1中虚线所示的电场强度分布。较低的电场峰值意味着其积分所得电压也小于理想情况下的计算。情况严重时,如图1所示,靠近漏极的几个浮栅根本起不到提高器件击穿电压的作用。In order to increase the operating voltage of the device, several commonly used methods for mitigating the electric field peak at the gate edge include: using a gate with a field plate structure, adding a floating gate between the gate and the drain, and so on. Switching devices often use the addition of a floating gate between the gate and drain to increase the operating voltage. As shown in Figure 1, after the floating gate is added, several electric field spikes are added between the gate and the drain, and the increased electric field spikes expand the electric field integral between the gate and the drain, increasing the breakdown of the device Voltage. If the floating gate is not used, the electric field will only form a peak at the edge of the gate, and the corresponding highest voltage that can be tolerated is the area of the gray triangle area shown in Figure 1, which is the integral of the electric field. However, in a device using a floating gate structure, due to the leakage current on the floating gate, the peak value of the electric field generated by the floating gate is smaller than the theoretical expectation, as shown in the electric field intensity distribution shown by the dotted line in Figure 1. The lower peak value of the electric field means that its integrated voltage is also smaller than the ideal calculation. In severe cases, as shown in Figure 1, several floating gates close to the drain can't improve the breakdown voltage of the device at all.

发明内容SUMMARY OF THE INVENTION

有鉴于此,本申请的目的在于提供一种半导体器件,以及用于制造该半导体器件的方法,以解决上述问题。In view of this, the purpose of the present application is to provide a semiconductor device and a method for manufacturing the semiconductor device to solve the above problems.

第一方面,本申请实施例提供一种半导体器件,所述半导体器件包括:In a first aspect, embodiments of the present application provide a semiconductor device, the semiconductor device comprising:

衬底;substrate;

设置于所述衬底上的半导体层;a semiconductor layer disposed on the substrate;

设置于所述半导体层远离所述衬底一侧的隔离层;an isolation layer disposed on the side of the semiconductor layer away from the substrate;

设置于隔离层上的源极和漏极,所述源极和漏极与所述隔离层欧姆接触;以及a source electrode and a drain electrode disposed on the isolation layer, the source electrode and the drain electrode being in ohmic contact with the isolation layer; and

设置在所述隔离层上的栅极和至少一个接地或经过接地处理的接地浮栅。A gate disposed on the isolation layer and at least one grounded or grounded floating gate.

可选地,在本实施例中,所述接地浮栅的数量为多个,多个所述接地浮栅彼此分离设置。Optionally, in this embodiment, the number of the grounded floating gates is multiple, and the multiple grounded floating gates are provided separately from each other.

可选地,在本实施例中,所述半导体器件还包括设置在所述隔离层远离衬底的一侧的第一介质层,所述接地浮栅为条形,多个所述接地浮栅间隔设置在所述第一介质层上。Optionally, in this embodiment, the semiconductor device further includes a first dielectric layer disposed on a side of the isolation layer away from the substrate, the grounded floating gate is strip-shaped, and a plurality of the grounded floating gates Spacers are provided on the first dielectric layer.

可选地,在本实施例中,所述接地浮栅包括设置于所述隔离层上的第二介质层以及位于该第二介质层上的浮栅导体。Optionally, in this embodiment, the grounded floating gate includes a second dielectric layer disposed on the isolation layer and a floating gate conductor located on the second dielectric layer.

可选地,在本实施例中,所述接地浮栅为肖特基接地浮栅或绝缘接地浮栅。Optionally, in this embodiment, the grounded floating gate is a Schottky grounded floating gate or an insulated grounded floating gate.

可选地,在本实施例中,所述半导体器件还包括设置于所述栅极与所述隔离层之间的带负电荷的栅极浮栅,所述栅极浮栅与所述栅极之间设置有绝缘介质。Optionally, in this embodiment, the semiconductor device further includes a negatively charged gate floating gate disposed between the gate and the isolation layer, the gate floating gate and the gate An insulating medium is provided between them.

可选地,在本实施例中,所述绝缘接地浮栅与所述栅极浮栅的金属部分采用相同的金属材料制造而成。Optionally, in this embodiment, the insulating grounded floating gate and the metal part of the gate floating gate are made of the same metal material.

可选地,在本实施例中,所述栅极与所述接地浮栅为叠层结构,所述隔离层上设置有第三介质层,所述第三介质层包裹或覆盖所述栅极与至少一个所述接地浮栅。Optionally, in this embodiment, the gate and the grounded floating gate are in a stacked structure, a third dielectric layer is disposed on the isolation layer, and the third dielectric layer wraps or covers the gate with at least one of the grounded floating gates.

第二方面,本申请实施例还提供一种用于制造第一方面中半导体器件的制造方法,所述方法包括:In a second aspect, embodiments of the present application further provide a method for manufacturing the semiconductor device in the first aspect, the method comprising:

基于一衬底制作形成半导体层;Forming a semiconductor layer based on a substrate;

在所述半导体层远离所述衬底的一侧制作形成隔离层;Forming an isolation layer on the side of the semiconductor layer away from the substrate;

在所述隔离层远离所述衬底的一侧制作形成与所述隔离层欧姆接触的源极和漏极;Fabricating a source electrode and a drain electrode forming ohmic contact with the isolation layer on the side of the isolation layer away from the substrate;

在所述隔离层远离所述半导体层的一侧制作栅极和至少一个接地或经过接地处理的接地浮栅。A gate and at least one grounded or grounded floating gate are fabricated on a side of the isolation layer away from the semiconductor layer.

可选地,在本实施例中,在所述隔离层远离所述半导体层的一侧制作栅极和至少一个接地或经过接地处理的接地浮栅,包括:Optionally, in this embodiment, forming a gate and at least one grounded or grounded floating gate on a side of the isolation layer away from the semiconductor layer, including:

在所述隔离层上的所述源极与漏极之间的区域沉积一第二介质层;depositing a second dielectric layer on the isolation layer in the region between the source electrode and the drain electrode;

在所述第二介质层远离所述隔离层的一侧上形成栅极导体和至少一个浮栅导体;forming a gate conductor and at least one floating gate conductor on a side of the second dielectric layer away from the isolation layer;

形成由所述栅极导体与第二介质层形成的栅极和由所述浮栅导体与第二介质层形成的浮栅;forming a gate formed by the gate conductor and the second dielectric layer and a floating gate formed by the floating gate conductor and the second dielectric layer;

将所述浮栅接地或接地处理得到接地浮栅。The floating gate is grounded or grounded to obtain a grounded floating gate.

可选地,在本实施例中,在所述隔离层远离所述半导体层的一侧制作栅极和至少一个接地或经过接地处理的接地浮栅之后,所述方法还包括:Optionally, in this embodiment, after forming a gate and at least one grounded or grounded floating gate on the side of the isolation layer away from the semiconductor layer, the method further includes:

在所述第二介质层被蚀刻掉的区域上沉积第三介质层,使所述第三介质层包裹或覆盖所述叠层栅极与至少一个所述叠层接地浮栅。A third dielectric layer is deposited on the area where the second dielectric layer is etched away, so that the third dielectric layer wraps or covers the stacked gate and at least one of the stacked grounded floating gates.

本申请实施例提供的半导体器件及其制造方法。所述半导体器件包括:衬底;设置于所述衬底上的半导体层;设置于所述半导体层远离所述衬底一侧的隔离层;设置于隔离层上的源极和漏极,所述源极和漏极与所述隔离层欧姆接触;以及设置在所述隔离层上的栅极和至少一个接地或经过接地处理的接地浮栅。通过在源极与漏极之间设置至少一个接地或经过接地处理的接地浮栅,避免浮栅中的漏电流对浮栅产生的电场尖峰峰值的影响,从而使基于电场尖峰的电场积分增大,提高半导体器件的工作电压,从而提高半导体器件的整体可靠性。The semiconductor device and the manufacturing method thereof provided by the embodiments of the present application. The semiconductor device comprises: a substrate; a semiconductor layer disposed on the substrate; an isolation layer disposed on the side of the semiconductor layer away from the substrate; source and drain electrodes disposed on the isolation layer, the the source electrode and the drain electrode are in ohmic contact with the isolation layer; and a gate electrode and at least one grounded or grounded floating gate disposed on the isolation layer. By arranging at least one grounded or grounded floating gate between the source and the drain, the effect of the leakage current in the floating gate on the peak value of the electric field generated by the floating gate is avoided, thereby increasing the electric field integral based on the electric field peak , improve the working voltage of the semiconductor device, thereby improving the overall reliability of the semiconductor device.

附图说明Description of drawings

为了更清楚地说明本申请实施例的技术方案,下面将对实施例中所需要使用的附图作简单地介绍。应当理解,以下附图仅示出了本申请的某些实施例,因此不应被看作是对范围的限定,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他相关的附图。In order to illustrate the technical solutions of the embodiments of the present application more clearly, the accompanying drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation of the scope. Other related figures are obtained from these figures.

图1为本现有技术中浮栅设计与电场强度之间的对应关系示意图;1 is a schematic diagram of the corresponding relationship between floating gate design and electric field strength in the prior art;

图2-图6为本申请实施例提供的半导体器件的多种变形结构示意图;2 to 6 are schematic diagrams of various modified structures of the semiconductor device provided by the embodiments of the present application;

图7为本申请实施例提供的半导体器件的制程流程图;FIG. 7 is a process flow diagram of a semiconductor device provided by an embodiment of the present application;

图8A-图8G为本请实施例提供的半导体器件的制程图。8A-8G are process diagrams of the semiconductor device provided by the present embodiment.

图标:10-半导体器件;11-衬底;12-半导体层;13-隔离层;14-源极;15-漏极;16-栅极;161-栅极导体;17-接地浮栅;171-浮栅导体;18-栅极浮栅;19-第一介质层;20-第二介质层;21-第三介质层。Icon: 10-semiconductor device; 11-substrate; 12-semiconductor layer; 13-isolation layer; 14-source; 15-drain; 16-gate; 161-gate conductor; 17-grounded floating gate; 171 - floating gate conductor; 18 - gate floating gate; 19 - first dielectric layer; 20 - second dielectric layer; 21 - third dielectric layer.

具体实施方式Detailed ways

下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述。显然,所描述的实施例仅仅是本申请的一部分实施例,而不是全部的实施例。通常在此处附图中描述和示出的本申请实施例的组件可以以各种不同的配置来布置和设计。The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

因此,以下对在附图中提供的本申请的实施例的详细描述并非旨在限制要求保护的本申请的范围,而是仅仅表示本申请的选定实施例。基于本申请的实施例,本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例,都属于本申请保护的范围。Thus, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the application as claimed, but is merely representative of selected embodiments of the application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

应注意到:相似的标号和字母在下面的附图中表示类似项,因此,一旦某一项在一个附图中被定义,则在随后的附图中不需要对其进行进一步定义和解释。It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

在本发明的描述中,需要说明的是,术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系,或者是该发明产品使用时惯常摆放的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。此外,术语“第一”、“第二”等仅用于区分描述,而不能理解为指示或暗示相对重要性。In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, or is usually placed when the product of the invention is used. The orientation or positional relationship is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first", "second", etc. are only used to differentiate the description and should not be construed to indicate or imply relative importance.

请参照图2,图2示出了本申请实施例提供的半导体器件10的结构示意图。半导体器件10包括衬底11、半导体层12、隔离层13、源极14、漏极15、栅极16及接地浮栅17。Please refer to FIG. 2 , which shows a schematic structural diagram of a semiconductor device 10 provided by an embodiment of the present application. The semiconductor device 10 includes a substrate 11 , a semiconductor layer 12 , an isolation layer 13 , a source electrode 14 , a drain electrode 15 , a gate electrode 16 and a grounded floating gate 17 .

半导体层12形成于衬底11的上表面,隔离层13设置在所述半导体层12远离衬底11的一侧。源极14和漏极15设置在隔离层13远离所述衬底11一侧,且源极14和漏极15与隔离层13欧姆接触。栅极16和至少一个接地或经过接地处理的接地浮栅17设置在隔离层13远离衬底11的一侧。The semiconductor layer 12 is formed on the upper surface of the substrate 11 , and the isolation layer 13 is provided on the side of the semiconductor layer 12 away from the substrate 11 . The source electrode 14 and the drain electrode 15 are disposed on the side of the isolation layer 13 away from the substrate 11 , and the source electrode 14 and the drain electrode 15 are in ohmic contact with the isolation layer 13 . The gate 16 and at least one grounded or grounded floating gate 17 are disposed on the side of the isolation layer 13 away from the substrate 11 .

在本实施例中,接地浮栅17相对于普通浮栅的区别在于接地浮栅17经过接地处理或直接接地,接地浮栅17中的漏电流远小于普通浮栅中的漏电流。从而使接地浮栅17产生的电场尖峰峰值较大,基于电场尖峰的电场积分较大,提高半导体器件10的工作电压。In this embodiment, the difference between the grounded floating gate 17 and the common floating gate is that the grounded floating gate 17 is grounded or directly grounded, and the leakage current in the grounded floating gate 17 is much smaller than that in the common floating gate. Therefore, the peak value of the electric field generated by the grounded floating gate 17 is larger, the electric field integral based on the electric field peak is larger, and the working voltage of the semiconductor device 10 is improved.

请再次参照图2,在本实施例中,半导体层12采用GaN材料制造而成,隔离层采用AlGaN材料制造而成。由于半导体层12与隔离层具有不同带隙,半导体器件10还包括位于半导体层12与隔离层相交界的二维电子气层2DEG。Referring to FIG. 2 again, in this embodiment, the semiconductor layer 12 is made of GaN material, and the isolation layer is made of AlGaN material. Since the semiconductor layer 12 and the isolation layer have different band gaps, the semiconductor device 10 further includes a two-dimensional electron gas layer 2DEG located at the interface between the semiconductor layer 12 and the isolation layer.

接下来对本实施例的可能实现方式进行介绍,可以理解地是,下述的描述仅仅是本申请中半导体器件10的可能实现方式,不应当理解为对本申请的限定,在本申请的其他实施例中还可以采用除下述实施方式之外的其他实现方式。Next, the possible implementations of this embodiment will be introduced. It can be understood that the following descriptions are only possible implementations of the semiconductor device 10 in this application, and should not be construed as a limitation of this application. In other embodiments of this application In addition to the following implementation manners, other implementation manners may also be adopted.

请再次参照图2,在本实施例的第一种实施方式中,接地浮栅17为肖特基浮栅,接地浮栅17的金属与隔离层13为肖特基接触。在此种情况下,在半导体器件10出厂前,需要对上述接地浮栅部分或全部做接地处理,具体地,可以通过金属导线将接地浮栅17的金属部分与地连接,以去除接地浮栅17上的自由电荷,此后将金属导线去除,接地浮栅17与外界没有电连接,接地浮栅17在电位上是浮空的,接地浮栅17与器件的各个电极彼此隔离没有电连接,同时在接地浮栅17为多个时,每个接地浮栅17之间相互彼此分离。在此种设置下,该接地浮栅17相对于普通浮栅的漏电流更小,可以提高半导体器件10的击穿电压。Referring to FIG. 2 again, in the first implementation manner of this embodiment, the grounded floating gate 17 is a Schottky floating gate, and the metal of the grounded floating gate 17 is in Schottky contact with the isolation layer 13 . In this case, before the semiconductor device 10 leaves the factory, part or all of the grounded floating gate needs to be grounded. Specifically, the metal part of the grounded floating gate 17 can be connected to the ground through a metal wire to remove the grounded floating gate The free charge on 17, after which the metal wire is removed, the grounded floating gate 17 is not electrically connected to the outside world, the grounded floating gate 17 is floating in potential, and the grounded floating gate 17 is isolated from each electrode of the device and has no electrical connection. When there are multiple grounded floating gates 17 , each of the grounded floating gates 17 is separated from each other. Under this arrangement, the leakage current of the grounded floating gate 17 is smaller than that of the common floating gate, which can improve the breakdown voltage of the semiconductor device 10 .

请再次参照图2,在本实施例的第二种实施方式中,接地浮栅17的全部或部分直接接地,各接地浮栅彼此独立,相互之间没有物理连接,接地浮栅17与半导体器件10的各个电极之间也没有物理连接。此种接地浮栅17可以增加栅极16上的电场尖峰,大大提高半导体器件10的击穿电压。Referring to FIG. 2 again, in the second implementation of this embodiment, all or part of the grounded floating gate 17 is directly grounded, and the grounded floating gates are independent of each other and are not physically connected to each other. The grounded floating gate 17 is connected to the semiconductor device. There is also no physical connection between the various electrodes of 10. The grounded floating gate 17 can increase the electric field peak on the gate 16 and greatly increase the breakdown voltage of the semiconductor device 10 .

请参照图3,图3给出半导体器件10为增强型开关器件的情形,在本实施例的第三种实施方式中,半导体器件10包括设置在栅极16与隔离层13之间的栅极浮栅18,其中,栅极浮栅18上带有负电荷。栅极浮栅18与栅极16之间设置有绝缘介质。在本实施方式中,可以在出厂前对该栅极浮栅18进行预充电。Please refer to FIG. 3 . FIG. 3 shows a situation in which the semiconductor device 10 is an enhancement type switching device. In the third implementation manner of this embodiment, the semiconductor device 10 includes a gate electrode disposed between the gate electrode 16 and the isolation layer 13 . The floating gate 18, wherein the gate floating gate 18 has a negative charge on it. An insulating medium is provided between the gate floating gate 18 and the gate 16 . In this embodiment, the gate floating gate 18 may be precharged before shipment.

在第三实施方式中,上述栅极浮栅18的材料可为半绝缘材料,可包括富氧多晶硅或富硅的氮化硅。采用上述材料的栅极浮栅18具备稳定的存储电子的能力,采用上述材料的栅极浮栅18可在常温下绝缘,方块电阻率在100G欧姆以上,在某特定条件下可导电,方块电阻率在100M欧姆以下。在半导体器件10出厂前对栅极浮栅18进行预充,预充时栅极浮栅18导电,使电子存储到栅极浮栅18中。此后,半导体器件10在工作过程中栅极浮栅18绝缘,使电子存储其中而不泄露,防止了栅极浮栅18漏电造成的半导体阈值漂移。另外,上述栅极浮栅18的材料也可为导体材料。In the third embodiment, the material of the above-mentioned gate floating gate 18 may be a semi-insulating material, which may include oxygen-rich polysilicon or silicon-rich silicon nitride. The gate floating gate 18 using the above-mentioned materials has the ability to store electrons stably, the gate floating gate 18 using the above-mentioned materials can be insulated at normal temperature, the sheet resistivity is above 100G ohms, and it can conduct electricity under certain conditions, and the sheet resistance rate below 100M ohms. The gate floating gate 18 is precharged before the semiconductor device 10 leaves the factory. During the precharging, the gate floating gate 18 conducts electricity, so that electrons are stored in the gate floating gate 18 . Thereafter, the gate floating gate 18 of the semiconductor device 10 is insulated during operation, so that electrons are stored therein without leakage, and the semiconductor threshold shift caused by the leakage of the gate floating gate 18 is prevented. In addition, the material of the above-mentioned gate floating gate 18 may also be a conductor material.

具体地,栅极浮栅18的材料为富氧多晶硅,在半导体器件10出厂前对栅极浮栅18进行预充(校准)时,将栅极浮栅18加热到200摄氏度,使得栅极浮栅18的材料由绝缘材料转变成为导电材料,通过电容充电的方式,使栅极浮栅18积累足够多且呈均匀分布的电子,降低栅极浮栅18电势,使半导体器件10得到正的开启电压,从而得到增强型开关器件。栅极浮栅18写入电子后,将温度降低到室温,使栅极浮栅18材料恢复到绝缘属性,将写入到栅极浮栅18的电子冻结在栅极浮栅18中,从而起到增强型开关器件初始阈值的作用。Specifically, the material of the gate floating gate 18 is oxygen-rich polysilicon. When the gate floating gate 18 is precharged (calibrated) before the semiconductor device 10 leaves the factory, the gate floating gate 18 is heated to 200 degrees Celsius to make the gate floating The material of the gate 18 is changed from an insulating material to a conductive material, and the gate floating gate 18 accumulates enough and uniformly distributed electrons by means of capacitive charging, which reduces the potential of the gate floating gate 18 and enables the semiconductor device 10 to be positively turned on. voltage, resulting in an enhancement-mode switching device. After the gate floating gate 18 writes electrons, the temperature is lowered to room temperature, so that the material of the gate floating gate 18 is restored to its insulating properties, and the electrons written into the gate floating gate 18 are frozen in the gate floating gate 18, so as to activate the gate floating gate 18. to the initial threshold of the enhancement-mode switching device.

在第三种实施方式中,同时采用接地浮栅17和栅极浮栅18可以大大提高开关器件的击穿电压。In the third embodiment, the use of the grounded floating gate 17 and the gated floating gate 18 at the same time can greatly improve the breakdown voltage of the switching device.

请参照图4,在本实施例的第四种实施方式中,提供一种接地浮栅17为绝缘接地浮栅的情形,其中,绝缘接地浮栅是在上述实施方式中描述的接地浮栅17的基础上在接地浮栅17与隔离层13接触的地方增加绝缘介质,如此可以降低接地浮栅17中的漏电流,提高半导体器件10的击穿电压。Referring to FIG. 4 , in a fourth implementation of this embodiment, a situation is provided in which the grounded floating gate 17 is an insulated grounded floating gate, wherein the insulated grounded floating gate is the grounded floating gate 17 described in the above-mentioned implementation manner. In addition, an insulating medium is added where the grounded floating gate 17 is in contact with the isolation layer 13 , so that the leakage current in the grounded floating gate 17 can be reduced and the breakdown voltage of the semiconductor device 10 can be improved.

请参照图5,在本实施例的第五种实施方式中,在同一半导体器件10上可以采用不同类型的接地浮栅17,就比如,在半导体器件10上同时采用绝缘接地浮栅和肖特基接地浮栅。具体地,可以将绝缘接地浮栅设置在栅极附近,这样可以降低接地浮栅的漏电流,提高半导体器件的击穿电压。Referring to FIG. 5 , in the fifth implementation of this embodiment, different types of grounded floating gates 17 can be used on the same semiconductor device 10 , for example, the semiconductor device 10 can be simultaneously used with insulated grounded floating gates and Schotts. Base ground floating gate. Specifically, the insulated grounded floating gate can be arranged near the gate, which can reduce the leakage current of the grounded floating gate and improve the breakdown voltage of the semiconductor device.

请参照图6,在本实施例的第六种实施方式中,所述接地浮栅17可以为条形,在本实施方式中,半导体器件10还包括设置在隔离层13远离衬底11的一侧的第一介质层19,多个条形接地浮栅17设置在第一介质层19上,条形接地浮栅17之间彼此隔离设置。在本实施方式中,即使单个条形接地浮栅17漏电,也不会影响整体接地浮栅17的漏电,整体接地浮栅17的漏电还是较小,如此可以提高半导体器件10的击穿电压和可靠性。Referring to FIG. 6 , in a sixth implementation manner of the present embodiment, the grounded floating gate 17 may be in a strip shape. In this implementation manner, the semiconductor device 10 further includes a spacer disposed on the isolation layer 13 away from the substrate 11 . On the first dielectric layer 19 on the side, a plurality of strip-shaped grounded floating gates 17 are provided on the first dielectric layer 19, and the strip-shaped grounded floating gates 17 are isolated from each other. In this embodiment, even if a single strip-shaped grounded floating gate 17 leaks, it will not affect the leakage of the overall grounded floating gate 17, and the leakage of the overall grounded floating gate 17 is still small, which can improve the breakdown voltage of the semiconductor device 10 and reliability.

在本实施例中,接地浮栅为双层结构,可以参照图8E,接地浮栅17包括设置于隔离层13上的第二介质层20和位于该第二介质层20上的浮栅导体171。In this embodiment, the grounded floating gate has a double-layer structure. Referring to FIG. 8E , the grounded floating gate 17 includes a second dielectric layer 20 disposed on the isolation layer 13 and a floating gate conductor 171 located on the second dielectric layer 20 . .

进一步地,在本实施例中,绝缘接地浮栅与栅极浮栅18的金属部分采用相同的金属材料制造而成。Further, in this embodiment, the insulating grounded floating gate and the metal portion of the gate floating gate 18 are made of the same metal material.

上述实施例公开的半导体器件10,在源极14与漏极15之间设置至少一个接地或经过接地处理的接地浮栅17,避免浮栅中的漏电流对浮栅产生的电场尖峰峰值的影响,从而使基于电场尖峰的电场积分增大,提高半导体器件10的工作电压,和整体可靠性。In the semiconductor device 10 disclosed in the above embodiments, at least one grounded or grounded floating gate 17 is arranged between the source 14 and the drain 15 to avoid the influence of the leakage current in the floating gate on the peak value of the electric field generated by the floating gate. , thereby increasing the electric field integral based on the electric field peak, improving the operating voltage and overall reliability of the semiconductor device 10 .

请参照图8G,在本实施例中,栅极16与接地浮栅17为叠层结构,隔离层13上设置有第三介质层21,所述第三介质层21包裹或覆盖栅极16与至少一个接地浮栅17。Referring to FIG. 8G , in this embodiment, the gate 16 and the grounded floating gate 17 are in a stacked structure, and a third dielectric layer 21 is disposed on the isolation layer 13 , and the third dielectric layer 21 wraps or covers the gate 16 and the grounded floating gate 17 . At least one grounded floating gate 17 .

请参照图7,本申请实施例还提供一种半导体器件10的制造方法,该制造方法用于制造上面实施例所述的半导体器件10,所述方法包括以下具体步骤:Referring to FIG. 7 , an embodiment of the present application further provides a method for manufacturing a semiconductor device 10 , which is used for manufacturing the semiconductor device 10 described in the above embodiment, and the method includes the following specific steps:

步骤S710,请参照图8A,基于一衬底11制作形成半导体层12。In step S710 , referring to FIG. 8A , the semiconductor layer 12 is formed based on a substrate 11 .

步骤S720,请参照图8B,在半导体层12远离衬底11的一侧制作形成隔离层13。In step S720 , referring to FIG. 8B , an isolation layer 13 is formed on the side of the semiconductor layer 12 away from the substrate 11 .

步骤S730,请参照图8C,在隔离层13远离衬底11的一侧形成与隔离层13欧姆接触的源极14和漏极15。Step S730 , referring to FIG. 8C , the source electrode 14 and the drain electrode 15 , which are in ohmic contact with the isolation layer 13 , are formed on the side of the isolation layer 13 away from the substrate 11 .

步骤S740,在隔离层13远离半导体层12的一侧制作栅极16和至少一个接地或经过接地处理的接地浮栅17。Step S740 , forming a gate 16 and at least one grounded or grounded floating gate 17 on the side of the isolation layer 13 away from the semiconductor layer 12 .

在本实施例中,栅极16和接地浮栅17为叠层结构,步骤S740可以包括:In this embodiment, the gate 16 and the grounded floating gate 17 are stacked structures, and step S740 may include:

首先,请参照图8D,在隔离层13上的源极14与漏极15之间的区域沉积一第二介质层20。First, referring to FIG. 8D , a second dielectric layer 20 is deposited on the isolation layer 13 in the region between the source electrode 14 and the drain electrode 15 .

接着,请参照图8E,在第二介质层20远离隔离层13的一侧上形成栅极导体161和至少一个浮栅导体171。Next, referring to FIG. 8E , a gate conductor 161 and at least one floating gate conductor 171 are formed on the side of the second dielectric layer 20 away from the isolation layer 13 .

再接着,请参照图8F,将栅极导体161和至少一个浮栅导体171作为掩模,蚀刻第二介质层20,形成由栅极导体161与第二介质层20形成的栅极16和由浮栅导体171与第二介质层形成的浮栅。Next, referring to FIG. 8F , using the gate conductor 161 and at least one floating gate conductor 171 as masks, the second dielectric layer 20 is etched to form the gate 16 formed by the gate conductor 161 and the second dielectric layer 20 and the gate 16 formed by the gate conductor 161 and the second dielectric layer 20 The floating gate formed by the floating gate conductor 171 and the second dielectric layer.

在蚀刻第二介质层20之后,在所述第二介质层20被蚀刻掉的区域上沉积第三介质层30,使所述第三介质层30包裹或覆盖所述栅极16与至少一个浮栅。After the second dielectric layer 20 is etched, a third dielectric layer 30 is deposited on the etched area of the second dielectric layer 20, so that the third dielectric layer 30 wraps or covers the gate 16 and at least one floating grid.

将浮栅直接接地或对浮栅做接地处理,得到接地浮栅17。The floating gate is directly grounded or grounded to obtain a grounded floating gate 17 .

在本实施例中,在步骤S740之后,所述方法还包括:In this embodiment, after step S740, the method further includes:

请参照图8G,在所述第二介质层20被蚀刻掉的区域上沉积第三介质层21,使所述第三介质层21包裹或覆盖所述栅极与至少一个所述接地浮栅。Referring to FIG. 8G , a third dielectric layer 21 is deposited on the area where the second dielectric layer 20 is etched away, so that the third dielectric layer 21 wraps or covers the gate and at least one of the grounded floating gates.

本申请实施例提供的半导体器件及其制造方法。所述半导体器件包括:衬底;设置于所述衬底上的半导体层;设置于所述半导体层远离所述衬底一侧的隔离层;设置于隔离层上的源极和漏极,所述源极和漏极与所述隔离层欧姆接触;以及设置在所述隔离层上的栅极和至少一个接地或经过接地处理的接地浮栅。通过在源极与漏极之间设置至少一个接地或经过接地处理的接地浮栅,避免浮栅中的漏电流对浮栅产生的电场尖峰峰值的影响,从而使基于电场尖峰的电场积分增大,提高半导体器件的工作电压,从而提高半导体器件的整体可靠性。The semiconductor device and the manufacturing method thereof provided by the embodiments of the present application. The semiconductor device comprises: a substrate; a semiconductor layer disposed on the substrate; an isolation layer disposed on the side of the semiconductor layer away from the substrate; source and drain electrodes disposed on the isolation layer, the the source electrode and the drain electrode are in ohmic contact with the isolation layer; and a gate electrode and at least one grounded or grounded floating gate disposed on the isolation layer. By arranging at least one grounded or grounded floating gate between the source and the drain, the effect of the leakage current in the floating gate on the peak value of the electric field generated by the floating gate is avoided, thereby increasing the electric field integral based on the electric field peak , improve the working voltage of the semiconductor device, thereby improving the overall reliability of the semiconductor device.

以上所述仅为本申请的优选实施例而已,并不用于限制本申请,对于本领域的技术人员来说,本申请可以有各种更改和变化。凡在本申请的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本申请的保护范围之内。The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims (11)

1. A semiconductor device, characterized in that the semiconductor device comprises:
a substrate;
a semiconductor layer disposed on the substrate;
the isolation layer is arranged on one side, away from the substrate, of the semiconductor layer;
a source electrode and a drain electrode disposed on the isolation layer, the source electrode and the drain electrode being in ohmic contact with the isolation layer; and
a gate electrode disposed on the isolation layer and at least one grounded or grounded floating gate electrode.
2. The semiconductor device according to claim 1, wherein the number of the grounded floating gates is plural, and a plurality of the grounded floating gates are provided separately from each other.
3. The semiconductor device according to claim 1, further comprising a first dielectric layer disposed on a side of the isolation layer away from the substrate, wherein the grounded floating gate has a stripe shape, and a plurality of the grounded floating gates are disposed on the first dielectric layer at intervals.
4. The semiconductor device of any of claims 1-3, wherein the grounded floating gate comprises a second dielectric layer disposed on the isolation layer and a floating gate conductor disposed on the second dielectric layer.
5. The semiconductor device of claim 4, wherein the grounded floating gate is a Schottky grounded floating gate or an insulated grounded floating gate.
6. The semiconductor device of claim 5, further comprising a negatively charged gate floating gate disposed between the gate and the isolation layer with an insulating medium disposed therebetween.
7. The semiconductor device of claim 6, wherein the metal portions of the insulated grounded floating gate and the gate floating gate are made of the same metal material.
8. The semiconductor device of claim 6, wherein the gate and the grounded floating gate are stacked, and a third dielectric layer is disposed on the isolation layer and wraps or covers the gate and at least one grounded floating gate.
9. A method of manufacturing a semiconductor device, the method comprising:
forming a semiconductor layer based on a substrate;
forming an isolation layer on one side of the semiconductor layer far away from the substrate;
manufacturing and forming a source electrode and a drain electrode which are in ohmic contact with the isolation layer on one side of the isolation layer away from the substrate;
and manufacturing a grid electrode and at least one grounded floating gate which is grounded or subjected to grounding treatment on one side of the isolation layer far away from the semiconductor layer.
10. The method of manufacturing a semiconductor device according to claim 9, wherein the gate electrode and the grounded floating gate are stacked, and the gate electrode and the at least one grounded or grounded floating gate are formed on a side of the isolation layer away from the semiconductor layer, and the method comprises:
depositing a second dielectric layer in the area between the source electrode and the drain electrode on the isolation layer;
forming a gate conductor and at least one floating gate conductor on a side of the second dielectric layer away from the isolation layer;
forming a gate formed of the gate conductor and the second dielectric layer and a floating gate formed of the floating gate conductor and the second dielectric layer;
and grounding or grounding the floating gate to obtain a grounded floating gate.
11. The method of manufacturing a semiconductor device according to claim 10, wherein after the gate electrode and the at least one grounded or grounded floating gate electrode are formed on a side of the isolation layer away from the semiconductor layer, the method further comprises:
and depositing a third dielectric layer on the etched region of the second dielectric layer, so that the third dielectric layer wraps or covers the grid and the at least one grounded floating gate.
CN201810731422.4A 2018-07-05 2018-07-05 Semiconductor device and manufacturing method Active CN110690281B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810731422.4A CN110690281B (en) 2018-07-05 2018-07-05 Semiconductor device and manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810731422.4A CN110690281B (en) 2018-07-05 2018-07-05 Semiconductor device and manufacturing method

Publications (2)

Publication Number Publication Date
CN110690281A true CN110690281A (en) 2020-01-14
CN110690281B CN110690281B (en) 2023-08-08

Family

ID=69106794

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810731422.4A Active CN110690281B (en) 2018-07-05 2018-07-05 Semiconductor device and manufacturing method

Country Status (1)

Country Link
CN (1) CN110690281B (en)

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100770132B1 (en) * 2006-10-30 2007-10-24 페어차일드코리아반도체 주식회사 Nitride-based semiconductor device
US20080135880A1 (en) * 2006-11-17 2008-06-12 The Furukawa Electric Co., Ltd. Nitride semiconductor heterojunction field effect transistor
CN101320751A (en) * 2007-06-06 2008-12-10 西安能讯微电子有限公司 HEMT device and its manufacturing method
JP2010278333A (en) * 2009-05-29 2010-12-09 Furukawa Electric Co Ltd:The Semiconductor device and method of manufacturing the same
CN103000673A (en) * 2011-09-09 2013-03-27 瑞萨电子株式会社 Semiconductor device and method of manufacturing the same
US20130193487A1 (en) * 2010-08-02 2013-08-01 Seles Es S.P.A. High electron mobility transistors with field plate electrode
CN103765565A (en) * 2011-08-22 2014-04-30 瑞萨电子株式会社 Semiconductor device
CN104916678A (en) * 2014-03-14 2015-09-16 株式会社东芝 Semiconductor device
CN104993825A (en) * 2015-07-01 2015-10-21 东南大学 Gallium arsenide-based low-leakage-current double-cantilever-beam-switch double-gate frequency divider
JP2015211104A (en) * 2014-04-25 2015-11-24 株式会社デンソー Semiconductor device and electronic circuit using the same
US20150340483A1 (en) * 2014-05-21 2015-11-26 International Rectifier Corporation Group III-V Device Including a Shield Plate
CN105355659A (en) * 2015-11-06 2016-02-24 西安电子科技大学 Trench-gate AlGaN/GaN HEMT device structure and manufacturing method
CN106158954A (en) * 2016-09-26 2016-11-23 南方科技大学 High electron mobility transistor and preparation method thereof
CN106158952A (en) * 2016-09-26 2016-11-23 南方科技大学 High electron mobility transistor and preparation method thereof
WO2018054377A1 (en) * 2016-09-26 2018-03-29 南方科技大学 High-electron-mobility transistor and preparation method therefor

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100770132B1 (en) * 2006-10-30 2007-10-24 페어차일드코리아반도체 주식회사 Nitride-based semiconductor device
US20080135880A1 (en) * 2006-11-17 2008-06-12 The Furukawa Electric Co., Ltd. Nitride semiconductor heterojunction field effect transistor
CN101320751A (en) * 2007-06-06 2008-12-10 西安能讯微电子有限公司 HEMT device and its manufacturing method
JP2010278333A (en) * 2009-05-29 2010-12-09 Furukawa Electric Co Ltd:The Semiconductor device and method of manufacturing the same
US20130193487A1 (en) * 2010-08-02 2013-08-01 Seles Es S.P.A. High electron mobility transistors with field plate electrode
CN103765565A (en) * 2011-08-22 2014-04-30 瑞萨电子株式会社 Semiconductor device
CN103000673A (en) * 2011-09-09 2013-03-27 瑞萨电子株式会社 Semiconductor device and method of manufacturing the same
CN104916678A (en) * 2014-03-14 2015-09-16 株式会社东芝 Semiconductor device
JP2015211104A (en) * 2014-04-25 2015-11-24 株式会社デンソー Semiconductor device and electronic circuit using the same
US20150340483A1 (en) * 2014-05-21 2015-11-26 International Rectifier Corporation Group III-V Device Including a Shield Plate
CN104993825A (en) * 2015-07-01 2015-10-21 东南大学 Gallium arsenide-based low-leakage-current double-cantilever-beam-switch double-gate frequency divider
CN105355659A (en) * 2015-11-06 2016-02-24 西安电子科技大学 Trench-gate AlGaN/GaN HEMT device structure and manufacturing method
CN106158954A (en) * 2016-09-26 2016-11-23 南方科技大学 High electron mobility transistor and preparation method thereof
CN106158952A (en) * 2016-09-26 2016-11-23 南方科技大学 High electron mobility transistor and preparation method thereof
WO2018054377A1 (en) * 2016-09-26 2018-03-29 南方科技大学 High-electron-mobility transistor and preparation method therefor

Also Published As

Publication number Publication date
CN110690281B (en) 2023-08-08

Similar Documents

Publication Publication Date Title
US11721753B2 (en) Method of fabricating a transistor
US9496353B2 (en) Fabrication of single or multiple gate field plates
CN103367403B (en) Semiconductor devices and its manufacturing method
US7253486B2 (en) Field plate transistor with reduced field plate resistance
US10461161B1 (en) GaN device with floating field plates
CN110649096B (en) High-voltage n-channel HEMT device
JP5558196B2 (en) HFET
CN103887334B (en) GaN high electron mobility transistor and GaN diode
JP2016511544A (en) Electrode of semiconductor device and manufacturing method thereof
JP2014508413A (en) Semiconductor device having low conductivity electric field control element
CN112242444A (en) High electron mobility transistor and manufacturing method thereof
CN110391297A (en) Gallium Nitride Transistor with Improved Termination Structure
CN115274825A (en) A kind of semiconductor device and preparation method thereof
CN116072724A (en) Semiconductor power device and preparation method thereof
CN110718585A (en) LDMOS device and method of making the same
US11862680B2 (en) Electrostatic discharge protection structure, nitride-based device having the same and method for manufacturing nitride-based device
CN110634948A (en) LDMOS device and method of forming the same
CN102315248A (en) Semiconductor device and the method for making semiconductor device
WO2018177426A1 (en) Semiconductor device and method for manufacturing same
CN110690281B (en) Semiconductor device and manufacturing method
US20230080636A1 (en) Device structure for power semiconductor transistor
TWI538208B (en) Ion implanted and self aligned gate structure for gan transistors
CN113394284A (en) High-voltage MIS-HEMT device with composite layer structure
CN112805837A (en) Grid-controlled diode and chip
KR102686096B1 (en) GaN RF HEMT Structure and fabrication method of the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant