CN110690281A - Semiconductor device and manufacturing method - Google Patents

Abstract

The semiconductor device and the manufacturing method provided by the embodiments of the present application. The semiconductor device comprises: a substrate; a semiconductor layer disposed on the substrate; an isolation layer disposed on the side of the semiconductor layer away from the substrate; source and drain electrodes disposed on the isolation layer, the the source electrode and the drain electrode are in ohmic contact with the isolation layer; and a gate electrode and at least one grounded or grounded floating gate disposed on the isolation layer. By arranging at least one grounded or grounded floating gate between the source and the drain, the effect of the leakage current in the floating gate on the peak value of the electric field generated by the floating gate is avoided, thereby increasing the electric field integral based on the electric field peak , improve the working voltage of the semiconductor device, thereby improving the overall reliability of the semiconductor device.

Description

Semiconductor device and manufacturing method

technical field

The present application relates to the technical field of semiconductors and semiconductor manufacturing, and in particular, to a semiconductor device and a manufacturing method.

Background technique

Planar channel field effect transistors in High Electron Mobility Transistor (HEMT), such as Gallium Nitride High Electron Mobility Transistor (GaNHEMT) and Gallium Arsenide High Electron Mobility Transistor (GaAs HEMT) and other devices. Including the source (Source, S), gate (Gate, G) and drain (Drain, D), the electric field will gather at the edge of the gate close to the drain, forming an electric field peak. When the voltage applied between the gate and the drain is gradually increased and the electric field at the peak value of this electric field is higher than the critical electric field of the semiconductor material, the device will break down and fail. At the same time, since the breakdown voltage (stressed) of the device is the integral of the electric field between the gate and the drain, compared with a uniformly distributed electric field, the sharper the peak value of the electric field at the gate edge of the device, the higher the breakdown voltage of the device. the lower the voltage.

In order to increase the operating voltage of the device, several commonly used methods for mitigating the electric field peak at the gate edge include: using a gate with a field plate structure, adding a floating gate between the gate and the drain, and so on. Switching devices often use the addition of a floating gate between the gate and drain to increase the operating voltage. As shown in Figure 1, after the floating gate is added, several electric field spikes are added between the gate and the drain, and the increased electric field spikes expand the electric field integral between the gate and the drain, increasing the breakdown of the device Voltage. If the floating gate is not used, the electric field will only form a peak at the edge of the gate, and the corresponding highest voltage that can be tolerated is the area of the gray triangle area shown in Figure 1, which is the integral of the electric field. However, in a device using a floating gate structure, due to the leakage current on the floating gate, the peak value of the electric field generated by the floating gate is smaller than the theoretical expectation, as shown in the electric field intensity distribution shown by the dotted line in Figure 1. The lower peak value of the electric field means that its integrated voltage is also smaller than the ideal calculation. In severe cases, as shown in Figure 1, several floating gates close to the drain can't improve the breakdown voltage of the device at all.

SUMMARY OF THE INVENTION

In view of this, the purpose of the present application is to provide a semiconductor device and a method for manufacturing the semiconductor device to solve the above problems.

In a first aspect, embodiments of the present application provide a semiconductor device, the semiconductor device comprising:

substrate;

a semiconductor layer disposed on the substrate;

an isolation layer disposed on the side of the semiconductor layer away from the substrate;

a source electrode and a drain electrode disposed on the isolation layer, the source electrode and the drain electrode being in ohmic contact with the isolation layer; and

A gate disposed on the isolation layer and at least one grounded or grounded floating gate.

Optionally, in this embodiment, the number of the grounded floating gates is multiple, and the multiple grounded floating gates are provided separately from each other.

Optionally, in this embodiment, the semiconductor device further includes a first dielectric layer disposed on a side of the isolation layer away from the substrate, the grounded floating gate is strip-shaped, and a plurality of the grounded floating gates Spacers are provided on the first dielectric layer.

Optionally, in this embodiment, the grounded floating gate includes a second dielectric layer disposed on the isolation layer and a floating gate conductor located on the second dielectric layer.

Optionally, in this embodiment, the grounded floating gate is a Schottky grounded floating gate or an insulated grounded floating gate.

Optionally, in this embodiment, the semiconductor device further includes a negatively charged gate floating gate disposed between the gate and the isolation layer, the gate floating gate and the gate An insulating medium is provided between them.

Optionally, in this embodiment, the insulating grounded floating gate and the metal part of the gate floating gate are made of the same metal material.

Optionally, in this embodiment, the gate and the grounded floating gate are in a stacked structure, a third dielectric layer is disposed on the isolation layer, and the third dielectric layer wraps or covers the gate with at least one of the grounded floating gates.

In a second aspect, embodiments of the present application further provide a method for manufacturing the semiconductor device in the first aspect, the method comprising:

Forming a semiconductor layer based on a substrate;

Forming an isolation layer on the side of the semiconductor layer away from the substrate;

Fabricating a source electrode and a drain electrode forming ohmic contact with the isolation layer on the side of the isolation layer away from the substrate;

A gate and at least one grounded or grounded floating gate are fabricated on a side of the isolation layer away from the semiconductor layer.

Optionally, in this embodiment, forming a gate and at least one grounded or grounded floating gate on a side of the isolation layer away from the semiconductor layer, including:

depositing a second dielectric layer on the isolation layer in the region between the source electrode and the drain electrode;

forming a gate conductor and at least one floating gate conductor on a side of the second dielectric layer away from the isolation layer;

forming a gate formed by the gate conductor and the second dielectric layer and a floating gate formed by the floating gate conductor and the second dielectric layer;

The floating gate is grounded or grounded to obtain a grounded floating gate.

Optionally, in this embodiment, after forming a gate and at least one grounded or grounded floating gate on the side of the isolation layer away from the semiconductor layer, the method further includes:

A third dielectric layer is deposited on the area where the second dielectric layer is etched away, so that the third dielectric layer wraps or covers the stacked gate and at least one of the stacked grounded floating gates.

The semiconductor device and the manufacturing method thereof provided by the embodiments of the present application. The semiconductor device comprises: a substrate; a semiconductor layer disposed on the substrate; an isolation layer disposed on the side of the semiconductor layer away from the substrate; source and drain electrodes disposed on the isolation layer, the the source electrode and the drain electrode are in ohmic contact with the isolation layer; and a gate electrode and at least one grounded or grounded floating gate disposed on the isolation layer. By arranging at least one grounded or grounded floating gate between the source and the drain, the effect of the leakage current in the floating gate on the peak value of the electric field generated by the floating gate is avoided, thereby increasing the electric field integral based on the electric field peak , improve the working voltage of the semiconductor device, thereby improving the overall reliability of the semiconductor device.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application more clearly, the accompanying drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation of the scope. Other related figures are obtained from these figures.

1 is a schematic diagram of the corresponding relationship between floating gate design and electric field strength in the prior art;

2 to 6 are schematic diagrams of various modified structures of the semiconductor device provided by the embodiments of the present application;

FIG. 7 is a process flow diagram of a semiconductor device provided by an embodiment of the present application;

8A-8G are process diagrams of the semiconductor device provided by the present embodiment.

Icon: 10-semiconductor device; 11-substrate; 12-semiconductor layer; 13-isolation layer; 14-source; 15-drain; 16-gate; 161-gate conductor; 17-grounded floating gate; 171 - floating gate conductor; 18 - gate floating gate; 19 - first dielectric layer; 20 - second dielectric layer; 21 - third dielectric layer.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

Thus, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the application as claimed, but is merely representative of selected embodiments of the application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, or is usually placed when the product of the invention is used. The orientation or positional relationship is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first", "second", etc. are only used to differentiate the description and should not be construed to indicate or imply relative importance.

Please refer to FIG. 2 , which shows a schematic structural diagram of a semiconductor device 10 provided by an embodiment of the present application. The semiconductor device 10 includes a substrate 11 , a semiconductor layer 12 , an isolation layer 13 , a source electrode 14 , a drain electrode 15 , a gate electrode 16 and a grounded floating gate 17 .

The semiconductor layer 12 is formed on the upper surface of the substrate 11 , and the isolation layer 13 is provided on the side of the semiconductor layer 12 away from the substrate 11 . The source electrode 14 and the drain electrode 15 are disposed on the side of the isolation layer 13 away from the substrate 11 , and the source electrode 14 and the drain electrode 15 are in ohmic contact with the isolation layer 13 . The gate 16 and at least one grounded or grounded floating gate 17 are disposed on the side of the isolation layer 13 away from the substrate 11 .

In this embodiment, the difference between the grounded floating gate 17 and the common floating gate is that the grounded floating gate 17 is grounded or directly grounded, and the leakage current in the grounded floating gate 17 is much smaller than that in the common floating gate. Therefore, the peak value of the electric field generated by the grounded floating gate 17 is larger, the electric field integral based on the electric field peak is larger, and the working voltage of the semiconductor device 10 is improved.

Referring to FIG. 2 again, in this embodiment, the semiconductor layer 12 is made of GaN material, and the isolation layer is made of AlGaN material. Since the semiconductor layer 12 and the isolation layer have different band gaps, the semiconductor device 10 further includes a two-dimensional electron gas layer 2DEG located at the interface between the semiconductor layer 12 and the isolation layer.

Next, the possible implementations of this embodiment will be introduced. It can be understood that the following descriptions are only possible implementations of the semiconductor device 10 in this application, and should not be construed as a limitation of this application. In other embodiments of this application In addition to the following implementation manners, other implementation manners may also be adopted.

Referring to FIG. 2 again, in the first implementation manner of this embodiment, the grounded floating gate 17 is a Schottky floating gate, and the metal of the grounded floating gate 17 is in Schottky contact with the isolation layer 13 . In this case, before the semiconductor device 10 leaves the factory, part or all of the grounded floating gate needs to be grounded. Specifically, the metal part of the grounded floating gate 17 can be connected to the ground through a metal wire to remove the grounded floating gate The free charge on 17, after which the metal wire is removed, the grounded floating gate 17 is not electrically connected to the outside world, the grounded floating gate 17 is floating in potential, and the grounded floating gate 17 is isolated from each electrode of the device and has no electrical connection. When there are multiple grounded floating gates 17 , each of the grounded floating gates 17 is separated from each other. Under this arrangement, the leakage current of the grounded floating gate 17 is smaller than that of the common floating gate, which can improve the breakdown voltage of the semiconductor device 10 .

Referring to FIG. 2 again, in the second implementation of this embodiment, all or part of the grounded floating gate 17 is directly grounded, and the grounded floating gates are independent of each other and are not physically connected to each other. The grounded floating gate 17 is connected to the semiconductor device. There is also no physical connection between the various electrodes of 10. The grounded floating gate 17 can increase the electric field peak on the gate 16 and greatly increase the breakdown voltage of the semiconductor device 10 .

Please refer to FIG. 3 . FIG. 3 shows a situation in which the semiconductor device 10 is an enhancement type switching device. In the third implementation manner of this embodiment, the semiconductor device 10 includes a gate electrode disposed between the gate electrode 16 and the isolation layer 13 . The floating gate 18, wherein the gate floating gate 18 has a negative charge on it. An insulating medium is provided between the gate floating gate 18 and the gate 16 . In this embodiment, the gate floating gate 18 may be precharged before shipment.

In the third embodiment, the material of the above-mentioned gate floating gate 18 may be a semi-insulating material, which may include oxygen-rich polysilicon or silicon-rich silicon nitride. The gate floating gate 18 using the above-mentioned materials has the ability to store electrons stably, the gate floating gate 18 using the above-mentioned materials can be insulated at normal temperature, the sheet resistivity is above 100G ohms, and it can conduct electricity under certain conditions, and the sheet resistance rate below 100M ohms. The gate floating gate 18 is precharged before the semiconductor device 10 leaves the factory. During the precharging, the gate floating gate 18 conducts electricity, so that electrons are stored in the gate floating gate 18 . Thereafter, the gate floating gate 18 of the semiconductor device 10 is insulated during operation, so that electrons are stored therein without leakage, and the semiconductor threshold shift caused by the leakage of the gate floating gate 18 is prevented. In addition, the material of the above-mentioned gate floating gate 18 may also be a conductor material.

Specifically, the material of the gate floating gate 18 is oxygen-rich polysilicon. When the gate floating gate 18 is precharged (calibrated) before the semiconductor device 10 leaves the factory, the gate floating gate 18 is heated to 200 degrees Celsius to make the gate floating The material of the gate 18 is changed from an insulating material to a conductive material, and the gate floating gate 18 accumulates enough and uniformly distributed electrons by means of capacitive charging, which reduces the potential of the gate floating gate 18 and enables the semiconductor device 10 to be positively turned on. voltage, resulting in an enhancement-mode switching device. After the gate floating gate 18 writes electrons, the temperature is lowered to room temperature, so that the material of the gate floating gate 18 is restored to its insulating properties, and the electrons written into the gate floating gate 18 are frozen in the gate floating gate 18, so as to activate the gate floating gate 18. to the initial threshold of the enhancement-mode switching device.

In the third embodiment, the use of the grounded floating gate 17 and the gated floating gate 18 at the same time can greatly improve the breakdown voltage of the switching device.

Referring to FIG. 4 , in a fourth implementation of this embodiment, a situation is provided in which the grounded floating gate 17 is an insulated grounded floating gate, wherein the insulated grounded floating gate is the grounded floating gate 17 described in the above-mentioned implementation manner. In addition, an insulating medium is added where the grounded floating gate 17 is in contact with the isolation layer 13 , so that the leakage current in the grounded floating gate 17 can be reduced and the breakdown voltage of the semiconductor device 10 can be improved.

Referring to FIG. 5 , in the fifth implementation of this embodiment, different types of grounded floating gates 17 can be used on the same semiconductor device 10 , for example, the semiconductor device 10 can be simultaneously used with insulated grounded floating gates and Schotts. Base ground floating gate. Specifically, the insulated grounded floating gate can be arranged near the gate, which can reduce the leakage current of the grounded floating gate and improve the breakdown voltage of the semiconductor device.

Referring to FIG. 6 , in a sixth implementation manner of the present embodiment, the grounded floating gate 17 may be in a strip shape. In this implementation manner, the semiconductor device 10 further includes a spacer disposed on the isolation layer 13 away from the substrate 11 . On the first dielectric layer 19 on the side, a plurality of strip-shaped grounded floating gates 17 are provided on the first dielectric layer 19, and the strip-shaped grounded floating gates 17 are isolated from each other. In this embodiment, even if a single strip-shaped grounded floating gate 17 leaks, it will not affect the leakage of the overall grounded floating gate 17, and the leakage of the overall grounded floating gate 17 is still small, which can improve the breakdown voltage of the semiconductor device 10 and reliability.

In this embodiment, the grounded floating gate has a double-layer structure. Referring to FIG. 8E , the grounded floating gate 17 includes a second dielectric layer 20 disposed on the isolation layer 13 and a floating gate conductor 171 located on the second dielectric layer 20 . .

Further, in this embodiment, the insulating grounded floating gate and the metal portion of the gate floating gate 18 are made of the same metal material.

In the semiconductor device 10 disclosed in the above embodiments, at least one grounded or grounded floating gate 17 is arranged between the source 14 and the drain 15 to avoid the influence of the leakage current in the floating gate on the peak value of the electric field generated by the floating gate. , thereby increasing the electric field integral based on the electric field peak, improving the operating voltage and overall reliability of the semiconductor device 10 .

Referring to FIG. 8G , in this embodiment, the gate 16 and the grounded floating gate 17 are in a stacked structure, and a third dielectric layer 21 is disposed on the isolation layer 13 , and the third dielectric layer 21 wraps or covers the gate 16 and the grounded floating gate 17 . At least one grounded floating gate 17 .

Referring to FIG. 7 , an embodiment of the present application further provides a method for manufacturing a semiconductor device 10 , which is used for manufacturing the semiconductor device 10 described in the above embodiment, and the method includes the following specific steps:

In step S710 , referring to FIG. 8A , the semiconductor layer 12 is formed based on a substrate 11 .

In step S720 , referring to FIG. 8B , an isolation layer 13 is formed on the side of the semiconductor layer 12 away from the substrate 11 .

Step S730 , referring to FIG. 8C , the source electrode 14 and the drain electrode 15 , which are in ohmic contact with the isolation layer 13 , are formed on the side of the isolation layer 13 away from the substrate 11 .

Step S740 , forming a gate 16 and at least one grounded or grounded floating gate 17 on the side of the isolation layer 13 away from the semiconductor layer 12 .

In this embodiment, the gate 16 and the grounded floating gate 17 are stacked structures, and step S740 may include:

First, referring to FIG. 8D , a second dielectric layer 20 is deposited on the isolation layer 13 in the region between the source electrode 14 and the drain electrode 15 .

Next, referring to FIG. 8E , a gate conductor 161 and at least one floating gate conductor 171 are formed on the side of the second dielectric layer 20 away from the isolation layer 13 .

Next, referring to FIG. 8F , using the gate conductor 161 and at least one floating gate conductor 171 as masks, the second dielectric layer 20 is etched to form the gate 16 formed by the gate conductor 161 and the second dielectric layer 20 and the gate 16 formed by the gate conductor 161 and the second dielectric layer 20 The floating gate formed by the floating gate conductor 171 and the second dielectric layer.

After the second dielectric layer 20 is etched, a third dielectric layer 30 is deposited on the etched area of the second dielectric layer 20, so that the third dielectric layer 30 wraps or covers the gate 16 and at least one floating grid.

The floating gate is directly grounded or grounded to obtain a grounded floating gate 17 .

In this embodiment, after step S740, the method further includes:

Referring to FIG. 8G , a third dielectric layer 21 is deposited on the area where the second dielectric layer 20 is etched away, so that the third dielectric layer 21 wraps or covers the gate and at least one of the grounded floating gates.

The semiconductor device and the manufacturing method thereof provided by the embodiments of the present application. The semiconductor device comprises: a substrate; a semiconductor layer disposed on the substrate; an isolation layer disposed on the side of the semiconductor layer away from the substrate; source and drain electrodes disposed on the isolation layer, the the source electrode and the drain electrode are in ohmic contact with the isolation layer; and a gate electrode and at least one grounded or grounded floating gate disposed on the isolation layer. By arranging at least one grounded or grounded floating gate between the source and the drain, the effect of the leakage current in the floating gate on the peak value of the electric field generated by the floating gate is avoided, thereby increasing the electric field integral based on the electric field peak , improve the working voltage of the semiconductor device, thereby improving the overall reliability of the semiconductor device.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims (11)

1. A semiconductor device, characterized in that the semiconductor device comprises:

a substrate;

a semiconductor layer disposed on the substrate;

the isolation layer is arranged on one side, away from the substrate, of the semiconductor layer;

a source electrode and a drain electrode disposed on the isolation layer, the source electrode and the drain electrode being in ohmic contact with the isolation layer; and

a gate electrode disposed on the isolation layer and at least one grounded or grounded floating gate electrode.

2. The semiconductor device according to claim 1, wherein the number of the grounded floating gates is plural, and a plurality of the grounded floating gates are provided separately from each other.

3. The semiconductor device according to claim 1, further comprising a first dielectric layer disposed on a side of the isolation layer away from the substrate, wherein the grounded floating gate has a stripe shape, and a plurality of the grounded floating gates are disposed on the first dielectric layer at intervals.

4. The semiconductor device of any of claims 1-3, wherein the grounded floating gate comprises a second dielectric layer disposed on the isolation layer and a floating gate conductor disposed on the second dielectric layer.

5. The semiconductor device of claim 4, wherein the grounded floating gate is a Schottky grounded floating gate or an insulated grounded floating gate.

6. The semiconductor device of claim 5, further comprising a negatively charged gate floating gate disposed between the gate and the isolation layer with an insulating medium disposed therebetween.

7. The semiconductor device of claim 6, wherein the metal portions of the insulated grounded floating gate and the gate floating gate are made of the same metal material.

8. The semiconductor device of claim 6, wherein the gate and the grounded floating gate are stacked, and a third dielectric layer is disposed on the isolation layer and wraps or covers the gate and at least one grounded floating gate.

9. A method of manufacturing a semiconductor device, the method comprising:

forming a semiconductor layer based on a substrate;

forming an isolation layer on one side of the semiconductor layer far away from the substrate;

manufacturing and forming a source electrode and a drain electrode which are in ohmic contact with the isolation layer on one side of the isolation layer away from the substrate;

and manufacturing a grid electrode and at least one grounded floating gate which is grounded or subjected to grounding treatment on one side of the isolation layer far away from the semiconductor layer.

10. The method of manufacturing a semiconductor device according to claim 9, wherein the gate electrode and the grounded floating gate are stacked, and the gate electrode and the at least one grounded or grounded floating gate are formed on a side of the isolation layer away from the semiconductor layer, and the method comprises:

depositing a second dielectric layer in the area between the source electrode and the drain electrode on the isolation layer;

forming a gate conductor and at least one floating gate conductor on a side of the second dielectric layer away from the isolation layer;

forming a gate formed of the gate conductor and the second dielectric layer and a floating gate formed of the floating gate conductor and the second dielectric layer;

and grounding or grounding the floating gate to obtain a grounded floating gate.

11. The method of manufacturing a semiconductor device according to claim 10, wherein after the gate electrode and the at least one grounded or grounded floating gate electrode are formed on a side of the isolation layer away from the semiconductor layer, the method further comprises:

and depositing a third dielectric layer on the etched region of the second dielectric layer, so that the third dielectric layer wraps or covers the grid and the at least one grounded floating gate.

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