CN110690281A - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
- Publication number
- CN110690281A CN110690281A CN201810731422.4A CN201810731422A CN110690281A CN 110690281 A CN110690281 A CN 110690281A CN 201810731422 A CN201810731422 A CN 201810731422A CN 110690281 A CN110690281 A CN 110690281A
- Authority
- CN
- China
- Prior art keywords
- floating gate
- grounded
- gate
- semiconductor device
- isolation layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000002955 isolation Methods 0.000 claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000004020 conductor Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 239000007769 metal material Substances 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 34
- 239000000463 material Substances 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The embodiment of the application provides a semiconductor device and a manufacturing method. The semiconductor device includes: a substrate; a semiconductor layer disposed on the substrate; the isolation layer is arranged on one side, away from the substrate, of the semiconductor layer; a source electrode and a drain electrode disposed on the isolation layer, the source electrode and the drain electrode being in ohmic contact with the isolation layer; and a gate electrode and at least one grounded floating gate disposed on the isolation layer and grounded or grounded. The influence of leakage current in the floating gate on an electric field peak value generated by the floating gate is avoided by arranging at least one grounded floating gate or grounded floating gate between the source electrode and the drain electrode, so that electric field integral based on the electric field peak is increased, the working voltage of the semiconductor device is improved, and the overall reliability of the semiconductor device is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor and semiconductor manufacturing technologies, and in particular, to a semiconductor device and a manufacturing method thereof.
Background
In a planar channel field effect Transistor (HEMT) in a High Electron Mobility Transistor (HEMT), such as a gallium nitride High Electron Mobility Transistor (gan HEMT) and a gallium arsenide High Electron Mobility Transistor (GaAs HEMT), which includes a Source (Source, S), a Gate (Gate, G) and a Drain (Drain, D), an electric field is concentrated at an edge of the Gate close to the Drain, forming an electric field spike. When the voltage applied between the gate and drain is increased in steps and the electric field at the peak of this electric field spike is caused to be higher than the critical electric field of the semiconductor material, the device breaks down and fails. Meanwhile, as the breakdown voltage (bearing) borne by the device is the integral of the electric field between the grid electrode and the drain electrode, compared with an evenly distributed electric field, the sharper the peak value of the electric field peak of the device at the edge of the grid electrode is, the smaller the breakdown voltage borne by the device is.
To increase the operating voltage of the device, several commonly used methods for mitigating electric field spikes at the edge of the gate include: a grid adopting a field plate structure, a floating gate added between the grid and a drain electrode and the like. Switching devices often use the addition of a floating gate between the gate and drain to increase the operating voltage. As shown in fig. 1, after the floating gate is added, several electric field spikes are added between the gate and the drain, and the added electric field spikes enlarge the electric field integral between the gate and the drain, raising the breakdown voltage of the device. If a floating gate is not used, the electric field will only form a peak at the edge of the gate, and the highest voltage that can be tolerated is the area of the gray triangular area shown in fig. 1, i.e., the integral of the electric field. However, in the device adopting the floating gate structure, the peak value of the electric field peak generated by the floating gate is smaller than the theoretical expectation due to the leakage current existing on the floating gate, and the electric field intensity distribution shown by the dotted line in fig. 1 is shown. A lower electric field peak means that the voltage resulting from its integration is also less than calculated in the ideal case. In severe cases, as shown in fig. 1, several floating gates near the drain may not function at all to increase the breakdown voltage of the device.
Disclosure of Invention
In view of the above, the present application aims to provide a semiconductor device and a method for manufacturing the semiconductor device to solve the above problems.
In a first aspect, an embodiment of the present application provides a semiconductor device, including:
a substrate;
a semiconductor layer disposed on the substrate;
the isolation layer is arranged on one side, away from the substrate, of the semiconductor layer;
a source electrode and a drain electrode disposed on the isolation layer, the source electrode and the drain electrode being in ohmic contact with the isolation layer; and
a gate electrode disposed on the isolation layer and at least one grounded or grounded floating gate electrode.
Optionally, in this embodiment, the number of the grounded floating gates is multiple, and the multiple grounded floating gates are separately arranged from each other.
Optionally, in this embodiment, the semiconductor device further includes a first dielectric layer disposed on a side of the isolation layer away from the substrate, the grounded floating gate is in a stripe shape, and a plurality of the grounded floating gates are disposed on the first dielectric layer at intervals.
Optionally, in this embodiment, the grounded floating gate includes a second dielectric layer disposed on the isolation layer and a floating gate conductor disposed on the second dielectric layer.
Optionally, in this embodiment, the grounded floating gate is a schottky grounded floating gate or an insulated grounded floating gate.
Optionally, in this embodiment, the semiconductor device further includes a negatively charged gate floating gate disposed between the gate and the isolation layer, and an insulating medium is disposed between the gate floating gate and the gate.
Optionally, in this embodiment, the metal portions of the insulated and grounded floating gate and the gate floating gate are made of the same metal material.
Optionally, in this embodiment, the gate and the grounded floating gate are of a stacked structure, and a third dielectric layer is disposed on the isolation layer, and wraps or covers the gate and the at least one grounded floating gate.
In a second aspect, embodiments of the present application further provide a manufacturing method for manufacturing the semiconductor device in the first aspect, the method including:
forming a semiconductor layer based on a substrate;
forming an isolation layer on one side of the semiconductor layer far away from the substrate;
manufacturing and forming a source electrode and a drain electrode which are in ohmic contact with the isolation layer on one side of the isolation layer away from the substrate;
and manufacturing a grid electrode and at least one grounded floating gate which is grounded or subjected to grounding treatment on one side of the isolation layer far away from the semiconductor layer.
Optionally, in this embodiment, the manufacturing a gate and at least one grounded or grounded floating gate on a side of the isolation layer away from the semiconductor layer includes:
depositing a second dielectric layer in the area between the source electrode and the drain electrode on the isolation layer;
forming a gate conductor and at least one floating gate conductor on a side of the second dielectric layer away from the isolation layer;
forming a gate formed of the gate conductor and the second dielectric layer and a floating gate formed of the floating gate conductor and the second dielectric layer;
and grounding or grounding the floating gate to obtain a grounded floating gate.
Optionally, in this embodiment, after the gate and the at least one grounded or grounded floating gate are fabricated on the side of the isolation layer away from the semiconductor layer, the method further includes:
and depositing a third dielectric layer on the etched region of the second dielectric layer, so that the third dielectric layer wraps or covers the laminated grid and at least one laminated grounding floating gate.
The embodiment of the application provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate; a semiconductor layer disposed on the substrate; the isolation layer is arranged on one side, away from the substrate, of the semiconductor layer; a source electrode and a drain electrode disposed on the isolation layer, the source electrode and the drain electrode being in ohmic contact with the isolation layer; and a gate electrode and at least one grounded floating gate disposed on the isolation layer and grounded or grounded. The influence of leakage current in the floating gate on an electric field peak value generated by the floating gate is avoided by arranging at least one grounded floating gate or grounded floating gate between the source electrode and the drain electrode, so that electric field integral based on the electric field peak is increased, the working voltage of the semiconductor device is improved, and the overall reliability of the semiconductor device is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below. It is appreciated that the following drawings depict only certain embodiments of the application and are therefore not to be considered limiting of its scope, for those skilled in the art will be able to derive additional related drawings therefrom without the benefit of the inventive faculty.
FIG. 1 is a diagram illustrating the correspondence between floating gate design and electric field strength in the prior art;
fig. 2 to fig. 6 are schematic structural diagrams of various modifications of the semiconductor device provided in the embodiments of the present application;
FIG. 7 is a flow chart illustrating a process of fabricating a semiconductor device according to an embodiment of the present disclosure;
fig. 8A to 8G are process diagrams of the semiconductor device according to the embodiment of the present disclosure.
Icon: 10-a semiconductor device; 11-a substrate; 12-a semiconductor layer; 13-an isolation layer; 14-a source electrode; 15-a drain electrode; 16-a gate; 161-gate conductor; 17-a grounded floating gate; 171-floating gate conductor; 18-gate floating gate; 19-a first dielectric layer; 20-a second dielectric layer; 21-third dielectric layer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the described embodiments are merely a few embodiments of the present application and not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "upper", "lower", and the like refer to orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the present invention are conventionally placed in use, and are used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a semiconductor device 10 according to an embodiment of the present disclosure. The semiconductor device 10 includes a substrate 11, a semiconductor layer 12, an isolation layer 13, a source 14, a drain 15, a gate 16, and a grounded floating gate 17.
A semiconductor layer 12 is formed on the upper surface of the substrate 11, and an isolation layer 13 is disposed on a side of the semiconductor layer 12 away from the substrate 11. The source electrode 14 and the drain electrode 15 are disposed on the side of the spacer layer 13 remote from the substrate 11, and the source electrode 14 and the drain electrode 15 are in ohmic contact with the spacer layer 13. A gate 16 and at least one grounded or grounded floating gate 17 are arranged on the side of the isolation layer 13 remote from the substrate 11.
In the present embodiment, the grounded floating gate 17 is different from the ordinary floating gate in that the grounded floating gate 17 is grounded or directly grounded, and the leakage current in the grounded floating gate 17 is much smaller than that in the ordinary floating gate. Thus, the peak value of the electric field peak generated by the grounded floating gate 17 is large, the electric field integral based on the electric field peak is large, and the operating voltage of the semiconductor device 10 is increased.
Referring to fig. 2 again, in the present embodiment, the semiconductor layer 12 is made of GaN material, and the isolation layer is made of AlGaN material. Since semiconductor layer 12 and the isolation layer have different band gaps, semiconductor device 10 further includes a two-dimensional electron gas layer 2DEG located at the interface of semiconductor layer 12 and the isolation layer.
Next, a possible implementation manner of the present embodiment is described, and it should be understood that the following description is only a possible implementation manner of the semiconductor device 10 in the present application, and should not be construed as a limitation to the present application, and other implementation manners besides the following implementation manners may also be adopted in other embodiments of the present application.
Referring to fig. 2 again, in the first embodiment of the present invention, the grounded floating gate 17 is a schottky floating gate, and the metal of the grounded floating gate 17 and the isolation layer 13 are schottky contacts. In this case, before the semiconductor device 10 is shipped, it is necessary to perform grounding treatment on part or all of the above-mentioned grounded floating gates, specifically, the metal part of the grounded floating gate 17 may be connected to ground through a metal wire to remove free charges on the grounded floating gate 17, and thereafter the metal wire is removed, the grounded floating gate 17 is not electrically connected to the outside, the grounded floating gate 17 is floating in potential, the grounded floating gate 17 is isolated from each other with respect to each electrode of the device without being electrically connected, and when there are a plurality of grounded floating gates 17, each grounded floating gate 17 is separated from each other. With this arrangement, the leakage current of the grounded floating gate 17 is smaller than that of a normal floating gate, and the breakdown voltage of the semiconductor device 10 can be increased.
Referring again to fig. 2, in the second embodiment of the present invention, all or part of the grounded floating gates 17 are directly grounded, the grounded floating gates are independent of each other and are not physically connected to each other, and the grounded floating gates 17 are not physically connected to the electrodes of the semiconductor device 10. Such a grounded floating gate 17 may increase the electric field spike on the gate 16, greatly increasing the breakdown voltage of the semiconductor device 10.
Referring to fig. 3, fig. 3 shows a case where the semiconductor device 10 is an enhancement-type switching device, and in a third embodiment of the present embodiment, the semiconductor device 10 includes a gate floating gate 18 disposed between the gate 16 and the isolation layer 13, wherein the gate floating gate 18 has negative charges thereon. An insulating dielectric is disposed between the gate floating gate 18 and the gate 16. In this embodiment, the gate floating gate 18 can be precharged before shipment.
In the third embodiment, the material of the gate floating gate 18 may be a semi-insulating material, and may include oxygen-rich polysilicon or silicon-rich silicon nitride. The gate floating gate 18 made of the material has a stable ability to store electrons, the gate floating gate 18 made of the material can be insulated at normal temperature, has a square resistivity of 100G ohm or more, can conduct electricity under a certain condition, and has a square resistivity of 100M ohm or less. The gate floating gate 18 is pre-charged before the semiconductor device 10 is shipped, and the gate floating gate 18 is conductive during pre-charging, causing electrons to be stored in the gate floating gate 18. Thereafter, the semiconductor device 10 insulates the gate floating gate 18 during operation, allowing electrons to be stored therein without leakage, preventing semiconductor threshold drift due to leakage of the gate floating gate 18. The material of the gate floating gate 18 may be a conductor material.
Specifically, the material of the gate floating gate 18 is oxygen-rich polysilicon, and when the gate floating gate 18 is pre-charged (calibrated) before the semiconductor device 10 leaves the factory, the gate floating gate 18 is heated to 200 ℃, so that the material of the gate floating gate 18 is converted from an insulating material into a conductive material, and the gate floating gate 18 accumulates enough and uniformly distributed electrons in a capacitance charging manner, so that the potential of the gate floating gate 18 is reduced, the semiconductor device 10 obtains a positive turn-on voltage, and the enhanced switching device is obtained. After the electrons are written into the floating gate 18, the temperature is reduced to room temperature, so that the material of the floating gate 18 of the gate recovers the insulating property, and the electrons written into the floating gate 18 of the gate are frozen in the floating gate 18 of the gate, thereby playing the role of the initial threshold of the enhancement type switching device.
In the third embodiment, the use of both the grounded floating gate 17 and the gate floating gate 18 can greatly improve the breakdown voltage of the switching device.
Referring to fig. 4, in a fourth embodiment of the present invention, a case is provided where the grounded floating gate 17 is an insulated grounded floating gate, wherein an insulating medium is added to the place where the grounded floating gate 17 contacts the isolation layer 13 on the basis of the grounded floating gate 17 described in the above embodiments, so that the leakage current in the grounded floating gate 17 can be reduced, and the breakdown voltage of the semiconductor device 10 can be increased.
Referring to fig. 5, in the fifth embodiment of the present invention, different types of grounded floating gates 17 can be used on the same semiconductor device 10, for example, both an insulated grounded floating gate and a schottky grounded floating gate can be used on the semiconductor device 10. Specifically, the insulated grounded floating gate can be arranged near the gate, so that the leakage current of the grounded floating gate can be reduced, and the breakdown voltage of the semiconductor device can be improved.
Referring to fig. 6, in a sixth implementation manner of this embodiment, the grounded floating gates 17 may be strip-shaped, in this implementation manner, the semiconductor device 10 further includes a first dielectric layer 19 disposed on a side of the isolation layer 13 away from the substrate 11, the plurality of strip-shaped grounded floating gates 17 are disposed on the first dielectric layer 19, and the strip-shaped grounded floating gates 17 are disposed in isolation from each other. In the present embodiment, even if a single stripe-shaped grounded floating gate 17 leaks, the leakage of the entire grounded floating gate 17 is not affected, and the leakage of the entire grounded floating gate 17 is small, so that the breakdown voltage and reliability of the semiconductor device 10 can be improved.
In the present embodiment, the floating gate is a double-layer structure, and referring to fig. 8E, the floating gate 17 includes a second dielectric layer 20 disposed on the isolation layer 13 and a floating gate conductor 171 disposed on the second dielectric layer 20.
Further, in the present embodiment, the metal portions of the insulated grounded floating gate and the gate floating gate 18 are made of the same metal material.
In the semiconductor device 10 disclosed in the above embodiment, at least one grounded floating gate 17 or grounded floating gate grounded is disposed between the source 14 and the drain 15, so as to avoid the influence of the leakage current in the floating gate on the peak value of the electric field spike generated by the floating gate, thereby increasing the electric field integral based on the electric field spike, and improving the operating voltage and overall reliability of the semiconductor device 10.
Referring to fig. 8G, in the present embodiment, the gate 16 and the floating gate 17 are stacked, and a third dielectric layer 21 is disposed on the isolation layer 13, wherein the third dielectric layer 21 wraps or covers the gate 16 and at least one floating gate 17.
Referring to fig. 7, the present embodiment further provides a method for manufacturing the semiconductor device 10, where the method is used to manufacture the semiconductor device 10 according to the above embodiment, and the method includes the following specific steps:
in step S710, referring to fig. 8A, a semiconductor layer 12 is formed on a substrate 11.
In step S720, referring to fig. 8B, an isolation layer 13 is formed on a side of the semiconductor layer 12 away from the substrate 11.
In step S730, referring to fig. 8C, a source electrode 14 and a drain electrode 15 are formed on the side of the isolation layer 13 away from the substrate 11, wherein the source electrode and the drain electrode are in ohmic contact with the isolation layer 13.
In step S740, a gate electrode 16 and at least one grounded or grounded floating gate 17 are formed on the side of the isolation layer 13 away from the semiconductor layer 12.
In this embodiment, the gate 16 and the grounded floating gate 17 are stacked, and the step S740 may include:
first, referring to fig. 8D, a second dielectric layer 20 is deposited on the isolation layer 13 in the region between the source 14 and the drain 15.
Next, referring to fig. 8E, a gate conductor 161 and at least one floating gate conductor 171 are formed on a side of the second dielectric layer 20 away from the isolation layer 13.
Next, referring to fig. 8F, the second dielectric layer 20 is etched using the gate conductor 161 and the at least one floating gate conductor 171 as masks, so as to form the gate 16 formed by the gate conductor 161 and the second dielectric layer 20 and the floating gate formed by the floating gate conductor 171 and the second dielectric layer.
After etching the second dielectric layer 20, a third dielectric layer 30 is deposited on the etched-out region of the second dielectric layer 20, such that the third dielectric layer 30 wraps or covers the gate 16 and the at least one floating gate.
And directly grounding the floating gate or grounding the floating gate to obtain the grounded floating gate 17.
In this embodiment, after step S740, the method further includes:
referring to fig. 8G, a third dielectric layer 21 is deposited on the etched-out region of the second dielectric layer 20, such that the third dielectric layer 21 wraps or covers the gate and at least one of the floating gates.
The embodiment of the application provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate; a semiconductor layer disposed on the substrate; the isolation layer is arranged on one side, away from the substrate, of the semiconductor layer; a source electrode and a drain electrode disposed on the isolation layer, the source electrode and the drain electrode being in ohmic contact with the isolation layer; and a gate electrode and at least one grounded floating gate disposed on the isolation layer and grounded or grounded. The influence of leakage current in the floating gate on an electric field peak value generated by the floating gate is avoided by arranging at least one grounded floating gate or grounded floating gate between the source electrode and the drain electrode, so that electric field integral based on the electric field peak is increased, the working voltage of the semiconductor device is improved, and the overall reliability of the semiconductor device is improved.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (11)
1. A semiconductor device, characterized in that the semiconductor device comprises:
a substrate;
a semiconductor layer disposed on the substrate;
the isolation layer is arranged on one side, away from the substrate, of the semiconductor layer;
a source electrode and a drain electrode disposed on the isolation layer, the source electrode and the drain electrode being in ohmic contact with the isolation layer; and
a gate electrode disposed on the isolation layer and at least one grounded or grounded floating gate electrode.
2. The semiconductor device according to claim 1, wherein the number of the grounded floating gates is plural, and a plurality of the grounded floating gates are provided separately from each other.
3. The semiconductor device according to claim 1, further comprising a first dielectric layer disposed on a side of the isolation layer away from the substrate, wherein the grounded floating gate has a stripe shape, and a plurality of the grounded floating gates are disposed on the first dielectric layer at intervals.
4. The semiconductor device of any of claims 1-3, wherein the grounded floating gate comprises a second dielectric layer disposed on the isolation layer and a floating gate conductor disposed on the second dielectric layer.
5. The semiconductor device of claim 4, wherein the grounded floating gate is a Schottky grounded floating gate or an insulated grounded floating gate.
6. The semiconductor device of claim 5, further comprising a negatively charged gate floating gate disposed between the gate and the isolation layer with an insulating medium disposed therebetween.
7. The semiconductor device of claim 6, wherein the metal portions of the insulated grounded floating gate and the gate floating gate are made of the same metal material.
8. The semiconductor device of claim 6, wherein the gate and the grounded floating gate are stacked, and a third dielectric layer is disposed on the isolation layer and wraps or covers the gate and at least one grounded floating gate.
9. A method of manufacturing a semiconductor device, the method comprising:
forming a semiconductor layer based on a substrate;
forming an isolation layer on one side of the semiconductor layer far away from the substrate;
manufacturing and forming a source electrode and a drain electrode which are in ohmic contact with the isolation layer on one side of the isolation layer away from the substrate;
and manufacturing a grid electrode and at least one grounded floating gate which is grounded or subjected to grounding treatment on one side of the isolation layer far away from the semiconductor layer.
10. The method of manufacturing a semiconductor device according to claim 9, wherein the gate electrode and the grounded floating gate are stacked, and the gate electrode and the at least one grounded or grounded floating gate are formed on a side of the isolation layer away from the semiconductor layer, and the method comprises:
depositing a second dielectric layer in the area between the source electrode and the drain electrode on the isolation layer;
forming a gate conductor and at least one floating gate conductor on a side of the second dielectric layer away from the isolation layer;
forming a gate formed of the gate conductor and the second dielectric layer and a floating gate formed of the floating gate conductor and the second dielectric layer;
and grounding or grounding the floating gate to obtain a grounded floating gate.
11. The method of manufacturing a semiconductor device according to claim 10, wherein after the gate electrode and the at least one grounded or grounded floating gate electrode are formed on a side of the isolation layer away from the semiconductor layer, the method further comprises:
and depositing a third dielectric layer on the etched region of the second dielectric layer, so that the third dielectric layer wraps or covers the grid and the at least one grounded floating gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810731422.4A CN110690281B (en) | 2018-07-05 | 2018-07-05 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810731422.4A CN110690281B (en) | 2018-07-05 | 2018-07-05 | Semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110690281A true CN110690281A (en) | 2020-01-14 |
| CN110690281B CN110690281B (en) | 2023-08-08 |
Family
ID=69106794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810731422.4A Active CN110690281B (en) | 2018-07-05 | 2018-07-05 | Semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110690281B (en) |
Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100770132B1 (en) * | 2006-10-30 | 2007-10-24 | 페어차일드코리아반도체 주식회사 | Gan semiconductor device |
| US20080135880A1 (en) * | 2006-11-17 | 2008-06-12 | The Furukawa Electric Co., Ltd. | Nitride semiconductor heterojunction field effect transistor |
| CN101320751A (en) * | 2007-06-06 | 2008-12-10 | 西安能讯微电子有限公司 | HEMT device and manufacturing method thereof |
| JP2010278333A (en) * | 2009-05-29 | 2010-12-09 | Furukawa Electric Co Ltd:The | Semiconductor device and method of manufacturing the same |
| CN103000673A (en) * | 2011-09-09 | 2013-03-27 | 瑞萨电子株式会社 | Semiconductor device and method of manufacturing the same |
| US20130193487A1 (en) * | 2010-08-02 | 2013-08-01 | Seles Es S.P.A. | High electron mobility transistors with field plate electrode |
| CN103765565A (en) * | 2011-08-22 | 2014-04-30 | 瑞萨电子株式会社 | Semiconductor device |
| CN104916678A (en) * | 2014-03-14 | 2015-09-16 | 株式会社东芝 | Semiconductor device |
| CN104993825A (en) * | 2015-07-01 | 2015-10-21 | 东南大学 | Gallium arsenide-based low-leakage-current double-cantilever-beam-switch double-gate frequency divider |
| JP2015211104A (en) * | 2014-04-25 | 2015-11-24 | 株式会社デンソー | Semiconductor device and electronic circuit using the same |
| US20150340483A1 (en) * | 2014-05-21 | 2015-11-26 | International Rectifier Corporation | Group III-V Device Including a Shield Plate |
| CN105355659A (en) * | 2015-11-06 | 2016-02-24 | 西安电子科技大学 | Trench-gate AlGaN/GaN HEMT device structure and manufacturing method |
| CN106158952A (en) * | 2016-09-26 | 2016-11-23 | 南方科技大学 | High electron mobility transistor and preparation method thereof |
| CN106158954A (en) * | 2016-09-26 | 2016-11-23 | 南方科技大学 | High electron mobility transistor and preparation method thereof |
| WO2018054377A1 (en) * | 2016-09-26 | 2018-03-29 | 南方科技大学 | High-electron-mobility transistor and preparation method therefor |
-
2018
- 2018-07-05 CN CN201810731422.4A patent/CN110690281B/en active Active
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100770132B1 (en) * | 2006-10-30 | 2007-10-24 | 페어차일드코리아반도체 주식회사 | Gan semiconductor device |
| US20080135880A1 (en) * | 2006-11-17 | 2008-06-12 | The Furukawa Electric Co., Ltd. | Nitride semiconductor heterojunction field effect transistor |
| CN101320751A (en) * | 2007-06-06 | 2008-12-10 | 西安能讯微电子有限公司 | HEMT device and manufacturing method thereof |
| JP2010278333A (en) * | 2009-05-29 | 2010-12-09 | Furukawa Electric Co Ltd:The | Semiconductor device and method of manufacturing the same |
| US20130193487A1 (en) * | 2010-08-02 | 2013-08-01 | Seles Es S.P.A. | High electron mobility transistors with field plate electrode |
| CN103765565A (en) * | 2011-08-22 | 2014-04-30 | 瑞萨电子株式会社 | Semiconductor device |
| CN103000673A (en) * | 2011-09-09 | 2013-03-27 | 瑞萨电子株式会社 | Semiconductor device and method of manufacturing the same |
| CN104916678A (en) * | 2014-03-14 | 2015-09-16 | 株式会社东芝 | Semiconductor device |
| JP2015211104A (en) * | 2014-04-25 | 2015-11-24 | 株式会社デンソー | Semiconductor device and electronic circuit using the same |
| US20150340483A1 (en) * | 2014-05-21 | 2015-11-26 | International Rectifier Corporation | Group III-V Device Including a Shield Plate |
| CN104993825A (en) * | 2015-07-01 | 2015-10-21 | 东南大学 | Gallium arsenide-based low-leakage-current double-cantilever-beam-switch double-gate frequency divider |
| CN105355659A (en) * | 2015-11-06 | 2016-02-24 | 西安电子科技大学 | Trench-gate AlGaN/GaN HEMT device structure and manufacturing method |
| CN106158952A (en) * | 2016-09-26 | 2016-11-23 | 南方科技大学 | High electron mobility transistor and preparation method thereof |
| CN106158954A (en) * | 2016-09-26 | 2016-11-23 | 南方科技大学 | High electron mobility transistor and preparation method thereof |
| WO2018054377A1 (en) * | 2016-09-26 | 2018-03-29 | 南方科技大学 | High-electron-mobility transistor and preparation method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110690281B (en) | 2023-08-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11721753B2 (en) | Method of fabricating a transistor | |
| JP5735139B2 (en) | Semiconductor device having low conductivity electric field control element | |
| CN110649096B (en) | High-voltage n-channel HEMT device | |
| CN103426910B (en) | Power semiconductor element and edge termination structure thereof | |
| CN110660851A (en) | High-voltage n-channel HEMT device | |
| US10461161B1 (en) | GaN device with floating field plates | |
| CN115274825A (en) | Semiconductor device and preparation method thereof | |
| CN110649097B (en) | High-voltage p-channel HFET device | |
| CN110993683A (en) | Power semiconductor device and manufacturing method thereof | |
| US11862680B2 (en) | Electrostatic discharge protection structure, nitride-based device having the same and method for manufacturing nitride-based device | |
| US9543402B1 (en) | Integrated high performance lateral schottky diode | |
| CN110660843A (en) | High-voltage p-channel HEMT device | |
| CN117174756B (en) | SiC MOSFET cell structure with double multilayer shielding structure, device and preparation method | |
| US11264450B2 (en) | Semiconductor device and manufacturing method | |
| CN115050819B (en) | Gallium nitride transistor for reducing input capacitance of multilayer field plate | |
| CN110690281B (en) | Semiconductor device and method of manufacturing the same | |
| CN113394283B (en) | High-voltage HEMT device with composite layer structure | |
| US20220336656A1 (en) | Semiconductor device trench termination structure | |
| CN113394284B (en) | High-voltage MIS-HEMT device with composite layer structure | |
| CN114830352A (en) | Laterally diffused metal oxide semiconductor transistor and manufacturing method thereof | |
| US7307329B2 (en) | Electronic device with guard ring | |
| US20220208963A1 (en) | Esd protection device | |
| CN116799050A (en) | Semiconductor transistor with a high-voltage power supply | |
| CN118039688A (en) | Bidirectional opening HEMT device and manufacturing method | |
| CN111326568A (en) | Nitride device with guard ring structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |