CN110690271A - High-voltage DMOS device and manufacturing method thereof - Google Patents
High-voltage DMOS device and manufacturing method thereof Download PDFInfo
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- CN110690271A CN110690271A CN201911037547.8A CN201911037547A CN110690271A CN 110690271 A CN110690271 A CN 110690271A CN 201911037547 A CN201911037547 A CN 201911037547A CN 110690271 A CN110690271 A CN 110690271A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000009792 diffusion process Methods 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 238000002347 injection Methods 0.000 claims abstract description 12
- 239000007924 injection Substances 0.000 claims abstract description 12
- FRWYFWZENXDZMU-UHFFFAOYSA-N 2-iodoquinoline Chemical compound C1=CC=CC2=NC(I)=CC=C21 FRWYFWZENXDZMU-UHFFFAOYSA-N 0.000 claims abstract description 6
- LTPBRCUWZOMYOC-UHFFFAOYSA-N beryllium oxide Inorganic materials O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000002955 isolation Methods 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
- 239000000243 solution Substances 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 230000015556 catabolic process Effects 0.000 description 15
- 241001391944 Commicarpus scandens Species 0.000 description 3
- 230000033228 biological regulation Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- VLXBWPOEOIIREY-UHFFFAOYSA-N dimethyl diselenide Natural products C[Se][Se]C VLXBWPOEOIIREY-UHFFFAOYSA-N 0.000 description 1
- WQOXQRCZOLPYPM-UHFFFAOYSA-N dimethyl disulfide Chemical compound CSSC WQOXQRCZOLPYPM-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a high-voltage DMOS device and a manufacturing method thereof, and the high-voltage DMOS device comprises a P-type semiconductor substrate, wherein an n-high resistance drift layer is arranged on the front surface of the P-type semiconductor substrate, a beryllium oxide isolation layer is arranged on the back surface of the P-type semiconductor substrate, n-type epitaxial layers are arranged on two sides of the n-high resistance drift layer, the height of the n-type epitaxial layer is smaller than that of the n-high resistance drift layer, a P-type doped trap is formed between the n-type epitaxial layer and the n-high resistance drift layer, an injection channel layer is arranged in the P-type doped trap, the injection channel layer comprises a first diffusion layer arranged in the P-type doped trap, a second diffusion layer is arranged above the first diffusion layer, a source electrode is embedded in the P-type doped trap, and a drain electrode is connected to. The invention has stronger pressure resistance.
Description
Technical Field
The invention relates to the technical field of DMOS devices, in particular to a high-voltage DMOS device and a manufacturing method thereof.
Background
DMOS (double diffused MOS) transistors are one type of MOSFET (metal field effect transistor on semiconductor) that uses diffusion to form the transistor area. DMDS transistors are commonly used as power transistors to provide high voltage circuits for power integrated circuit applications. DMOS transistors provide higher current per unit area when low forward voltage drops are required. The existing DMOS device is easy to break down and has poor voltage withstanding performance. We therefore provide a high voltage DMOS device and method of making the same.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a high-voltage DMOS device.
In order to solve the technical problems, the invention provides the following technical scheme:
the invention discloses a high-voltage DMOS device which comprises a P-type semiconductor substrate, wherein an n-high resistance drift layer is arranged on the front side of the P-type semiconductor substrate, a beryllium oxide isolation layer is arranged on the back side of the P-type semiconductor substrate, n-type epitaxial layers are arranged on two sides of the n-high resistance drift layer, the height of the n-type epitaxial layer is smaller than that of the n-high resistance drift layer, a P-type doped trap is formed between the n-type epitaxial layer and the n-high resistance drift layer, an injection channel layer is arranged in the P-type doped trap and comprises a first diffusion layer arranged in the P-type doped trap, a second diffusion layer is arranged above the first diffusion layer, a source electrode is embedded in the P-type doped trap, and a drain electrode is connected to the top of the n-high resistance drift layer.
In a preferred embodiment of the present invention, the first diffusion layer and the second diffusion layer form a channel having a concentration gradient.
In a preferred embodiment of the present invention, the first diffusion layer is a boron diffusion layer, and the concentration of boron is 1015cm-2。
In a preferred embodiment of the present invention, the second diffusion layer is a phosphorus diffusion layer, and the concentration of phosphorus is 1013cm-2。
As a preferred technical solution of the present invention, a field oxide layer is disposed on the top of the n-high resistance drift region, and a gate layer covering the upper side of the injection channel layer and the side end of the field oxide layer is disposed on the field oxide layer.
As a preferred technical solution of the present invention, the field oxide layer is a silicon dioxide layer.
A manufacturing method of a high-voltage DMOS device comprises the steps of generating an n-high resistance drift layer on a p-type semiconductor substrate, growing and forming n-type epitaxial layers on two sides of the n-high resistance drift layer, enabling the height of the n-type epitaxial layer to be smaller than that of the n-high resistance drift layer, forming a p-type doped trap, injecting boron solution into the p-type doped trap, carrying out thermal diffusion to form a first diffusion layer, injecting phosphorus solution into the p-type doped trap, carrying out thermal diffusion to form a second diffusion layer, and forming an injection channel layer with a certain concentration gradient by matching the first diffusion layer and the second diffusion layer; and growing a field oxide layer on the top of the n-high-resistance drift region, wherein the field oxide layer is provided with a grid layer covering the upper part of the injection channel layer and the side end of the field oxide layer.
The invention has the beneficial effects that: this kind of high-voltage DMOS device makes to improve holistic breakdown voltage greatly through n-high resistance drift layer for n-high resistance drift layer is difficult for being punctured, can carry out normal work under more highly compressed work regulation, thereby has improved holistic resistance to pressure greatly, and need not to improve breakdown voltage through the thickness that increases traditional drift layer, makes holistic volume less. In addition, the field oxide layer is arranged, so that the electrical connection between the active layer and the substrate layer is effectively isolated, the breakdown point can be structurally transferred from internal breakdown to silicon dioxide layer breakdown, and the overall voltage resistance is improved. In addition, the beryllium oxide isolation layer is arranged on the back surface of the p-type semiconductor substrate, so that the overall heat dissipation performance is effectively improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.
In the drawings:
fig. 1 is a schematic diagram of a high voltage DMOS device of the present invention;
fig. 2 is a partial structural schematic diagram of a high voltage DMOS device of the present invention.
In the figure: 1. a p-type semiconductor substrate; 2. an n-high resistance drift layer; 3. an n-type epitaxial layer; 4. a P-type doped trap; 5. injecting the channel layer; 6. a first diffusion layer; 7. a second diffusion layer; 8. a source electrode; 9. a drain electrode; 10. a field oxide layer; 11. a gate layer; 12. a beryllium oxide isolation layer.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Example (b): as shown in fig. 1 and 2, a high voltage DMOS device of the present invention includes a p-type semiconductor substrate 1, the front surface of the p-type semiconductor substrate 1 is provided with an n-high resistance drift layer 2, the back surface of the p-type semiconductor substrate 1 is provided with a beryllium oxide isolation layer 12, the two sides of the n-high resistance drift layer 2 are provided with n-type epitaxial layers 3, the height of the n-type epitaxial layers 3 is less than that of the n-high resistance drift layer 2, a P-type doped trap 4 is formed between the n-type epitaxial layer 3 and the n-high resistance drift layer 2, an implant channel layer 5 is provided within the p-type doped trap 4, the implant channel layer 5 comprising a first diffusion layer 6 disposed within the p-type doped trap 4, a second diffusion layer 7 is arranged above the first diffusion layer 6, a source electrode 8 is embedded in the p-type doped trap 4, and a drain electrode 9 is connected to the top of the n-high resistance drift layer 2. The overall breakdown voltage is greatly improved through the n-high resistance drift layer 2, so that the n-high resistance drift layer 2 is not easy to break down, and can normally work under the higher-voltage work regulation, thereby greatly improving the overall voltage resistance without increasing the thickness of the traditional drift layer to improve the breakdown voltage, and ensuring that the overall size is smaller. In addition, the field oxide layer 10 is arranged, so that the electrical connection between the active layer and the substrate layer is effectively isolated, the breakdown point can be structurally transferred from internal breakdown to silicon dioxide layer breakdown, and the overall voltage resistance is improved.
Wherein the first diffusion layer 6 and the second diffusion layer 7 form a channel with a concentration gradient.
Wherein the first diffusion layer 6 is a boron diffusion layer, and the concentration of boron is 1015cm-2。
Wherein the second diffusion layer 7 is a phosphorus diffusion layer with a phosphorus concentration of 1013cm-2。
The top of n-high resistance drift region 2 is equipped with field oxide 10, be equipped with on the field oxide 10 and cover in injecting into grid layer 11 of channel layer 5 top and field oxide 10 side.
The field oxide layer 10 is a silicon dioxide layer.
According to the invention, the overall breakdown voltage is greatly improved through the n-high resistance drift layer 2, so that the n-high resistance drift layer 2 is not easy to break down, and can normally work under higher-voltage working regulation, thereby greatly improving the overall voltage resistance without increasing the thickness of the traditional drift layer to improve the breakdown voltage, and ensuring that the overall volume is smaller. In addition, the field oxide layer 10 is arranged, so that the electrical connection between the active layer and the substrate layer is effectively isolated, the breakdown point can be structurally transferred from internal breakdown to silicon dioxide layer breakdown, and the overall voltage resistance is improved.
A manufacturing method of a high-voltage DMOS device comprises the steps of generating an n-high resistance drift layer on a p-type semiconductor substrate, growing and forming n-type epitaxial layers on two sides of the n-high resistance drift layer, enabling the height of the n-type epitaxial layer to be smaller than that of the n-high resistance drift layer, forming a p-type doped trap, injecting boron solution into the p-type doped trap, carrying out thermal diffusion to form a first diffusion layer, injecting phosphorus solution into the p-type doped trap, carrying out thermal diffusion to form a second diffusion layer, and forming an injection channel layer with a certain concentration gradient by matching the first diffusion layer and the second diffusion layer; and growing a field oxide layer on the top of the n-high-resistance drift region, wherein the field oxide layer is provided with a grid layer covering the upper part of the injection channel layer and the side end of the field oxide layer.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A high voltage DMOS device characterized by: the P-type doped trap structure comprises a P-type semiconductor substrate (1), wherein an n-high resistance drift layer (2) is arranged on the front face of the P-type semiconductor substrate (1), a beryllium oxide isolation layer (12) is arranged on the back face of the P-type semiconductor substrate (1), n-type epitaxial layers (3) are arranged on two sides of the n-high resistance drift layer (2), the height of each n-type epitaxial layer (3) is smaller than that of the n-high resistance drift layer (2), a P-type doped trap (4) is formed between each n-type epitaxial layer (3) and each n-high resistance drift layer (2), an injection channel layer (5) is arranged in each P-type doped trap (4), each injection channel layer (5) comprises a first diffusion layer (6) arranged in each P-type doped trap (4), a second diffusion layer (7) is arranged above each first diffusion layer (6), and a source electrode (8) is embedded in each P-type doped trap (4), the top of the n-high resistance drift layer (2) is connected with a drain electrode (9).
2. A high-voltage DMOS device according to claim 1, wherein said first (6) and second (7) diffusions form channels with a concentration gradient.
3. A high voltage DMOS device according to claim 3, wherein said first diffusion layer (6) is a boron diffusion layer, the concentration of boron being 1015cm-2。
4. A high-voltage DMOS device according to claim 3, wherein said second diffusion layer (7) is a phosphorus diffusion layer, the concentration of phosphorus being 1013cm-2。
5. A high-voltage DMOS device according to claim 1, characterized in that said n-high resistance drift region (2) is provided on top with a field oxide layer (10), said field oxide layer (10) being provided with a gate layer (11) overlying the implanted channel layer (5) and at the side of the field oxide layer (10).
6. A high voltage DMOS device according to claim 1, wherein said field oxide layer (10) is a silicon dioxide layer.
7. The manufacturing method of the high-voltage DMOS device according to claims 1-6, wherein an n-high resistance drift layer is formed on a p-type semiconductor substrate, then n-type epitaxial layers are formed on two sides of the n-high resistance drift layer in a growing mode, so that the height of the n-type epitaxial layer is smaller than that of the n-high resistance drift layer, a p-type doped trap is formed, boron solution is injected into the p-type doped trap and thermal diffusion is carried out, a first diffusion layer is formed, then phosphorus solution is injected into the p-type doped trap and thermal diffusion is carried out, a second diffusion layer is formed, and the two diffusion layers are matched with each other to form an injection channel layer with a certain concentration gradient; and growing a field oxide layer on the top of the n-high-resistance drift region, wherein the field oxide layer is provided with a grid layer covering the upper part of the injection channel layer and the side end of the field oxide layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911037547.8A CN110690271A (en) | 2019-10-29 | 2019-10-29 | High-voltage DMOS device and manufacturing method thereof |
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| CN201911037547.8A CN110690271A (en) | 2019-10-29 | 2019-10-29 | High-voltage DMOS device and manufacturing method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060192256A1 (en) * | 2005-01-21 | 2006-08-31 | Cooper James A | High-voltage power semiconductor device |
| US20090057713A1 (en) * | 2007-08-31 | 2009-03-05 | Infineon Technologies Austria Ag | Semiconductor device with a semiconductor body |
| CN102130163A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | ESD (electrostatic discharge) high-voltage DMOS (diffused metal oxide semiconductor) device and manufacturing method thereof |
| CN104201203A (en) * | 2014-08-13 | 2014-12-10 | 四川广义微电子股份有限公司 | High voltage resistance LDMOS device and manufacturing method thereof |
| CN210743952U (en) * | 2019-10-29 | 2020-06-12 | 浙江艾水科技有限公司 | High-voltage DMOS device |
-
2019
- 2019-10-29 CN CN201911037547.8A patent/CN110690271A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060192256A1 (en) * | 2005-01-21 | 2006-08-31 | Cooper James A | High-voltage power semiconductor device |
| US20090057713A1 (en) * | 2007-08-31 | 2009-03-05 | Infineon Technologies Austria Ag | Semiconductor device with a semiconductor body |
| CN102130163A (en) * | 2010-01-18 | 2011-07-20 | 上海华虹Nec电子有限公司 | ESD (electrostatic discharge) high-voltage DMOS (diffused metal oxide semiconductor) device and manufacturing method thereof |
| CN104201203A (en) * | 2014-08-13 | 2014-12-10 | 四川广义微电子股份有限公司 | High voltage resistance LDMOS device and manufacturing method thereof |
| CN210743952U (en) * | 2019-10-29 | 2020-06-12 | 浙江艾水科技有限公司 | High-voltage DMOS device |
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