CN110690219B

CN110690219B - Three-dimensional memory, preparation method thereof and photoetching mask

Info

Publication number: CN110690219B
Application number: CN201911259258.2A
Authority: CN
Inventors: 朱宏斌; 高志虎
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-12-10
Filing date: 2019-12-10
Publication date: 2020-07-14
Anticipated expiration: 2039-12-10
Also published as: CN110690219A

Abstract

The embodiment of the invention discloses a three-dimensional memory, a preparation method thereof and a photoetching mask plate; wherein the three-dimensional memory comprises: a substrate; the stacked structure is positioned on the substrate and comprises a plurality of memory cell areas which are arranged at intervals along the plane direction of the substrate; a filling material layer filled between at least two adjacent memory cell regions; wherein the stacked structure further comprises stress buffer regions distributed between the memory cell regions, and the filler material layer is spaced between the at least two adjacent memory cell regions by the stress buffer regions.

Description

Three-dimensional memory, preparation method thereof and photoetching mask

Technical Field

The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory, a preparation method thereof and a photoetching mask.

Background

Memory (Memory) is a Memory device used in modern information technology to store information. With the increasing demands of various electronic devices for integration and data storage density, it is increasingly difficult for a common two-dimensional memory device to meet the demands, and in such a situation, a three-dimensional (3D) memory has come into play.

In the preparation of the three-dimensional memory, a stacked structure is mainly formed on a substrate, and the stacked structure is divided into a plurality of memory cell areas arranged at intervals along the plane direction of the substrate, so that a memory array is formed; step areas (SS areas) are formed around the memory cell areas, so that each layer of grid electrodes in the memory cell areas are in conductive connection with vertical Contact holes (CT) through corresponding step surfaces, and therefore addressing operation of each layer of grid electrodes corresponding to the memory cell areas is achieved. Above the step regions and between the memory cell regions, a layer of filler material needs to be formed, which provides a planar top surface for the device structure.

However, the conventional process for manufacturing a three-dimensional memory is highly affected by local stress because the periphery of the memory cell region is filled with a filling material layer, and the filling material layer is easily deformed in a subsequent high-temperature annealing process due to the process, so that the memory cell region is extruded, and in addition, the top pattern of the memory cell region is a large-size Block (GB), which is often used as an Overlay (OV L) marker in a photolithography process, and once the boundary of the memory cell region is extruded and deformed, Overlay deviation is directly caused, thereby reducing the product yield.

Disclosure of Invention

In view of the above, embodiments of the present invention provide a three-dimensional memory, a method for manufacturing the same, and a photolithography mask to solve at least one of the problems in the background art.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

an embodiment of the present invention provides a three-dimensional memory, including:

a substrate;

the stacked structure is positioned on the substrate and comprises a plurality of memory cell areas which are arranged at intervals along the plane direction of the substrate;

a filling material layer filled between the memory cell regions;

the stacked structure further comprises a stress buffer region distributed between at least two adjacent memory cell regions, and the filling material layer is spaced by the stress buffer region between the at least two adjacent memory cell regions.

In the above scheme, the distance between the stress buffer region and the nearest memory cell region is in a range of 5 μm to 20 μm.

In the above scheme, two stress buffer regions are distributed between the at least two adjacent memory cell regions, and the two stress buffer regions are respectively distributed adjacent to the mutually adjacent side walls of the two adjacent memory cell regions, so that the distance between the stress buffer region and the most adjacent memory cell region is smaller than the distance between the two stress buffer regions.

In the above scheme, the stress buffer region extends in a direction parallel to the adjacent sidewalls of the two adjacent memory cell regions, and the length of the stress buffer region is equal to the length of the sidewall of the memory cell region.

In the above scheme, the filling material layer includes an ethyl orthosilicate layer.

The embodiment of the invention also provides a preparation method of the three-dimensional memory, which comprises the following steps:

providing a substrate, and forming a stack layer on the substrate;

etching the stacked layer to divide the stacked layer into a plurality of memory cell areas which are arranged at intervals along the substrate plane direction and stress buffer areas which are distributed between at least two adjacent memory cell areas;

and filling and forming a filling material layer between the memory cell areas, wherein the filling material layer is spaced by the stress buffer area between the at least two adjacent memory cell areas.

In the above scheme, in the step of etching the stack layer, a step region of the three-dimensional memory is formed.

In the above scheme, two stress buffer regions are distributed between the at least two adjacent memory cell regions, and the two stress buffer regions are respectively distributed adjacent to the mutually adjacent side walls of the two adjacent memory cell regions, so that the distance between the stress buffer region and the most adjacent memory cell region is smaller than the distance between the two stress buffer regions. In the above scheme, the stress buffer region extends in a direction parallel to the adjacent sidewalls of the two adjacent memory cell regions, and the length of the stress buffer region is equal to the length of the sidewall of the memory cell region.

In the above scheme, the filling and forming the filling material layer includes: and filling tetraethoxysilane between the storage unit area and the stress buffer area to form the filling material layer.

The embodiment of the present invention further provides a photolithography mask, which is used in a process of forming a stacked structure of a three-dimensional memory by etching, wherein the stacked structure includes a plurality of memory cell regions arranged at intervals and a stress buffer region distributed between at least two adjacent memory cell regions, and the photolithography mask includes:

a plurality of first pattern areas arranged at intervals, wherein the first pattern areas correspond to the storage unit areas of the three-dimensional memory;

and the second pattern area is positioned between at least two adjacent first pattern areas and corresponds to the stress buffer area.

In the above scheme, a distance between the second pattern region and the nearest first pattern region ranges from 5 μm to 20 μm.

In the above scheme, two second pattern areas are distributed between the at least two adjacent first pattern areas, and the two second pattern areas are respectively distributed adjacent to the mutually adjacent side edges of the two adjacent first pattern areas, so that the distance between the second pattern area and the most adjacent first pattern area is smaller than the distance between the two second pattern areas.

In the above solution, the second pattern region extends in a direction parallel to the mutually adjacent side edges of the two adjacent first pattern regions, and the length of the second pattern region is equal to the length of the side edge of the first pattern region.

The three-dimensional memory and the preparation method thereof and the photoetching mask provided by the embodiment of the invention are provided; wherein the three-dimensional memory comprises: a substrate; the stacked structure is positioned on the substrate and comprises a plurality of memory cell areas which are arranged at intervals along the plane direction of the substrate; a filling material layer filled between at least two adjacent memory cell regions; wherein the stacked structure further comprises stress buffer regions distributed between the memory cell regions, and the filler material layer is spaced between the at least two adjacent memory cell regions by the stress buffer regions. Therefore, the stress buffer area is arranged between the storage unit areas, the large filling material layer is isolated, the stress of the filling material layer is relieved, the filling material layer is prevented from extruding the storage unit areas, and the product yield is finally improved.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1 is a schematic diagram illustrating a layout of memory cell regions of a three-dimensional memory according to the related art;

FIG. 2 is a cross-sectional view of a three-dimensional memory structure according to an embodiment of the invention;

FIG. 3 is a schematic diagram illustrating an arrangement of memory cell regions of a three-dimensional memory according to an embodiment of the invention;

fig. 4 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is present in the invention.

Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

Fig. 1 is a schematic diagram illustrating a layout of a memory cell region of a three-dimensional memory according to the related art. As shown, memory cell regions are arranged at intervals on a substrate, thereby forming a memory array; several adjacent memory cell regions in the memory array form a memory plane, for example, as shown by oval boxes in fig. 1, four longitudinally arranged memory cell regions form a memory plane. A step region is formed around the memory cell region; above the step region and between the memory cell regions, a filling material layer, such as a Tetraethylorthosilicate (TEOS) layer, is formed.

Due to process reasons, the filling material layer is easy to deform in a subsequent high-temperature annealing process, so that the memory cell region is extruded; as shown in fig. 1, both sides of the memory cell region are pressed and deformed in the direction of the arrow. Not only causes stress trouble to the memory cell area, but also directly influences the alignment precision in the subsequent photoetching process and reduces the product yield.

Based on this, the embodiment of the invention provides a three-dimensional memory; please refer to fig. 2. As shown, the three-dimensional memory includes: a substrate 10; a stacked structure 11 located on the substrate 10, wherein the stacked structure 11 includes a plurality of memory cell regions arranged at intervals along a planar direction of the substrate 10; a filler material layer 12 filled between the memory cell regions; the stacked structure 11 further includes a stress buffer region distributed between at least two adjacent memory cell regions, and the filling material layer 12 is spaced between the at least two adjacent memory cell regions by the stress buffer region.

The stress buffer area is arranged between the memory cell areas, so that the large filling material layer is isolated, the stress of the filling material layer is relieved, the filling material layer is prevented from extruding the memory cell areas, and the product yield is improved finally.

Here, the substrate 10 may be a semiconductor substrate; specifically including at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

The stacked structure 11 may include a plurality of first material layers 111 and second material layers 112 alternately arranged. The first material layer 111 is a dielectric layer; the second material layer 112 is a gate layer or a dummy gate layer.

The material of the first material layer 111 includes, but is not limited to, silicon oxide, silicon nitride layer, silicon oxynitride, etc.; in one embodiment, the material of the first material layer 111 is SiO₂. For the case that the second material layer 112 is a gate layer, the material of the second material layer 112 includes, for example, metal tungsten (W); for the case where the second material layer 112 is a dummy gate layer, the material of the second material layer 112 includes, for example, one of an oxide layer, a nitride layer, a silicon carbide layer, a silicon layer, and a silicon germanium layer; in a specific embodiment, the material of the second material layer 112 is SiN.

The memory cell region is a memory region on the substrate 10 and insulated and isolated from each other. The memory cell area may also be referred to as an array memory area; the shape of each memory cell region is, for example, a rectangle or a square. The memory cell region includes a plurality of channel structures formed in Channel Holes (CH) and at least one Array Common Source (ACS). The CH penetrates through the stacked structure 11, and the channel structure provides a channel for the flow of carriers for each stacked gate layer; the drain electrode of the memory cell region can be positioned at the top of the CH and is connected with the channel structure; the ACS is the source of the memory cell area. In practical application, the circulation path of the current in the three-dimensional memory is as follows: CH top drain-CH inner channel structure-lower select transistor channel layer SEG-substrate-ACS.

The filling material layer 12 is filled between the memory cell regions to electrically isolate the memory cell regions; therefore, the filler material layer 12 may also be referred to as a space insulating layer. The material of the filling material layer 12 is an insulating material, and the dielectric constant is, for example, 4 or more; and may specifically comprise a silicon oxide material, including TEOS for example.

The lower surface of the filler material layer 12 is in contact with the upper surface of the substrate 10; the upper surface of the filler material layer 12 is located above the upper surface of the memory cell region (specifically, the upper surface of the stacked structure 11), and it should be understood that the above includes the case where the two are coplanar, i.e., the filler material layer 12 provides a flat top surface for the device structure after dividing the memory cell region. In one embodiment, a step region is formed around the memory cell region, and the filling material layer 12 is filled on the step region and on the substrate 10 between the memory cell regions.

This embodiment only shows the case where the stress buffer region is located between at least two adjacent memory cell regions; it should be understood that when a memory cell region is surrounded by a large-area filler material layer in other sidewall directions (e.g., a memory cell region located at a side, an angular position of a memory array, or a memory cell region located beside a dicing street) in addition to having the large-area filler material layer between adjacent memory cell regions, the stacked structure may further include stress buffer regions distributed near any sidewall of the memory cell region to alleviate the compression of the filler material layer on any sidewall of the memory cell region.

In order to achieve better stress buffering effect, the distance between the stress buffer region and the nearest adjacent memory cell region is in the range of 5 μm-20 μm.

Fig. 3 is a schematic layout diagram of a memory cell area of a three-dimensional memory according to an embodiment of the invention. Fig. 3 can be regarded as a top view of the three-dimensional memory structure in fig. 2, and fig. 2 is a cross-sectional view of the memory cell region in fig. 3 along the longitudinal direction.

With reference to fig. 2 to 3, two stress buffer regions are distributed between at least two adjacent memory cell regions, and the two stress buffer regions are respectively distributed adjacent to the adjacent sidewalls of the two adjacent memory cell regions, so that the distance between the stress buffer region and the nearest memory cell region is smaller than the distance between the two stress buffer regions. In the present embodiment, as shown by the arrows in fig. 2, most of the stress generated by the filling material layer is blocked between the two stress buffer regions, and will not directly act on the sidewalls of the memory cell region due to the buffering effect of the stress buffer regions; the part of the filling material layer between the stress buffer area and the nearest memory cell area generates negligible stress due to small area; therefore, the extrusion of the filling material layer on the memory cell area is better avoided.

In one embodiment, the two stress buffer regions are each located at a distance in a range from 5 μm to 20 μm from the respective nearest neighbor memory cell region. And the distance between the two stress buffer regions is at least more than 100 μm, much larger than the distance between the stress buffer region and the nearest neighbor memory cell region.

In practical applications, as a common layout manner of the memory cell region, the step regions are mainly formed on two sides in the width direction of the storage plane (i.e. the lateral direction in fig. 3), i.e. the CTs conductively connected to the gate electrode are mainly distributed on two sides in the lateral direction in fig. 3; in this direction, the area of the filler material layer is not large due to the presence of the step region, and in this case, the stress buffer regions may be provided only on both sides of the memory cell region in the longitudinal direction of the memory plane (i.e., the longitudinal direction in fig. 3). Specifically, the three-dimensional memory may further include: the grid connecting areas are distributed on two sides of the memory unit area along a first direction in the substrate plane and are used for leading out the grid layer in the memory unit area in a conductive mode; the stress buffer regions are distributed between at least two adjacent memory cell regions along a second direction within the substrate plane, the second direction being perpendicular to the first direction.

In this embodiment, the width of the stress buffer is, for example, in the range of 10-50 μm.

In this embodiment, the stress buffer region extends in a direction parallel to the sidewalls of the two adjacent memory cell regions, and the length of the stress buffer region is equal to the length of the sidewalls of the memory cell regions.

In this embodiment, the filler material layer comprises a TEOS layer.

The embodiment of the invention also provides a preparation method of the three-dimensional memory; refer specifically to FIG. 4. As shown, the method comprises the steps of:

step 201, providing a substrate, and forming a stack layer on the substrate;

202, etching the stacked layer to divide the stacked layer into a plurality of memory cell areas which are arranged at intervals along the substrate plane direction and stress buffer areas which are distributed between at least two adjacent memory cell areas;

step 203, filling and forming a filling material layer between the memory cell regions, wherein the filling material layer is spaced between the at least two adjacent memory cell regions by the stress buffer region.

In the embodiment of the invention, the stress buffer area is formed between the memory cell areas by the stacked layers, so that the large filling material layers are isolated, the stress of the filling material layers is relieved, the memory cell areas are prevented from being extruded by the filling material layers, and the product yield is finally improved.

Here, the substrate may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

The stacked layers may be the same as the stacked structure 11 in the above-described embodiment, or may be different from the stacked structure 11. Specifically, the stacked layer and the stacked structure 11 may be structures on the surface of the substrate in the same or different processes. The stacked layer is not limited to the case of including a plurality of dielectric layers and dummy gate layers which are alternately arranged; the embodiment of the application does not exclude the situation that a plurality of alternately arranged dielectric layers and gate layers are directly formed on the substrate, namely, the gate layers are formed by refilling gate materials without removing the dummy gate layers subsequently.

In a specific embodiment, in the step of etching the stack layer, a step region of the three-dimensional memory is formed.

In one embodiment, the distance between the stress buffer region and the nearest memory cell region is in a range of 5 μm to 20 μm.

In an embodiment, two stress buffer regions are distributed between the at least two adjacent memory cell regions, and the two stress buffer regions are respectively distributed adjacent to the mutually adjacent sidewalls of the two adjacent memory cell regions, so that a distance between the stress buffer region and the most adjacent memory cell region is smaller than a distance between the two stress buffer regions.

In one embodiment, the stress buffer region extends in a direction parallel to sidewalls of the two adjacent memory cell regions that are adjacent to each other, and a length of the stress buffer region is equal to a length of the sidewalls of the memory cell regions.

In a specific embodiment, the filling forms a layer of filler material, including: and filling TEOS between the memory cell area and the stress buffer area to form the filling material layer.

the memory comprises a plurality of first pattern areas which are arranged at intervals, wherein the first pattern areas correspond to memory cell areas of a three-dimensional memory;

Here, the structure of the photolithography mask may refer to the memory cell region layout of the three-dimensional memory in fig. 3. The position of the storage unit area of the three-dimensional memory corresponds to a first pattern area on the photoetching mask plate, and the position of the stress buffer area of the three-dimensional memory corresponds to a second pattern area on the photoetching mask plate.

It can be understood that the first pattern area and the second pattern area may be both hollow patterns so that the corresponding area is an exposure area, or the first pattern area and the second pattern area are both shielding patterns so that the corresponding area is a non-exposure area; here, whether the first pattern region and the second pattern region are hollow patterns or shielding patterns depends on whether the photoresist covering the corresponding region is a positive photoresist or a negative photoresist.

It should be noted that the first pattern region and the second pattern region in the photolithography mask are understood as two regions that are not connected and do not coincide; in other words, the first pattern region and the second pattern region are independent regions with a space therebetween. This is consistent with the relationship between the memory cell region and the stress buffer region in the stacked structure of the three-dimensional memory, so that the memory cell region and the stress buffer region formed based on the lithography reticle etching are also regions independent of each other with a space in between.

In this embodiment, the photolithography mask may be a mask used in a process of forming a step region of a three-dimensional memory.

In the etching process of the step area, the boundary of the first pattern area can be continuously trimmed along with the change of the position of the etching step, and the second pattern area can be kept unchanged in the step etching process.

In one embodiment, the distance between the second pattern region and the nearest first pattern region is in a range of 5 μm to 20 μm.

In a specific embodiment, two second pattern areas are distributed between the at least two adjacent first pattern areas, and the two second pattern areas are respectively distributed adjacent to the mutually adjacent side edges of the two adjacent first pattern areas, so that the distance between the second pattern area and the most adjacent first pattern area is smaller than the distance between the two second pattern areas.

In one embodiment, the second pattern region extends in a direction parallel to the side edges of the two adjacent first pattern regions adjacent to each other, and the length of the second pattern region is equal to the length of the side edges of the first pattern regions.

It should be noted that the embodiment of the three-dimensional memory provided by the invention, the embodiment of the preparation method of the three-dimensional memory and the embodiment of the photoetching mask belong to the same concept; the technical features of the technical means described in the embodiments may be arbitrarily combined without conflict. It should be further noted that, in the three-dimensional memory provided by the embodiment of the present invention, the technical feature combinations thereof can already solve the technical problems to be solved by the present invention; therefore, the three-dimensional memory provided by the embodiment of the present invention is not limited by the method for manufacturing the three-dimensional memory provided by the embodiment of the present invention, and any three-dimensional memory manufactured by the method for manufacturing the three-dimensional memory structure provided by the embodiment of the present invention is within the protection scope of the present invention.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.

Claims

1. A three-dimensional memory, comprising:

a substrate;

a stack structure located on the substrate,

the stacked structure comprises a plurality of storage unit areas which are arranged at intervals along the substrate plane direction;

a filling material layer filled between the memory cell regions;

wherein the stacked structure further comprises a stress buffer region distributed between at least two adjacent memory cell regions, the filler material layer being spaced by the stress buffer region between the at least two adjacent memory cell regions;

the stacked structure comprises a plurality of first material layers and a plurality of second material layers which are alternately arranged.

2. The three-dimensional memory according to claim 1, wherein the distance between the stress buffer region and the nearest neighbor memory cell region is in a range of 5 μm to 20 μm.

3. The three-dimensional memory according to claim 1, wherein two stress buffer regions are distributed between the at least two adjacent memory cell regions, and the two stress buffer regions are respectively distributed adjacent to the side walls of the two adjacent memory cell regions adjacent to each other, so that the distance between the stress buffer region and the nearest memory cell region is smaller than the distance between the two stress buffer regions.

4. The three-dimensional memory according to claim 1, wherein the stress buffer region extends in a direction parallel to sidewalls of the two adjacent memory cell regions adjacent to each other, and a length of the stress buffer region is equal to a length of the sidewalls of the memory cell regions.

5. The three-dimensional memory according to claim 1, wherein the layer of filler material comprises a layer of ethyl orthosilicate.

6. A method of fabricating a three-dimensional memory, the method comprising:

providing a substrate, and forming a stack layer on the substrate; the stacked layers comprise a plurality of first material layers and a plurality of second material layers which are alternately arranged;

7. The method of claim 6, wherein the step region of the three-dimensional memory is formed in the step of etching the stack layer.

8. The method of claim 6, wherein the distance between the stress buffer region and the nearest memory cell region is in a range of 5 μm to 20 μm.

9. The method as claimed in claim 6, wherein two stress buffer regions are disposed between the at least two adjacent memory cell regions, and the two stress buffer regions are disposed adjacent to the sidewalls of the two adjacent memory cell regions, respectively, such that the distance between the stress buffer region and the nearest memory cell region is smaller than the distance between the two stress buffer regions.

10. The method of claim 6, wherein the stress buffer region extends in a direction parallel to sidewalls of the two adjacent memory cell regions adjacent to each other, and a length of the stress buffer region is equal to a length of the sidewalls of the memory cell regions.

11. The method of claim 6, wherein the filling forms a layer of filler material, comprising: and filling tetraethoxysilane between the storage unit area and the stress buffer area to form the filling material layer.

12. A photoetching mask plate is used in the process of etching and forming a stacked structure of a three-dimensional memory, the stacked structure comprises a plurality of memory unit areas which are arranged at intervals and stress buffer areas which are distributed between at least two adjacent memory unit areas, and the photoetching mask plate comprises:

13. The reticle of claim 12, wherein a distance between the second pattern region and a nearest neighbor first pattern region is in a range of 5 μ ι η -20 μ ι η.

14. The reticle of claim 12, wherein two second pattern regions are distributed between the at least two adjacent first pattern regions, the two second pattern regions being distributed adjacent to the sides of the two adjacent first pattern regions that are adjacent to each other, respectively, such that a distance between the second pattern region and the most adjacent first pattern region is smaller than a distance between the two second pattern regions.

15. The reticle of claim 12, wherein the second pattern region extends in a direction parallel to sides of the two adjacent first pattern regions that are adjacent to each other, the length of the second pattern region being equal to the length of the sides of the first pattern regions.