CN110676323B - NMOS transistor, forming method thereof and charge pump circuit - Google Patents

NMOS transistor, forming method thereof and charge pump circuit Download PDF

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CN110676323B
CN110676323B CN201910876179.XA CN201910876179A CN110676323B CN 110676323 B CN110676323 B CN 110676323B CN 201910876179 A CN201910876179 A CN 201910876179A CN 110676323 B CN110676323 B CN 110676323B
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region
well region
charge pump
voltage
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CN110676323A (en
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盖春赟
刘威
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

An NMOS transistor, a method of forming the same, and a charge pump circuit, the NMOS transistor comprising: forming an N-type deep well in the P-type substrate; forming a P-type well region in the N-type deep well; forming a gate structure on the surface of the P-type well region part; forming an N-type source region and an N-type drain region in the P-type well regions at two sides of the grid structure; forming an N-type well region surrounding the P-type well region, wherein one part of the N-type well region is positioned in an N-type deep well outside the P-type well region, and the other part of the N-type well region is positioned in a P-type substrate outside the N-type deep well region; and connecting the grid structure with a control voltage end, taking the N-type drain region as a voltage input end, connecting the voltage input end with an input voltage, and connecting the N-type source region and the N-type well region together as a voltage output end. The NMOS transistor can increase the output voltage of the voltage output terminal.

Description

NMOS transistor, forming method thereof and charge pump circuit
Technical Field
The present invention relates to the field of charge pumps, and in particular, to an NMOS transistor capable of increasing an output voltage, a method of forming the same, and a charge pump circuit.
Background
As electronic devices tend to be miniaturized and highly sophisticated, charge pump circuits are an important component of flash memories, which largely determine the initial programming, erasing, and read-write speeds of flash memories. These processes in flash memories often require high voltages to complete, which makes charge pump circuits increasingly important in flash memories. Various high performance charge pumps are increasingly being investigated as one of the hot spots of current research. Meanwhile, the charge pump circuit is one of hot spots of research in the field of energy collection. Is convenient for integration and miniaturization, and becomes an advantage point in special environment.
The cross-coupling charge pump has the advantages of simple structure, high multiplication efficiency, no special requirement on two-phase clock signals, no breakdown risk and the like, and is widely applied.
The existing cross-coupling charge pump comprises two NMOS tubes (MN 1 and MN 2), two PMOS tubes (MP 1 and MP 2) and two capacitors (C1 and C2), wherein the Source end (Source) and the body end (Bulk) of the MN1 and the MN2 are connected with an input end Vin; the Drain terminal (Drain) of MN1, the Drain terminal (MP 1), the Gate terminal (Gate) of MN2, the Gate terminal of MP2 and one end of capacitor C1 are all connected together, and the other end of capacitor C1 is connected with input clock CLK; the drain end of the MN2, the drain end of the MP2, the gate end of the MN1, the gate end of the MP1 and one end of the capacitor C2 are all connected together, the other end of the capacitor C2 is connected with the input clock CLKN, and the input clock CLK and the input clock CLKN are mutually opposite; the source and body terminals of MP1 and MP2 are connected to the output terminal Vout 1.
In order to further increase the gain (or output voltage), there are many methods for improving the cross-coupled charge pump, such as floating-well (floating-well) technology, four-phase clock technology, etc.
The above method brings problems such as increasing the gain (or output voltage) as well, for example: in the four-phase clock technology, the grid electrode of a transistor serving as a switch bears high voltage and needs to be realized by a high-voltage device, so that the power consumption is increased; in the floating-well technology, an additional auxiliary transistor and a control clock are added, and the area of a charge pump is increased.
Disclosure of Invention
The invention aims to solve the technical problems of increasing the gain (or output voltage) without increasing the area of a charge pump and adding extra devices, reducing the cost and the power consumption.
The invention provides an NMOS transistor for a charge pump circuit, comprising:
a P-type substrate;
an N-type deep well in the P-type substrate;
the P-type well region is positioned in the N-type deep well;
a gate structure located on a surface of the P-type well region portion;
the N-type source region and the N-type drain region are positioned in the P-type well regions at two sides of the grid structure;
the N-type well region surrounds the P-type well region, one part of the N-type well region is positioned in the N-type deep well outside the P-type well region, and the other part of the N-type well region is positioned in the P-type substrate outside the N-type deep well region;
the grid structure is connected with a control voltage end, the N-type drain region is used as a voltage input end, the voltage input end is connected with an input voltage, and the N-type source region and the N-type well region are connected together to be used as a voltage output end.
Optionally, an N-type doped region is provided in the N-type well region at one side of the N-type source region, a P-type doped region is provided in the P-type well region at one side of the N-type drain region, the N-type doped region is connected with the voltage output terminal, and the P-type doped region is connected with the voltage input terminal.
Optionally, the output voltage of the voltage output terminal is increased by reducing the doping concentration of the N-type well region.
The invention also provides a method for forming the NMOS transistor, which comprises the following steps:
providing a P-type substrate;
forming an N-type deep well in the P-type substrate;
forming a P-type well region in the N-type deep well;
forming a gate structure on the surface of the P-type well region part;
forming an N-type source region and an N-type drain region in the P-type well regions at two sides of the grid structure;
forming an N-type well region surrounding the P-type well region, wherein one part of the N-type well region is positioned in an N-type deep well outside the P-type well region, and the other part of the N-type well region is positioned in a P-type substrate outside the N-type deep well region;
and connecting the grid structure with a control voltage end, taking the N-type drain region as a voltage input end, connecting the voltage input end with an input voltage, and connecting the N-type source region and the N-type well region together as a voltage output end.
The invention also provides a charge pump circuit, which comprises N stages of charge pumps connected in series, wherein each stage of charge pump comprises two NMOS transistors and two PMOS transistors, and the two NMOS transistors and the two PMOS transistors are connected in a cross coupling way.
Optionally, the two NMOS transistors include the same first NMOS transistor and the same second NMOS transistor, the two PMOS transistors include the same first PMOS transistor and the same second PMOS transistor, and the two NMOS transistors and the two PMOS transistors in each stage of the charge pump are cross-coupled in a manner that: the drain electrode of the first NMOS transistor is connected with the drain electrode of the second NMOS transistor to serve as a voltage output end, the source electrode of the first NMOS transistor is connected with the source electrode of the first PMOS transistor and is connected with the grid electrode of the second NMOS transistor and the grid electrode of the second PMOS transistor, the source electrode of the second NMOS transistor is connected with the source electrode of the second PMOS transistor and is connected with the grid electrode of the first NMOS transistor and the grid electrode of the first PMOS transistor, the drain electrode of the first PMOS transistor and the drain electrode of the second PMOS transistor are connected together to serve as a voltage output end, and the voltage output end is connected with the voltage input end of the next stage charge pump.
Optionally, the voltage input end of the first stage charge pump is connected with the input voltage, and the voltage output end of the last stage charge pump is used as the voltage output end of the charge pump circuit.
Optionally, the charge pump further comprises a first clock and a second clock, wherein in each charge pump, a connection point of the source electrode of the first NMOS transistor and the source electrode of the first PMOS transistor is connected with the first clock through a first capacitor, and a connection point of the source electrode of the second NMOS transistor and the source electrode of the second PMOS transistor is connected with the second clock through a second capacitor.
Optionally, the source electrode of the first PMOS transistor is connected to the ground terminal through a third capacitor, the source electrode of the second PMOS transistor is connected to the ground terminal through a fourth capacitor, one end of the first capacitor connected to the first clock is connected to the ground terminal through a fifth capacitor, and one end of the second capacitor connected to the second clock is connected to the ground terminal through a sixth capacitor.
Optionally, the charge pump has a stage number of 3-10, the input voltage is 3V-5V, the first clock and the second clock are opposite to each other, the clock frequencies of the first clock and the second clock are 15MHz-25MHz, the clock amplitudes of the first clock and the second clock are 3V-5V, the capacitance values of the first capacitor and the second capacitor are 0.8pF-1.5pF, and the capacitance values of the third capacitor, the fourth capacitor, the fifth capacitor and the current capacitor are 0.8pF-1.5pF.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the NMOS transistor for a charge pump circuit of the present invention includes: forming an N-type deep well in the P-type substrate; forming a P-type well region in the N-type deep well; forming a gate structure on the surface of the P-type well region part; forming an N-type source region and an N-type drain region in the P-type well regions at two sides of the grid structure; forming an N-type well region surrounding the P-type well region, wherein one part of the N-type well region is positioned in an N-type deep well outside the P-type well region, and the other part of the N-type well region is positioned in a P-type substrate outside the N-type deep well region; and connecting the grid structure with a control voltage end, taking the N-type drain region as a voltage input end, connecting the voltage input end with an input voltage, and connecting the N-type source region and the N-type well region together as a voltage output end. Because the N-type well region surrounds the P-type well region, one part of the N-type well region is positioned in the N-type deep well outside the P-type well region, and the other part of the N-type well region is positioned in the P-type substrate outside the N-type deep well, on one hand, voltage can be applied to the N-type deep well through the N-type well region, so that the N-type deep well is reversely isolated from the P-type well region and the P-type substrate; on the other hand, by increasing the area of the N-type well region (the other part is located in the P-type substrate outside the N-type deep well), the concentration of impurity ions in the N-type well region is reduced, and the breakdown voltage of the NMOS transistor can be increased, so that when the N-type source region and the N-type well region are connected together as a voltage output terminal, the output voltage of the voltage output terminal is increased, and when the NMOS transistor is used in a charge pump circuit, the output voltage of the charge pump circuit can be increased, and the gain can be improved.
Further, the gate structure is connected to the control voltage terminal, the N-type drain region is used as a voltage input terminal, the voltage input terminal is connected to an input voltage Vin, the N-type source region and the N-type well region are connected together to be used as a voltage output terminal, an N-type doped region is arranged in the N-type well region at one side of the N-type source region, the ion doping concentration in the N-type doped region is larger than that in the N-type well region, the width and depth of the N-type doped region are smaller than those of the N-type well region, a P-type doped region is arranged in the P-type well region at one side of the N-type drain region, the N-type doped region is connected with a voltage output terminal, the N-type well region is connected with the voltage output terminal through the N-type doped region, and the P-type doped region is connected with the voltage input terminal.
The charge pump circuit comprises N stages of charge pumps connected in series, wherein each stage of charge pump comprises two NMOS transistors and two PMOS transistors, and the two NMOS transistors and the two PMOS transistors are connected in a cross coupling mode. Under the condition that an auxiliary transistor and a control clock are not added (only the structure of an NMOS transistor is improved), the charge pump circuit greatly improves the output voltage of the voltage pump circuit and improves the gain of the charge pump; compared with the prior charge pump circuit, the structure saves the area and reduces the power consumption under the same performance; and the transistor in the charge pump circuit has no overload problem (overload is that the voltage of each end of the transistor is larger than the power supply voltage).
Drawings
Fig. 1 is a schematic diagram of an NMOS transistor for a charge pump circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a charge pump circuit including the NMOS transistor shown in fig. 1.
Detailed Description
As mentioned in the background, the existing methods for improving the cross-coupled charge pump, although it can be improved, also bring about some problems, such as: in the four-phase clock technology, the grid electrode of a transistor serving as a switch bears high voltage and needs to be realized by a high-voltage device, so that the power consumption is increased; in the floating-well technology, an additional auxiliary transistor and a control clock are added, and the area of a charge pump is increased.
To this end, the present invention provides an NMOS transistor capable of increasing an output voltage, which includes: forming an N-type deep well in the P-type substrate; forming a P-type well region in the N-type deep well; forming a gate structure on the surface of the P-type well region part; forming an N-type source region and an N-type drain region in the P-type well regions at two sides of the grid structure; forming an N-type well region surrounding the P-type well region, wherein one part of the N-type well region is positioned in an N-type deep well outside the P-type well region, and the other part of the N-type well region is positioned in a P-type substrate outside the N-type deep well region; and connecting the grid structure with a control voltage end, taking the N-type drain region as a voltage input end, connecting the voltage input end with an input voltage, and connecting the N-type source region and the N-type well region together as a voltage output end. Because the N-type well region surrounds the P-type well region, one part of the N-type well region is positioned in the N-type deep well outside the P-type well region, and the other part of the N-type well region is positioned in the P-type substrate outside the N-type deep well, on one hand, voltage can be applied to the N-type deep well through the N-type well region, so that the N-type deep well is reversely isolated from the P-type well region and the P-type substrate; on the other hand, by increasing the area of the N-type well region (the other part is located in the P-type substrate outside the N-type deep well), the concentration of impurity ions in the N-type well region is reduced, and the breakdown voltage of the NMOS transistor can be increased, so that when the N-type source region and the N-type well region are connected together as a voltage output terminal, the output voltage of the voltage output terminal is increased, and when the NMOS transistor is used in a charge pump circuit, the output voltage of the charge pump circuit can be increased, and the gain can be improved.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings. In describing embodiments of the present invention in detail, the schematic drawings are not necessarily to scale and are merely illustrative and should not be taken as limiting the scope of the invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
Fig. 1 is a schematic diagram of an NMOS transistor for a charge pump circuit according to an embodiment of the present invention; fig. 2 is a schematic diagram of a charge pump circuit including the NMOS transistor shown in fig. 1.
Referring to fig. 1, the NMOS transistor M for a charge pump circuit includes:
a P-type substrate 201;
an N-type deep well 202 (DNW) located in the P-type substrate 201;
a P-type well region 203 (PW) located in the N-type deep well 202;
a gate structure 206 located on a portion of the surface of the P-type well region 203;
an N-type source region 208 and an N-type drain region 207 located in the P-type well region 203 at both sides of the gate structure 206;
an N-type well region 209 surrounding the P-type well region 203, wherein a part of the N-type well region 209 is located in the N-type deep well 202 outside the P-type well region 203, and another part of the N-type well region 209 is located in the P-type substrate 201 outside the N-type deep well 202;
the gate structure 206 is connected to a control voltage terminal Vcon, the N-type drain region 207 serves as a voltage input terminal 20, the voltage input terminal 20 is connected to an input voltage Vin, and the N-type source region 208 and the N-type well region 209 are connected together to serve as a voltage output terminal 21.
Specifically, the material of the P-type substrate 201 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); silicon On Insulator (SOI), germanium On Insulator (GOI); or may be other materials such as III-V compounds such as gallium arsenide. In this embodiment, the P-type substrate 201 is made of monocrystalline silicon (Si).
The P-type substrate 201 is doped with P-type impurity ions, wherein the P-type impurity ions are one or more of boron ions, gallium ions and indium ions.
An N-type deep well 202 (DNW) is formed in the P-type substrate 201, and the N-type deep well 202 may be formed by implanting N-type impurity ions into the P-type substrate 201 by an ion implantation process, where the N-type impurity ions are one or more of phosphorus ions, arsenic ions, and antimony ions.
A P-type well region 203 (PW) is formed in the N-type deep well 202, and the P-type well region 203 may be formed by implanting P-type impurity ions into the N-type deep well 202 using an ion implantation process. The depth of the P-type well region 203 is smaller than that of the N-type deep well 202, and the width of the P-type well region 203 is smaller than that of the N-type deep well 202, so that an N-type well region 209 surrounding the P-type well region 203 is formed around the P-type well region 203.
The N-type well region 209 surrounds the P-type well region 203, the depth of the N-type well region 209 is equal to the depth of the P-type well region 203, and a part of the N-type well region 209 is located in the N-type deep well 202 outside the P-type well region 209, and another part of the N-type well region 209 is located in the P-type substrate 201 outside the N-type deep well 202, on the one hand, a voltage can be applied to the N-type deep well 202 through the N-type well region 209, so that the N-type deep well 202 is reversely isolated from the P-type well region 209 and the P-type substrate 201; on the other hand, by increasing the area of the N-type well region (another portion is located in the P-type substrate 201 outside the N-type deep well 202), and decreasing the concentration of impurity ions in the N-type well region 209 (specifically, the concentration of impurity ions in the N-type well region 209 may be made smaller than the concentration of impurity ions in the N-type deep well 202), the breakdown voltage of the NMOS transistor M may be increased, so that when the N-type source region 208 and the N-type well region 209 are connected together as the voltage output terminal 21, the output voltage Vout1 of the voltage output terminal is increased, and when the NMOS transistor M is used in the charge pump circuit, the output voltage of the charge pump circuit may be increased, and the gain may be improved.
A gate structure 206 is formed on a portion of the surface of the P-type well region 203, and the gate structure 206 includes a gate dielectric layer 205 located on a portion of the surface of the P-type well region 203 and a gate electrode 204 located on a surface of the gate dielectric layer 205. In one embodiment, the forming of the gate structure 206 includes: forming a gate dielectric material layer and a gate electrode material layer on the gate dielectric material layer on the surface of the P-type substrate 201 through a deposition process; forming a patterned mask layer on the surface of the gate electrode material layer, wherein the patterned mask layer exposes a region of the gate electrode material layer to be etched and removed; and sequentially etching the gate electrode material layer and the gate dielectric material layer by taking the patterned mask layer as a mask, and forming a gate dielectric layer 205 and a gate electrode 204 positioned on the surface of the gate dielectric layer 205 on part of the surface of the P-type well region 203.
The gate dielectric layer 205 may be made of silicon oxide or a high-K (K is greater than or equal to 2.5) dielectric material, and the gate electrode 204 may be made of polysilicon or a metal material.
In an embodiment, the sidewall surface of the gate structure 206 may further form a sidewall (not shown). The side wall can be of a single-layer or multi-layer stacked structure, and the material of the side wall can be one or more of silicon oxide, silicon nitride and silicon oxynitride.
The P-type well region 203 at two sides of the gate structure 206 is formed with an N-type source region 208 and an N-type drain region 207, the depth of the N-type source region 208 and the N-type drain region 207 is smaller than the depth of the P-type well region 203, and the N-type source region 208 and the N-type drain region 207 are doped with N-type impurity ions. The N-type source region 208 and the N-type drain region 207 may be formed by implanting N-type impurity ions into the P-type well region 203 using an ion implantation process.
The N-type well region 209 at one side of the N-type source region 208 is provided with an N-type doped region 211, the ion doping concentration in the N-type doped region 211 is greater than the ion doping concentration in the N-type well region 209, the width and depth of the N-type doped region 211 are smaller than those of the N-type well region 209, the P-type well region 203 at one side of the N-type drain region 207 is provided with a P-type doped region 210, the N-type doped region 211 is connected with the voltage output terminal 21, the N-type well region 209 is connected with the voltage output terminal 21 through the N-type doped region 211, and the P-type doped region 210 is connected with the voltage input terminal 20.
The embodiment of the invention also provides a method for forming the NMOS transistor M, which comprises the following steps:
providing a P-type substrate 201;
forming an N-type deep well 202 in the P-type substrate 201, specifically, forming the N-type deep well 202 by an ion implantation process;
forming a P-type well region 203 in the N-type deep well 202, wherein the P-type deep well 202 may be formed by an ion implantation process;
forming a gate structure 206 on a portion of the surface of the P-type well region 203;
an N-type source region 208 and an N-type drain region 207 are formed in the P-type well region 203 at both sides of the gate structure 206, and the N-type source region 208 and the N-type drain region 207 may be formed by an ion implantation process
An N-type well region 209 surrounding the P-type well region 203 is formed, and a part of the N-type well region 209 is located in the N-type deep well 202 outside the P-type well region 203, and another part is located in the P-type substrate 201 outside the N-type deep well 202;
the gate structure 206 is connected to a control voltage terminal Vcon, the N-type drain region 207 is used as a voltage input terminal 20, the voltage input terminal 20 is connected to an input voltage Vin, and the N-type source region 208 and the N-type well region 209 are connected together as a voltage output terminal 21.
The semiconductor device further comprises an N-type doped region 211 formed in the N-type well region 209 at one side of the N-type source region 208, wherein the N-type doped region 211 is connected with the voltage output end 21, a P-type doped region 210 is formed in the P-type well region 203 at one side of the N-type drain region 207, and the voltage output end 21 is connected with the voltage input end 20..
The embodiment of the present invention further provides a charge pump circuit, referring to fig. 2, including N stages of charge pumps 31 connected in series, where each stage of charge pump 31 includes two NMOS transistors M (referring to fig. 1) and two PMOS transistors as described above, and the two NMOS transistors and the two PMOS transistors are connected in a cross-coupling manner.
Specifically, the two NMOS transistors include the same first NMOS transistor M1 and the same second NMOS transistor M2, the two PMOS transistors include the same first PMOS transistor P1 and the same second PMOS transistor P2, and the two NMOS transistors and the two PMOS transistors in each stage of charge pump are cross-coupled in the following manner: the drain (and body) of the first NMOS transistor M1 and the drain (and body) of the second NMOS transistor M2 are connected together as a voltage output terminal 20, the source of the first NMOS transistor M1 is connected to the source of the first PMOS transistor and to the gate of the second NMOS transistor M2 and to the gate of the second PMOS transistor P2, the source of the second NMOS transistor M2 is connected to the source of the second PMOS transistor P2 and to the gate of the first NMOS transistor M1 and to the gate of the first PMOS transistor P1, the drain (and body) of the first PMOS transistor P1 and the drain (and body) of the second PMOS transistor P2 are connected together as a voltage output terminal 21, and the voltage output terminal 21 is connected to the voltage input terminal of the next stage charge pump.
The voltage input end 20 of the first stage charge pump is connected with the input voltage Vin, and the voltage output end 21 of the last stage charge pump is used as the voltage output end of the charge pump circuit, and the voltage output end outputs the voltage Vout2.
The charge pump circuit further includes a first clock CLK1 and a second clock CLK2, in each charge pump, a connection point between a source of the first NMOS transistor M1 and a source of the first PMOS transistor P2 is connected to the first clock CLK1 through a first capacitor C1, and a connection point between a source of the second NMOS transistor M2 and a source of the second PMOS transistor P2 is connected to the second clock CLK2 through a second capacitor C2. The source of the first PMOS transistor P1 is connected to the ground through a third capacitor C3, the source of the second PMOS transistor P2 is connected to the ground through a fourth capacitor C4, one end of the first capacitor C1 connected to the first clock CLK1 is connected to the ground through a fifth capacitor C5, and one end of the second capacitor C2 connected to the second clock CLK is connected to the ground through a sixth capacitor C6.
The basic principle of the charge pump is as follows: the primary stage transfers charge backwards so that the voltage rises.
In an embodiment, the charge pump has a stage number of 3-10, the input voltage is 3V-5V, the first clock and the second clock are opposite to each other, the clock frequencies of the first clock and the second clock are 15MHz-25MHz, the clock amplitudes of the first clock and the second clock are 3V-5V, the capacitance values of the first capacitor and the second capacitor are 0.8pF-1.5pF, and the capacitance values of the third capacitor, the fourth capacitor, the fifth capacitor and the current capacitor are 0.8pF-1.5pF.
In a specific embodiment, the number of stages of the charge pump is 4, the input voltage is 3.3V, the first clock and the second clock are opposite to each other, the clock frequencies of the first clock and the second clock are 20MHz, the clock amplitudes of the first clock and the second clock are 3.3V, the capacitance values of the first capacitor and the second capacitor are 1pF, the capacitance values of the third capacitor, the fourth capacitor, the fifth capacitor and the current capacitor are 1pF, and by the above arrangement, the voltage of the output voltage Vout2 of the charge pump circuit of the present application is 16.19V, which is improved by about 7.4V compared with the output voltage 8.79V of the existing charge pump circuit, and the gain of the charge pump is greatly improved.
Thus, in the cross-coupled charge pump circuit having the NMOS transistor M (refer to fig. 1) described above in the present embodiment, the magnitude of the output voltage is greatly improved, and the charge pump gain is improved without adding an auxiliary transistor and a control clock (only the structure of the NMOS transistor M is improved); compared with the prior charge pump circuit, the structure saves the area and reduces the power consumption under the same performance; and the transistor in the charge pump circuit has no overload problem (overload is that the voltage of each end of the transistor is larger than the power supply voltage).
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.

Claims (9)

1. An NMOS transistor for a charge pump circuit, comprising:
a P-type substrate;
an N-type deep well in the P-type substrate;
the P-type well region is positioned in the N-type deep well;
a gate structure located on a surface of the P-type well region portion;
the N-type source region and the N-type drain region are positioned in the P-type well regions at two sides of the grid structure;
the N-type well region surrounds the P-type well region, one part of the N-type well region is positioned in the N-type deep well outside the P-type well region, and the other part of the N-type well region is positioned in the P-type substrate outside the N-type deep well region;
the grid structure is connected with a control voltage end, the N-type drain region is used as a voltage input end, the voltage input end is connected with an input voltage, and the N-type source region and the N-type well region are connected together to be used as a voltage output end; an N-type doped region is arranged in the N-type well region at one side of the N-type source region, a P-type doped region is arranged in the P-type well region at one side of the N-type drain region, the N-type doped region is connected with the voltage output end, and the P-type doped region is connected with the voltage input end.
2. The NMOS transistor for a charge pump circuit of claim 1, wherein the output voltage at the voltage output terminal is increased by decreasing the doping concentration of the N-type well region.
3. A method of forming the NMOS transistor of any of claims 1-2, comprising:
providing a P-type substrate;
forming an N-type deep well in the P-type substrate;
forming a P-type well region in the N-type deep well;
forming a gate structure on the surface of the P-type well region part;
forming an N-type source region and an N-type drain region in the P-type well regions at two sides of the grid structure;
forming an N-type well region surrounding the P-type well region, wherein one part of the N-type well region is positioned in an N-type deep well outside the P-type well region, and the other part of the N-type well region is positioned in a P-type substrate outside the N-type deep well region;
and connecting the grid structure with a control voltage end, taking the N-type drain region as a voltage input end, connecting the voltage input end with an input voltage, and connecting the N-type source region and the N-type well region together as a voltage output end.
4. A charge pump circuit comprising N stages of charge pumps in series, each stage of charge pump comprising two NMOS transistors and two PMOS transistors according to any of the preceding claims 1-2, the two NMOS transistors and the two PMOS transistors being cross-coupled.
5. The charge pump circuit of claim 4, wherein the two NMOS transistors comprise identical first and second NMOS transistors, the two PMOS transistors comprise identical first and second PMOS transistors, and the two NMOS transistors and the two PMOS transistors in each stage of the charge pump are cross-coupled in such a way that: the drain electrode of the first NMOS transistor is connected with the drain electrode of the second NMOS transistor to serve as a voltage output end, the source electrode of the first NMOS transistor is connected with the source electrode of the first PMOS transistor and is connected with the grid electrode of the second NMOS transistor and the grid electrode of the second PMOS transistor, the source electrode of the second NMOS transistor is connected with the source electrode of the second PMOS transistor and is connected with the grid electrode of the first NMOS transistor and the grid electrode of the first PMOS transistor, the drain electrode of the first PMOS transistor and the drain electrode of the second PMOS transistor are connected together to serve as a voltage output end, and the voltage output end is connected with the voltage input end of the next stage charge pump.
6. The charge pump circuit of claim 5, wherein the voltage input terminal of the first stage charge pump is connected to an input voltage and the voltage output terminal of the last stage charge pump is used as the voltage output terminal of the charge pump circuit.
7. The charge pump circuit of claim 6, further comprising a first clock and a second clock, wherein in each charge pump, a connection point of the source of the first NMOS transistor and the source of the first PMOS transistor is connected to the first clock through a first capacitor, and a connection point of the source of the second NMOS transistor and the source of the second PMOS transistor is connected to the second clock through a second capacitor.
8. The charge pump circuit of claim 7, wherein a source of the first PMOS transistor is connected to ground through a third capacitor, a source of the second PMOS transistor is connected to ground through a fourth capacitor, an end of the first capacitor connected to the first clock is connected to ground through a fifth capacitor, and an end of the second capacitor connected to the second clock is connected to ground through a sixth capacitor.
9. The charge pump circuit of claim 8, wherein the charge pump has a number of stages of 3-10, the input voltage is 3V-5V, the first clock and the second clock are inverted with respect to each other, the clock frequencies of the first clock and the second clock are 15MHz-25MHz, the clock amplitudes of the first clock and the second clock are 3V-5V, the capacitance values of the first capacitor and the second capacitor are 0.8pF-1.5pF, and the capacitance values of the third capacitor, the fourth capacitor, the fifth capacitor and the current capacitor are 0.8pF-1.5pF.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1592055A (en) * 2003-08-26 2005-03-09 三洋电机株式会社 Transistor circuit and booster circuit
JP2010187463A (en) * 2009-02-12 2010-08-26 Mitsumi Electric Co Ltd Charge pump circuit and device for switching power supply
US8008970B1 (en) * 2010-06-07 2011-08-30 Skyworks Solutions, Inc. Apparatus and method for enabled switch detection
CN104769717A (en) * 2012-10-17 2015-07-08 商升特公司 Semiconductor device and method of preventing latch-up in a charge pump circuit
CN105743328A (en) * 2016-04-28 2016-07-06 上海芯赫科技有限公司 Transistor, charge pump assembly and charge pump
CN108809084A (en) * 2018-06-14 2018-11-13 长江存储科技有限责任公司 Charge pump circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1592055A (en) * 2003-08-26 2005-03-09 三洋电机株式会社 Transistor circuit and booster circuit
JP2010187463A (en) * 2009-02-12 2010-08-26 Mitsumi Electric Co Ltd Charge pump circuit and device for switching power supply
US8008970B1 (en) * 2010-06-07 2011-08-30 Skyworks Solutions, Inc. Apparatus and method for enabled switch detection
CN104769717A (en) * 2012-10-17 2015-07-08 商升特公司 Semiconductor device and method of preventing latch-up in a charge pump circuit
CN105743328A (en) * 2016-04-28 2016-07-06 上海芯赫科技有限公司 Transistor, charge pump assembly and charge pump
CN108809084A (en) * 2018-06-14 2018-11-13 长江存储科技有限责任公司 Charge pump circuit

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