CN110676164A - Semiconductor process component, method of forming the same, and semiconductor process apparatus - Google Patents

Semiconductor process component, method of forming the same, and semiconductor process apparatus Download PDF

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Publication number
CN110676164A
CN110676164A CN201910973045.XA CN201910973045A CN110676164A CN 110676164 A CN110676164 A CN 110676164A CN 201910973045 A CN201910973045 A CN 201910973045A CN 110676164 A CN110676164 A CN 110676164A
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China
Prior art keywords
substrate
dielectric layer
forming
semiconductor process
layer
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蒋维楠
余兴
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Yangtze Delta Region Institute of Tsinghua University Zhejiang
ICLeague Technology Co Ltd
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Yangtze Delta Region Institute of Tsinghua University Zhejiang
ICLeague Technology Co Ltd
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Priority to CN201910973045.XA priority Critical patent/CN110676164A/en
Publication of CN110676164A publication Critical patent/CN110676164A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks

Abstract

A semiconductor process component, a method of forming the same, and a semiconductor process apparatus, wherein the method of forming comprises: providing a first substrate; forming a first groove in the first substrate; forming a first conductive layer in the first groove; forming a first dielectric layer on the first conductive layer and the first substrate; providing a second substrate; and carrying out first bonding treatment on the first substrate towards the second substrate, wherein the first dielectric layer is positioned between the first substrate and the second substrate. The method can simplify the preparation process steps and save the manufacturing cost.

Description

Semiconductor process component, method of forming the same, and semiconductor process apparatus
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor process component, a forming method thereof and semiconductor process equipment.
Background
In an ion doping apparatus or the like used in the manufacture of a liquid crystal panel, such as a plasma processing apparatus, an electron exposure apparatus, and an ion implantation apparatus used in the manufacture of semiconductor devices, it is required to reliably hold a semiconductor wafer or a glass substrate, which is an object to be processed, without damaging the substrate. In particular, recently, since contamination of a semiconductor wafer or a glass substrate, which is a processing target, is strictly controlled, most of the conventional methods of mechanically holding a substrate are replaced with electrostatic chuck methods using an electric attraction force.
The electrostatic chuck is a general name of an ultra-clean sheet bearing body, grabbing and carrying equipment suitable for atmospheric or vacuum environment, and the used electrostatic adsorption technology is an advantageous technology for replacing the traditional mechanical clamping and vacuum adsorption modes and is widely applied to the fields of semiconductors, panel display, optics and the like. When an object with static electricity is close to another object without static electricity, due to static induction, the side of the object without static electricity close to the object with static electricity will gather charges with opposite polarity to the charges carried by the charged object (the other side generates the same amount of charges with the same polarity), and due to the attraction of charges of different polarities, the phenomenon of electrostatic adsorption will be shown.
However, the current process for manufacturing semiconductor process components with electrostatic adsorption is complex and costly.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a semiconductor process part, a forming method thereof and semiconductor process equipment, so as to simplify the preparation process steps and save the manufacturing cost.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor process component, including: providing a first substrate; forming a first groove in the first substrate; forming a first conductive layer in the first groove; forming a first dielectric layer on the first conductive layer and the first substrate; providing a second substrate; and carrying out first bonding treatment on the first substrate towards the second substrate, wherein the first dielectric layer is positioned between the first substrate and the second substrate.
Optionally, the method further includes: before the first substrate faces a second substrate and is subjected to first bonding treatment, a second dielectric layer is formed on the surface of the second substrate; and carrying out first bonding treatment on the first dielectric layer towards the second dielectric layer.
Optionally, the material of the first substrate includes: aluminum oxide or aluminum nitride; the material of the second substrate includes: alumina or aluminum nitride.
Optionally, the material of the first dielectric layer includes: silicon oxide or silicon nitride.
Optionally, the material of the second dielectric layer includes: silicon oxide or silicon nitride.
Optionally, the material of the first conductive layer includes: one or more of molybdenum, tungsten, copper, nickel, aluminum or chromium.
Optionally, the roughness range of the surface of the first dielectric layer is 0 to 1 micrometer.
Optionally, the roughness range of the surface of the second dielectric layer is 0 to 1 micrometer.
Optionally, the forming method of the first trench includes: providing a first mask plate, wherein a mask opening penetrating through the first mask plate is formed in the first mask plate, and the position of the mask opening corresponds to the position and the size of the first groove; and placing a first mask on a first substrate, carrying out sand blasting treatment on the first substrate, and forming the first groove in the first substrate.
Optionally, the method for forming the first conductive layer includes: forming a conductive material film in the first groove and on the surface of the first substrate; and flattening the conductive material film until the surface of the first substrate is exposed, and forming the first conductive layer in the first groove.
Optionally, the method for forming the first dielectric layer includes: forming a first dielectric material film on the surface of the first conductive layer and the surface of the first substrate; and flattening the first dielectric material film, and forming the first dielectric layer on the surface of the first conductive layer and the surface of the first substrate.
Optionally, the forming method of the second dielectric layer includes: forming a second dielectric material film on the surface of the second substrate; and flattening the second medium material film, and forming the second medium layer on the surface of the second substrate.
Optionally, the method further includes: after a first dielectric layer and a second dielectric layer are formed and before the first bonding treatment, carrying out activation treatment on the surface of the first dielectric layer and the surface of the second dielectric layer; and after the activation treatment, carrying out first bonding treatment on the surface of the first dielectric layer facing the surface of the second dielectric layer.
Optionally, the method for activating processing includes: carrying out first cleaning on the surface of the first dielectric layer and the surface of the second dielectric layer by using diluted hydrofluoric acid or a mixed solution of diluted hydrofluoric acid and ammonium fluoride; and after the first cleaning treatment, carrying out second cleaning on the surface of the first medium layer and the surface of the second medium layer by using deionized water.
Optionally, the method for activating processing includes: and carrying out plasma treatment on the surface of the first dielectric layer and the surface of the second dielectric layer.
Optionally, the first bonding processing method includes: extruding and attaching the surface of the first dielectric layer to the surface of the second dielectric layer; and after the surface of the first dielectric layer faces the surface of the second dielectric layer and is extruded and attached, annealing treatment is carried out on the first dielectric layer and the second dielectric layer, so that the surface of the first dielectric layer is bonded with the surface of the second dielectric layer.
Optionally, the thickness of the first substrate ranges from 0.5 mm to 5 mm.
Optionally, the thickness of the second substrate ranges from 0.2 mm to 1 mm.
Optionally, a projection pattern of the first trench on the surface of the first substrate includes: one or more spirals, one or more nets, or one or more sheets.
Optionally, the method further includes: performing more than one stacking process after performing first bonding treatment on the first substrate towards the second substrate; each stacking process comprises the following steps: providing a third substrate, wherein the third substrate is internally provided with a second groove and a second conducting layer positioned in the second groove, and third dielectric layers are arranged on the second conducting layer and the third substrate; and carrying out second bonding treatment on the third dielectric layer towards the first substrate.
Correspondingly, the technical scheme of the invention also provides a semiconductor process part formed by adopting any one of the methods.
Correspondingly, the technical scheme of the invention also provides semiconductor process equipment, which comprises: such as the semiconductor process component described above.
Optionally, the semiconductor process component is an electrostatic chuck.
Optionally, the semiconductor process component is a heating electrode.
Optionally, the semiconductor process component is a radio frequency electrode.
Optionally, the semiconductor process component is a dc bias electrode.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the method for forming the semiconductor process component provided by the technical scheme of the invention, the semiconductor process component is formed by bonding the first substrate and the second substrate. The process steps performed on the first substrate and the process steps performed on the second substrate can be performed separately and simultaneously before the first bonding process is performed on the first substrate toward the second substrate, so that the process time can be saved. And the first bonding treatment process is simple to operate and easy to realize, and is favorable for saving cost.
Further, the material of the first dielectric layer comprises: silicon oxide or silicon nitride, the material of the second dielectric layer includes: silicon oxide or silicon nitride. The silicon oxide or silicon nitride material is low in cost and easy to obtain, so that the manufacturing cost is reduced. And moreover, silicon oxide or silicon nitride materials are used for bonding, so that the first dielectric layer and the second dielectric layer can be tightly combined, and the bonding effect is facilitated.
Further, activation treatment is respectively carried out on the surface of the first medium layer and the surface of the second medium layer, and the covalent bonds on the surface of the first medium layer and the surface of the second medium layer are fully opened through the activation treatment, so that the quality of the first bonding treatment is facilitated, namely more covalent bonds are formed between the surface of the first medium layer and the surface of the second medium layer, the tightness between the surface of the first medium layer and the surface of the second medium layer is better, and the performance of the formed semiconductor process component is better.
Furthermore, the roughness of the surface of the first medium layer is 0-1 micron, the roughness of the surface of the second medium layer is 0-1 micron, the roughness of the surface of the first medium layer and the roughness of the surface of the second medium layer are smaller, so that the surface of the first medium layer and the surface of the second medium layer can be more tightly attached together, a covalent bond can be fully formed between the surface of the first medium layer and the surface of the second medium layer in subsequent annealing treatment, the bonding effect is improved, and the performance of the formed semiconductor process component is better.
Drawings
Fig. 1-15 are schematic structural views of steps of a method for forming a semiconductor process element according to an embodiment of the invention.
Detailed Description
As described in the background, the conventional process for preparing semiconductor process components with electrostatic adsorption is complicated and expensive.
To solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor process component, including: providing a first substrate; forming a first groove in the first substrate; forming a first conductive layer in the first groove; forming a first dielectric layer on the first conductive layer and the first substrate; providing a second substrate; and carrying out first bonding treatment on the first substrate towards the second substrate, wherein the first dielectric layer is positioned between the first substrate and the second substrate. The preparation method has simple steps and can save the manufacturing cost.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1-15 are schematic structural views of steps of a method for forming a semiconductor process element according to an embodiment of the invention.
Referring to fig. 1, a first substrate 200 is provided.
The first substrate 200 may be made of various materials according to various requirements required for semiconductor process components. In this case, the polycrystalline ceramic sintered body is preferable in view of thermal conductivity and reliability of electrical insulation. The material of the first substrate 200 may be aluminum oxide, aluminum nitride, yttrium oxide, or silicon carbide.
The content range of the alumina, the aluminum nitride, the yttrium oxide or the silicon carbide is 94 to 99.99 weight percent. The first substrate 200 is formed of a material having a high purity, which has a high insulating property on one hand, and is beneficial to reducing contamination to other components on the other hand, thereby improving the performance of the formed semiconductor process components.
It should be noted that wt% means a percentage (%) by weight.
In this embodiment, the material of the first substrate 200 is alumina with a content of 99.99 wt%.
The thickness of the first substrate 200 ranges from 0.5 mm to 5 mm.
The significance of selecting said thickness range is: if the thickness is less than 0.5 mm, on one hand, the mechanical strength is not good, and the formed semiconductor process part is easy to be damaged; on the other hand, it is not favorable for generating sufficient electrostatic adsorption force or for ensuring higher heating efficiency; if the thickness is larger than 5 mm, the cost is easily wasted.
Referring to fig. 2 and 3, fig. 2 is a schematic cross-sectional view taken along a direction of a tangent M-N in fig. 3, and fig. 3 is a top view taken along a direction Y in fig. 2, wherein a first trench 210 is formed in the first substrate 200.
The first trench 210 is used for subsequent filling with a conductive material to form a first conductive layer.
The projection pattern of the first trench 210 on the surface of the first substrate 200 includes: one or more spirals, one or more nets, or one or more sheets.
In this embodiment, the projection pattern of the first groove 210 on the surface of the first substrate 200 is a spiral.
In this embodiment, the spiral shape is a circular shape. In other embodiments, the spiral may also be non-circular, e.g., elliptical.
The method for forming the first trench 210 includes: providing a first mask (not shown in the figure), wherein the first mask is provided with a mask opening (not shown in the figure) penetrating through the first mask, and the position of the mask opening corresponds to the position and the size of the first trench 210; a first mask is placed on the first substrate 200, and the first substrate 200 is subjected to sand blasting, so that the first trench 210 is formed in the first substrate 200.
The first mask 211 is made of metal.
The sandblasting process is to selectively remove a part of the material of the first substrate 200 by using the impact force of the high-speed sand flow.
Then, a first conductive layer is formed in the first trench. Please refer to fig. 4 to 5 for a process of forming the first conductive layer.
Referring to fig. 4, fig. 4 is a schematic view based on fig. 2, wherein a first conductive material film 220 is formed in the first trench 210 and on the surface of the first substrate 200.
The material of the first conductive material film 220 includes: one or more of molybdenum, tungsten, copper, nickel, aluminum or chromium.
The process of forming the first conductive material film 220 includes: a physical vapor deposition process or an electroplating process.
In the present embodiment, the process of forming the first conductive material film 220 is a physical vapor deposition process.
Referring to fig. 5, the first conductive material film 220 is planarized until the surface of the first substrate 200 is exposed, and the first conductive layer 230 is formed in the first trench 210.
The method of planarizing the first conductive material film 220 includes: and (5) carrying out a chemical mechanical polishing process.
Next, a first dielectric layer is formed on the first conductive layer and the first substrate, and please refer to fig. 6 to fig. 7 for a process of forming the first dielectric layer.
Referring to fig. 6, a first dielectric material film 240 is formed on the surface of the first conductive layer 230 and the surface of the first substrate 200.
The first dielectric material film 240 is used to provide a material for the subsequent formation of a first dielectric layer.
The materials of the first medium material film 240 include: silicon oxide or silicon nitride.
In this embodiment, the material of the first dielectric material film 240 is silicon oxide.
The silicon oxide or silicon nitride material is low in cost and easy to obtain, so that the manufacturing cost is reduced. And moreover, silicon oxide or silicon nitride materials are used for bonding, so that the first dielectric layer and the second dielectric layer which are formed subsequently can be tightly combined, and the bonding effect is facilitated.
The process of forming the first dielectric material film 240 includes: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In this embodiment, the process of forming the first dielectric material film 240 is a chemical vapor deposition process.
Referring to fig. 7, the first dielectric material film 240 is planarized, and the first dielectric layer 250 is formed on the surface of the first conductive layer 230 and the surface of the first substrate 200.
Since the first dielectric layer 250 is formed by planarizing the first dielectric material film 240. In this embodiment, the material of the first dielectric layer 250 is silicon oxide.
The roughness of the surface of the first dielectric layer 250 ranges from 0 micron to 1 micron.
The surface roughness of the first dielectric layer 250 is small, so that the surface of the first dielectric layer 250 and the surface of a subsequently formed second dielectric layer can be attached together more tightly, and during subsequent annealing treatment, covalent bonds can be formed between the surface of the first dielectric layer 250 and the surface of the second dielectric layer sufficiently, so that the bonding effect is improved, and the performance of the formed semiconductor process component is good.
The process of planarizing the first dielectric material film 240 includes: and (5) carrying out a chemical mechanical polishing process.
Referring to fig. 8, a second substrate 300 is provided.
The second substrate 300 may be made of various materials according to various requirements required for semiconductor process components. In this case, the polycrystalline ceramic sintered body is preferable in view of thermal conductivity and reliability of electrical insulation. The material of the second substrate 300 may be aluminum oxide, aluminum nitride, yttrium oxide, or silicon carbide.
In this embodiment, the material of the second substrate 300 is alumina with a content of 99.99 wt%.
The thickness of the second substrate 300 ranges from 0.2 mm to 1 mm.
The significance of selecting said thickness range is: if the thickness is less than 0.2 mm, on one hand, the mechanical strength is not good, and the formed semiconductor process part is easy to be damaged; on the other hand, it is not favorable for generating sufficient electrostatic adsorption force or for ensuring higher heating efficiency; if the thickness is larger than 1 mm, the cost is easily wasted.
Next, a second dielectric layer is formed on the surface of the second substrate, and please refer to fig. 9 to fig. 10 for a process of forming the second dielectric layer.
Referring to fig. 9, a second dielectric material film 310 is formed on the surface of the second substrate 300.
The second dielectric material film 310 is used for providing materials for the subsequent formation of a second dielectric layer.
The material of the second medium material film 310 includes: silicon oxide or silicon nitride.
The silicon oxide or silicon nitride material is low in cost and easy to obtain, so that the manufacturing cost is reduced. And moreover, silicon oxide or silicon nitride materials are used for bonding, so that the first dielectric layer and the second dielectric layer which are formed subsequently can be tightly combined, and the bonding effect is facilitated.
In this embodiment, the material of the second dielectric material film 310 is silicon oxide.
The process of forming the second dielectric material film 310 includes: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In the present embodiment, the process of forming the second dielectric material film 310 is a chemical vapor deposition process.
Referring to fig. 10, a second dielectric material film 310 is planarized, and the second dielectric layer 320 is formed on the surface of the second substrate 300.
Since the second dielectric layer 320 is formed by planarizing the second dielectric material film 310. In this embodiment, the second dielectric layer 320 is made of silicon oxide.
The roughness of the surface of the second dielectric layer 320 ranges from 0 micron to 1 micron.
The surface roughness of the second dielectric layer 320 is small, which is beneficial to enabling the surface of the first dielectric layer 250 and the surface of the second dielectric layer 320 to be tightly attached together, so that in the subsequent annealing treatment, covalent bonds are fully formed between the surface of the first dielectric layer 250 and the surface of the second dielectric layer 320, the bonding effect is improved, and the performance of the formed semiconductor process part is good.
The process of planarizing the second dielectric material film 310 includes: and (5) carrying out a chemical mechanical polishing process.
And after the first dielectric layer and the second dielectric layer are formed, carrying out activation treatment on the surface of the first dielectric layer and the surface of the second dielectric layer. Please refer to fig. 11 to 12 for a specific process of performing the activation process.
Referring to fig. 11, the surface of the first dielectric layer 250 and the surface of the second dielectric layer 320 are first cleaned by using diluted hydrofluoric acid or a diluted hydrofluoric acid and ammonium fluoride mixed solution.
In this embodiment, the surface of the first dielectric layer 250 and the surface of the second substrate layer 320 are treated with diluted hydrofluoric acid.
Referring to fig. 12, after the first cleaning process, a second cleaning process is performed on the surface of the first dielectric layer 250 and the surface of the second dielectric layer 320 by using deionized water.
The surface of the first dielectric layer 250 and the surface of the second dielectric layer 320 are respectively subjected to activation treatment, and the covalent bonds on the surface of the first dielectric layer 250 and the surface of the second dielectric layer 320 are fully opened by the activation treatment, so that the quality of subsequent first bonding treatment is facilitated, namely, more covalent bonds are formed between the surface of the first dielectric layer 250 and the surface of the second dielectric layer 320, the tightness between the surface of the first dielectric layer 250 and the surface of the second dielectric layer 320 is better, and the performance of the formed semiconductor process part is better.
In other embodiments, the method of activation processing includes: and carrying out plasma treatment on the surface of the first dielectric layer and the surface of the second dielectric layer.
And after the activation treatment, carrying out first bonding treatment on the first substrate towards the second substrate, wherein the first dielectric layer is positioned between the first substrate and the second substrate.
Referring to fig. 13, after the activation process, a first bonding process is performed on the first dielectric layer 250 toward the second dielectric layer 320.
The method of the first bonding process includes: extruding and attaching the surface of the first dielectric layer 250 to the surface 320 of the second dielectric layer; after the surface of the first dielectric layer 250 is pressed and attached to the surface of the second dielectric layer 320, annealing treatment is performed on the first dielectric layer 250 and the second dielectric layer 320, so that the surface of the first dielectric layer 250 and the surface of the second dielectric layer 320 are bonded.
The bonding between the first substrate 200 and the second substrate 300 is performed by performing a first bonding process with the first dielectric layer 250 facing the second dielectric layer 320. Since the process steps performed on the first substrate 200 and the process steps performed on the second substrate 300 can be performed separately and simultaneously before the first bonding process is performed on the first substrate 200 toward the second substrate 300, the process time can be saved. And the first bonding treatment process is simple to operate and easy to realize, and is favorable for saving cost.
The parameters of the annealing treatment comprise: the temperature range is 200-1500 ℃, and the treatment time is 0.5-24 hours.
It should be noted that the treatment time is related to the annealing temperature, i.e., the annealing treatment time is correspondingly decreased when the annealing temperature is higher, and the annealing treatment time is correspondingly increased when the annealing temperature is lower.
In this embodiment, after the first bonding process is performed on the first substrate toward the second substrate, the method further includes: the stacking process is performed more than once.
Referring to fig. 14, a third substrate 400 is provided, the third substrate having a second trench (not shown) therein and a second conductive layer 410 located in the second trench, and a third dielectric layer 420 is disposed on the second conductive layer 410 and the third substrate 400.
The material of the third substrate 400 can refer to the first substrate 200, and is not described herein again.
The forming method of the second trench is the same as that of the first trench 210, and is not described herein again.
The material and the forming method of the second conductive layer 410 are the same as those of the first conductive layer 230, and are not described herein again.
The material and the forming method of the third dielectric layer 420 are the same as those of the first dielectric layer 250, and are not described herein again.
Referring to fig. 15, a second bonding process is performed on the third dielectric layer 420 toward the first substrate 200.
Specifically, the third dielectric layer 420 is subjected to a second bonding process towards a surface of the first substrate 200 opposite to the first dielectric layer 250.
In the present embodiment, the stacking process is performed once.
In another embodiment, more than one stacking process may also be performed.
In yet another embodiment, the stacking process may not be performed.
By performing the stacking process more than once, the performance of the formed semiconductor process component can be improved, thereby meeting the actual process requirements.
Correspondingly, the embodiment of the invention also provides a semiconductor process part formed by adopting the method.
Correspondingly, an embodiment of the present invention further provides a semiconductor processing apparatus, including: the semiconductor process component described above.
In this embodiment, the semiconductor process component is an electrostatic chuck.
In one embodiment, the semiconductor process component is a heater electrode.
In another embodiment, the semiconductor process component may also be a radio frequency electrode.
In yet another embodiment, the semiconductor process component may also be a dc bias electrode.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (26)

1. A method of forming a semiconductor process component, comprising:
providing a first substrate;
forming a first groove in the first substrate;
forming a first conductive layer in the first groove;
forming a first dielectric layer on the first conductive layer and the first substrate;
providing a second substrate;
and carrying out first bonding treatment on the first substrate towards the second substrate, wherein the first dielectric layer is positioned between the first substrate and the second substrate.
2. The method of forming a semiconductor process component of claim 1, further comprising: before the first substrate faces a second substrate and is subjected to first bonding treatment, a second dielectric layer is formed on the surface of the second substrate; and carrying out first bonding treatment on the first dielectric layer towards the second dielectric layer.
3. The method of forming a semiconductor process component of claim 1, wherein the material of the first substrate comprises: aluminum oxide or aluminum nitride; the material of the second substrate includes: alumina or aluminum nitride.
4. The method of forming a semiconductor process feature of claim 1, wherein the material of the first dielectric layer comprises: silicon oxide or silicon nitride.
5. The method of forming a semiconductor process feature of claim 2, wherein the material of the second dielectric layer comprises: silicon oxide or silicon nitride.
6. The method of forming a semiconductor process component of claim 1, wherein the material of the first conductive layer comprises: one or more of molybdenum, tungsten, copper, nickel, aluminum or chromium.
7. The method of forming a semiconductor process component of claim 1, wherein the surface roughness of the first dielectric layer ranges from 0 microns to 1 micron.
8. The method of forming a semiconductor process component of claim 2, wherein the surface roughness of the second dielectric layer ranges from 0 microns to 1 micron.
9. The method of forming a semiconductor process feature of claim 1, wherein the method of forming the first trench comprises: providing a first mask plate, wherein a mask opening penetrating through the first mask plate is formed in the first mask plate, and the position of the mask opening corresponds to the position and the size of the first groove; and placing a first mask on a first substrate, carrying out sand blasting treatment on the first substrate, and forming the first groove in the first substrate.
10. The method of forming a semiconductor process component of claim 1, wherein the method of forming the first conductive layer comprises: forming a first conductive material film in the first groove and on the surface of the first substrate; and flattening the first conductive material film until the surface of the first substrate is exposed, and forming the first conductive layer in the first groove.
11. The method of forming a semiconductor process feature of claim 1, wherein the method of forming the first dielectric layer comprises: forming a first dielectric material film on the surface of the first conductive layer and the surface of the first substrate; and flattening the first dielectric material film, and forming the first dielectric layer on the surface of the first conductive layer and the surface of the first substrate.
12. The method of forming a semiconductor process feature of claim 2, wherein the method of forming the second dielectric layer comprises: forming a second dielectric material film on the surface of the second substrate; and flattening the second medium material film, and forming the second medium layer on the surface of the second substrate.
13. The method of forming a semiconductor process component of claim 2, further comprising: after a first dielectric layer and a second dielectric layer are formed and before the first bonding treatment, carrying out activation treatment on the surface of the first dielectric layer and the surface of the second dielectric layer; and after the activation treatment, carrying out first bonding treatment on the surface of the first dielectric layer facing the surface of the second dielectric layer.
14. The method of forming a semiconductor process component of claim 13, wherein the method of activating comprises: carrying out first cleaning on the surface of the first dielectric layer and the surface of the second dielectric layer by using diluted hydrofluoric acid or a mixed solution of diluted hydrofluoric acid and ammonium fluoride; and after the first cleaning treatment, carrying out second cleaning on the surface of the first medium layer and the surface of the second medium layer by using deionized water.
15. The method of forming a semiconductor process component of claim 13, wherein the method of activating comprises: and carrying out plasma treatment on the surface of the first dielectric layer and the surface of the second dielectric layer.
16. The method of forming a semiconductor process component of claim 2, wherein the first bonding process method comprises: extruding and attaching the surface of the first dielectric layer to the surface of the second dielectric layer; and after the surface of the first dielectric layer faces the surface of the second dielectric layer and is extruded and attached, annealing treatment is carried out on the first dielectric layer and the second dielectric layer, so that the surface of the first dielectric layer is bonded with the surface of the second dielectric layer.
17. The method of forming a semiconductor process component of claim 1, wherein the first substrate has a thickness in a range of 0.5 mm to 5 mm.
18. The method of forming a semiconductor process component of claim 1, wherein the second substrate has a thickness in a range of 0.2 mm to 1 mm.
19. The method of forming a semiconductor process component of claim 1, wherein the projected pattern of the first trench on the first substrate surface comprises: one or more spirals, one or more nets, or one or more sheets.
20. The method of forming a semiconductor process component of claim 1 or 2, further comprising: performing more than one stacking process after performing first bonding treatment on the first substrate towards the second substrate; each stacking process comprises the following steps: providing a third substrate, wherein the third substrate is internally provided with a second groove and a second conducting layer positioned in the second groove, and third dielectric layers are arranged on the second conducting layer and the third substrate; and carrying out second bonding treatment on the third dielectric layer towards the first substrate.
21. A semiconductor process component formed using the method of any of claims 1 to 20.
22. A semiconductor processing apparatus, comprising:
the semiconductor process component of claim 21.
23. The semiconductor processing apparatus of claim 22, wherein the semiconductor processing component is an electrostatic chuck.
24. The semiconductor processing apparatus of claim 22, wherein the semiconductor processing component is a heater electrode.
25. The semiconductor processing apparatus of claim 22, wherein the semiconductor processing component is a radio frequency electrode.
26. The semiconductor processing apparatus of claim 22, wherein the semiconductor processing component is a dc bias electrode.
CN201910973045.XA 2019-10-14 2019-10-14 Semiconductor process component, method of forming the same, and semiconductor process apparatus Pending CN110676164A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1860590A (en) * 2003-05-19 2006-11-08 齐普特洛尼克斯公司 Method of room temperature covalent bonding
CN102742004A (en) * 2010-02-04 2012-10-17 索泰克公司 Bonded semiconductor structures and methods of forming same
CN109671619A (en) * 2018-12-26 2019-04-23 上海集成电路研发中心有限公司 A kind of method that wafer scale is hybrid bonded
JP6583897B1 (en) * 2018-05-25 2019-10-02 ▲らん▼海精研股▲ふん▼有限公司 Method for manufacturing ceramic electrostatic chuck

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1860590A (en) * 2003-05-19 2006-11-08 齐普特洛尼克斯公司 Method of room temperature covalent bonding
CN102742004A (en) * 2010-02-04 2012-10-17 索泰克公司 Bonded semiconductor structures and methods of forming same
JP6583897B1 (en) * 2018-05-25 2019-10-02 ▲らん▼海精研股▲ふん▼有限公司 Method for manufacturing ceramic electrostatic chuck
CN109671619A (en) * 2018-12-26 2019-04-23 上海集成电路研发中心有限公司 A kind of method that wafer scale is hybrid bonded

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