CN110660818A

CN110660818A - Method of manufacturing image sensor

Info

Publication number: CN110660818A
Application number: CN201910956077.9A
Authority: CN
Inventors: 北村阳介
Original assignee: Huaian Imaging Device Manufacturer Corp
Current assignee: Huaian Imaging Device Manufacturer Corp
Priority date: 2019-10-10
Filing date: 2019-10-10
Publication date: 2020-01-07

Abstract

The present disclosure relates to a method of manufacturing an image sensor. There is provided a method of manufacturing an image sensor, the method including: providing a substrate, wherein the substrate comprises a photosensitive unit array; forming a first material layer on a substrate, the first material layer including a first portion disposed corresponding to the array of photosensitive cells and a second portion adjacent to the first portion; removing the second portion of the first material layer to form a plurality of trenches in the first material layer; forming a second material layer overlying the first portion of the first material layer and overlying sidewalls and a bottom of each of the plurality of trenches; forming a metal layer covering the second material layer and filling each of the plurality of trenches; removing a portion of the metal layer and a portion of the second material layer to leave the second material layer and the metal layer in each of a plurality of trenches; removing a first portion of the first material layer to form a plurality of first openings.

Description

Method of manufacturing image sensor

Technical Field

The present disclosure relates generally to the field of imaging, and more particularly, to methods of fabricating image sensing.

Background

Many modern electronic devices involve electronic devices that use image sensors, such as single-lens reflex cameras, general digital cameras, video cameras, cell phones, automotive electronics, and the like. Conventional image sensors may be fabricated from Complementary Metal Oxide Semiconductor (CMOS) technology or Charge Coupled Device (CCD) technology. A typical image sensor operates such that light is incident on a microlens, which focuses the light onto a photosensitive cell through a filter. The light sensing unit converts light into an electrical signal proportional to the intensity of incident light. In an image sensor, electrical signals in the photosites are coupled to amplification and readout circuitry (e.g., CMOS transistors) to generate an image based on light captured in the photosites.

Standard IC fabrication processes can use front side ("FSI") and back side ("BSI") image sensors. In the FSI image sensor, a metal layer is disposed between a microlens and a photosensitive cell. During the manufacture of image sensors using FSI technology, channels are thus created through the metal layer for light to travel from the microlenses to the photosensitive cells. However, in the FSI image sensor, light passing through the channel to the light sensing unit is attenuated, thereby causing a decrease in quantum efficiency of the light sensing unit and a decrease in sensitivity of the image sensor. Furthermore, internal reflection of light at the interface between different materials in an FSI image sensor can cause back emission, which in turn can exit from the bottom side of the metal layer to be reflected into adjacent photosites, causing optical crosstalk.

In an image sensor using BSI, a metal layer, a polysilicon layer, a diffusion layer are located on one side of a substrate and a light sensing unit is exposed to light from the other side of the substrate. Therefore, it is not necessary to create a path through the metal stack to the photosensitive unit. However, BSI image sensors may also have crosstalk between pixel cells.

Accordingly, there is a continuing need in the art for image sensors with improved pixel cell isolation.

Disclosure of Invention

An object of the present disclosure is to provide a method of manufacturing an image sensor and an electronic device.

According to an aspect of the present disclosure, there is provided a method of manufacturing an image sensor, the method including: providing a substrate, wherein the substrate comprises a photosensitive unit array; forming a first material layer on the substrate, the first material layer including a first portion disposed corresponding to the array of photosensitive cells and a second portion adjacent to the first portion; removing a second portion of the first material layer to form a plurality of trenches in the first material layer; forming a second layer of material overlying a first portion of the first layer of material and overlying sidewalls and a bottom of each of the plurality of trenches; forming a metal layer covering the second material layer and filling each of the plurality of trenches; removing a portion of the metal layer and a portion of the second material layer to leave the second material layer and the metal layer in each of the plurality of trenches; removing a first portion of the first material layer to form a plurality of first openings.

According to another aspect of the present disclosure, there is provided a method of manufacturing an electronic device, the method comprising manufacturing an image sensor using the method as described above.

Other features of the present disclosure and advantages thereof will become more apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:

fig. 1 shows a flow diagram for fabricating an image sensor according to one or more exemplary embodiments of the present disclosure;

fig. 2-11 respectively show schematic cross-sectional views at various steps of fabricating an image sensor according to one or more exemplary embodiments of the present disclosure.

Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In some cases, similar reference numbers and letters are used to denote similar items, and thus, once an item is defined in one figure, it need not be discussed further in subsequent figures.

For convenience of understanding, the positions, sizes, ranges, and the like of the respective structures shown in the drawings and the like do not sometimes indicate actual positions, sizes, ranges, and the like. Therefore, the present disclosure is not limited to the positions, dimensions, ranges, and the like disclosed in the drawings and the like.

Detailed Description

Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these exemplary embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. That is, the structures and methods herein are shown by way of example to illustrate different exemplary embodiments of the structures and methods of the present disclosure. Those skilled in the art will understand, however, that they are merely illustrative of exemplary ways in which the disclosure may be practiced and not exhaustive. Furthermore, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

Some exemplary embodiments of the invention are described with reference to semiconductor layers and/or regions, which are characterized as having a conductivity type, e.g., n-type or p-type, which relates to the majority carrier concentration in the layer and/or region. Thus, n-type material has a majority equilibrium concentration of negatively charged electrons, while p-type material has a majority equilibrium concentration of positively charged holes. Some materials may be designated with "+" or "-" (e.g., n +, n-, p +, p-, n + +, n-, p + +, p-, or the like) to indicate a relatively larger ("+") or smaller ("-") concentration of majority carriers as compared to another layer or region. However, this notation does not imply the presence of a particular concentration of majority or minority carriers in a layer or region. Unless expressly stated to the contrary, the terms "carrier concentration" or "dopant concentration" when referring to a layer, film or region are intended to mean the average concentration of such layer, film or region.

Although the devices are explained herein as certain n-type regions and certain p-type regions, it will be understood by those of ordinary skill in the art that the conductivity types may be reversed and are also possible as described in the specification, taking into account any necessary potential polarity reversal, transistor type and/or current direction reversal, etc.

One challenge of BSI image sensors is crosstalk between adjacent pixel cells. As BSI image sensors become smaller, the distance between adjacent pixel cells becomes smaller, thereby increasing the likelihood of crosstalk. Cross talk can degrade the performance of the image sensor, increase noise, and reduce the signal generated by the image sensor. Accordingly, there is a continuing need in the art for image sensors with reduced crosstalk.

In BSI image sensors, uniformity of light received by each pixel cell and prevention of optical crosstalk are generally improved by disposing a Color Filter Isolation (CFI) structure between color filters in a color filter array. In general, crosstalk of light between different pixel cells is prevented by providing a louver, which is generally formed of a metal having an opaque property, as a CFI structure, and such a louver may also be referred to as a metal louver. There have been problems with this metal grid process. As the device is reduced, the area occupied by the metal grid affects the effective area of the pixel unit, and therefore, it is desirable that the area occupied by the metal grid is small and is made thin, that is, the aspect ratio of the metal grid is increased. Furthermore, it is desirable to provide a CFI structure with a high aspect ratio to improve the sensitivity of the pixel cell, i.e. low reflectivity/high sensitivity. But this becomes a technological challenge. On the one hand, the residual defect of the etching of the metal grid affects the light transmittance of the pixel unit, so that the imaging is not uniform, thereby affecting the performance of the image sensor. On the other hand, as the aspect ratio increases, etching of the metal grid becomes more difficult, and the metal grid is susceptible to a collapse phenomenon. In particular, conventional CFI processes have difficulties in both lithography and etching. In terms of photolithography, it is difficult to form a narrow and thick resist pattern to cover a metal layer where a CFI structure is to be formed. In the etching, when forming a metal grid with a high aspect ratio, the metal grid may have a shape that is wide at both ends and narrow at the middle (bending), which also makes the process of forming the metal grid difficult.

Accordingly, there is a continuing need in the art for improved metal grids. In view of the above, the present invention provides a technique to achieve high aspect ratio CFI structures through a metal filling process.

Fig. 1 shows a flow chart for manufacturing an image sensor according to one or more exemplary embodiments of the present disclosure. Fig. 2-11 respectively show schematic cross-sectional views at various steps of fabricating an image sensor according to one or more exemplary embodiments of the present disclosure. One example of a method of manufacturing an image sensor according to one or more embodiments will be described according to the flowchart in fig. 1 and with reference to the cross-sectional views in fig. 2 to 11.

In one embodiment, a substrate 10 is first provided, the substrate 10 including an array of photosensitive cells 100 (step S101 in fig. 1).

As shown in fig. 2, the substrate 10 may be a silicon substrate or other semiconductor material. Gallium arsenide, germanium, silicon carbide, indium arsenide or indium phosphide or alloy semiconductors such as silicon germanium carbide, indium gallium phosphide, indium gallium arsenide, or the like may be used. The substrate 10 may typically be a wafer of semiconductor material. In other embodiments, the substrate 10 may be provided as an epitaxial layer on an insulator, such as an "SOI" layer. A wafer of semiconductor material may be bonded or stacked and the substrate 10 may be one of these layers. The substrate 10 is typically thinned by a wafer grinding process, such as chemical mechanical polishing ("CMP"), mechanical wafer grinding, or semiconductor etching.

The photosensitive cell array 100 is formed in the substrate 10. Fig. 2 to 11 show schematic cross-sectional views of the photosensitive cell array 100 including three photosensitive cells, but those skilled in the art understand that the image sensor may include more photosensitive cells and other elements. The photosensitive cells in these arrays of photosensitive cells are typically arranged in rows and columns. The photosensitive cells in the photosensitive cell array 100 are, for example, photodiodes. For example, the photodiode may include a corresponding first region (not shown) within the substrate 10 having a first doping type (e.g., n-type doping), and a corresponding second region (not shown) over the first region within the substrate 10 having a second doping type (e.g., p-type doping) different from the first doping type. The first region and the second region form a pn junction. In a photodiode, electron-hole pairs are generated in a pn junction in response to photons incident at a particular wavelength and energy, and charge (e.g., electrons) from the photons incident on the photodiode are accumulated. Also, when a transfer transistor (not shown) is turned on, the electric charges accumulated in the photodiode are taken out.

Further, a DTI structure (not shown) may be provided between the photosensitive cells in the photosensitive cell array 100. The DTI structure extends from the surface of the substrate 10 to a location within the substrate 10 to electrically and/or optically isolate adjacent photosites. DTI structures are formed by forming deep trenches in the substrate 10 using an etching process, followed by filling the formed deep trenches with material. The deep trenches may be filled with a dielectric layer material, such as an oxide material, which may be a high dielectric constant material, to form DTI structures. DTI structures can also be formed by covering the sidewalls and bottom of deep trenches with a dielectric material and then filling the deep trenches with a metal material so that the DTI structures can be electrically isolated and prevent optical crosstalk. The DTI structure is disposed between adjacent photosensitive cells in the photosensitive cell array 100 and surrounds the photosensitive cells. In addition, other pixel transistors (not shown) such as a transfer transistor, a selection transistor, an amplification transistor, a reset transistor, and the like for each pixel unit are included in the substrate 10.

In addition to the exemplary structures described herein, the substrate 10 may include other devices, including active transistors, diodes, capacitors, resistors, memory cells, analog devices, filters, transceivers, etc., formed in another portion of the substrate 10. Moreover, after forming the image sensor of the present invention, an encapsulation material may be disposed over the substrate to form a complete microelectronic assembly, such as an integrated circuit, a solar cell, a processor, and the like.

In addition, the substrate 10 may also include additional layers (not shown) including back end of line (BEOL) metallization stacks. The BEOL metallization stack may include a plurality of metallization layers stacked within an interlayer dielectric layer. One or more contacts of the BEOL metallization stack extend from the metallization layer to the pixel sensor. Further, one or more vias of the BEOL metallization stack extend between the metallization layers to interconnect the metallization layers. The metal interconnect line may be a metal of aluminum, aluminum/silicon/copper alloy, titanium nitride, tantalum nitride, tungsten, polysilicon, metal silicide, or combinations thereof, wherein the metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof.

Next, a first material layer 101 is formed on the substrate 10, the first material layer 101 including a first portion 101 ' disposed corresponding to the photosensitive cell array 100 and a second portion 101 ' adjacent to the first portion 101 ' (step S102 in fig. 1).

In one embodiment, as shown in fig. 3, the first material layer 101 may be formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), sputtering, evaporation, or the like.

The first material layer 101 may also be referred to as a dummy layer for defining trenches in which a metal grid is to be formed and first openings in which a color filter array is to be formed. The first material layer 101 may be formed of a SiN layer. In one example, the thickness of the first material layer 101 may be 200nm to 500 nm.

In one example, a third material layer 102 may be formed on the substrate 10 prior to forming the first material layer 101. The third material layer 102 may be configured to have an etch selectivity with respect to the first material layer 101 to serve as an etch stop layer when forming the plurality of trenches and the plurality of first openings in a subsequent step. In one example, the third material layer 102 may be formed by chemical vapor deposition, and the third material layer 102 may be formed of SiO₂And (4) forming. In one example, the thickness of the third material layer 102 may be 10nm to 50 nm.

In one example, an anti-reflective layer (ARC)103 may be formed on the substrate 10 prior to forming the first material layer 101. The ARC103 may be formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), sputtering, evaporation, and the like. ARC103 is disposed over substrate 10 along a surface of substrate 10. The ARC103 may be a silicon nitride (SiN) layer, a tantalum oxide (TaO) layer, or a silicon oxynitride (SiON) layer, and the ARC103 may also be other anti-reflective coatings. In one particular example, the ARC103 may be formed of SiN and may have a thickness of 30nm to 80 nm.

Next, the second portion 101 ″ of the first material layer 101 is removed to form a plurality of trenches 105 in the first material layer 101 (step S103 in fig. 1).

In one embodiment, as shown in fig. 4, a resist pattern 104 is formed on the first material layer 101 by, for example, a photolithography process. The resist pattern 104 exposes the second portion 101 ″ of the first material layer 101 and covers the first portion 101' of the first material layer 101. The above photolithography process includes, for example, steps of coating a resist layer, soft baking, exposure, post-exposure baking, development to form the resist pattern 104, and the like.

Subsequently, as shown in fig. 5, by a dry etching method or the like, the second portion 101 ″ of the first material layer 101 exposed by the resist pattern 104 is removed and the first portion 101' of the first material layer 101 covered by the resist pattern 104 remains. Thereby forming a plurality of trenches 105 having a high aspect ratio. After that, the resist pattern 104 is removed.

Next, a second material layer 106 is formed, the second material layer 106 covering the first portion 101' of the first material layer 101 and covering the sidewalls and the bottom of each of the plurality of trenches 105 (step S104 in fig. 1).

As shown in fig. 6, a second material layer 106 may be deposited by a Chemical Vapor Deposition (CVD) method or the like, the second material layer 106 being deposited on the surface and sidewalls of the first portion 101' of the first material layer 101 and on the bottom of the plurality of trenches 105. Second material layer 106 may be configured to have an etch selectivity with respect to the first material layer 101. In one example, the second material layer 106 may be made of SiO₂And may have a thickness of 5nm to 100 nm. The second material layer 106 may also be referred to as a spacer layer, which is used to isolate the metal grid formed in a subsequent step from the color filter array formed in a subsequent step.

Next, a metal layer 107 is formed, the metal layer 107 covering the second material layer 106 and filling each of the plurality of trenches 105 (step S105 in fig. 1).

In one embodiment, as shown in fig. 7, for example, the metal layer 107 may be formed by sputtering, evaporation, plating, etc., such that the metal layer 107 is on the second material layer 106 and fills each of the plurality of trenches 105.

The metal layer 107 may be formed of tungsten. Tungsten may be filled in the trench 105. The metal layer 107 may also be formed of aluminum or copper. In one example, the thickness of metal layer 107 may be 50nm to 200 nm. In one example, as shown in fig. 7, in the case where the width of the trench 105 is determined, the width of the metal layer 107 filled in the plurality of trenches 105 may be controlled by the thickness of the second material layer 106.

Next, a portion of the metal layer 107 and a portion of the second material layer 106 are removed to leave the second material layer 106 and the metal layer 107 in each of the plurality of trenches 105 (step S106 in fig. 1).

In one embodiment, as shown in fig. 8, the excess second material layer 106 and the metal layer 107 overlying the first portion 101' of the first material layer 101 are removed, for example, by a Chemical Mechanical Polishing (CMP) process or a blanket etch, and the second material layer 106 and the metal layer 107 in the plurality of trenches 105 remain. The metal layer remaining in the plurality of trenches 105 may also be referred to as a metal grid or CFI structure. The width of the CFI structure may be controlled by the thickness of the second material layer 106. That is, if the thickness of the second material layer 106 is thicker, the width of the CFI structure will be narrower; and if the thickness of the second material layer 106 is thin, the width of the CFI structure will be wide.

Next, the first portion 101' of the first material layer 101 is removed to form a plurality of first openings 108 (step S107 in fig. 1).

As the process advances, the size of the image sensor becomes smaller and the width of the grid becomes smaller, and thus in the case where the second material layer 106 and the metal layer 107 remaining in the trench 105 are covered with the resist pattern using the photolithography process and the first portion 101 'of the first material layer 101 is exposed to remove the first portion 101' of the first material layer 101, an exposure technique with sufficient accuracy is required for alignment. Furthermore, since the thickness of the first material layer 101 is relatively thick, in the process of removing the first portion 101' of the first material layer 101 using the photolithography process, it is necessary to form a resist pattern thick and narrow enough to cover the second material layer 106 and the metal layer 107 remaining in the trench 105, which also presents a challenge to sufficient exposure of the resist layer. Therefore, in a preferred embodiment, as shown in fig. 9, the first portion 101' of the first material layer 101 is removed by wet etching, not by a photolithography process, but by using the etch selectivity of the first material layer 101 and the second material layer 106, by selecting appropriate etch conditions (i.e., the etch rate of the first material layer 101 is greater than the etch rate of the second material layer 106).

With this embodiment, since the first material layer 101' of the first material layer 101 is directly wet-etched without using a photolithography process, process steps are reduced. Furthermore, the direct wet etching of the first portion 101' of the first material layer 101 without using a photolithography process reduces the requirements for exposure techniques and devices, thereby reducing process difficulties.

Further, in one embodiment, since the first material layer 101 and the third material layer 102 are configured to have an etching selectivity, in one example, the etching process is performed by wet etching by using an etching condition having an etching selectivity to the first material layer 101 with respect to the third material layer 102 (i.e., the etching rate of the first material layer 101 is greater than that of the third material layer 102). Through the etching process, the third material layer 102 serves as an etch stop layer for forming the plurality of first openings 108. Thereby forming a plurality of first openings 108 exposing a portion of the surface of the third material layer 102.

Next, in one embodiment, as shown in fig. 10, a color filter array 109 is formed in the plurality of first openings 108. The color filter array 109 may include red, green, and blue color filters, of course, the color filter array 109 may have other color filters as desired and may have any other suitable arrangement as desired. Color filters of different colors can be formed by a multi-step photolithography step. The color filter array 109 may include a colored or tinted material, such as acrylic. For example, polymethylmethacrylate ("PMMA") or propylene glycol monostearate ("PGMS") are suitable materials that can be used to add pigments or dyes to form color filters. However, other materials may also be used.

The upper surface of the color filter array 109 may be lower than, higher than, or equal to the upper surface of the metal layer 107 as a metal grid. Therefore, after the color filter array 109 is formed, the upper surface of the color filter array 109 may be planarized by forming a planarization layer, chemical mechanical polishing the planarization layer, or the like.

Next, in one embodiment, as shown in fig. 11, a microlens array 110 is formed on the color filter array 109. The microlens array 110 may be made of a transparent organic material, an inorganic compound material, and has a convex upper surface. The microlens array 110 may be centered on the center of the array of photosensitive cells 100 or slightly offset. The microlens array 110 may be formed on the top of the light sensing unit array 100 (assuming that the top is a position where incident light first arrives) to correspond to the photodiodes in the light sensing unit array 100. The microlens array 110 may be used to increase light condensing power, thereby improving image quality.

In this way, an image sensor according to one or more embodiments is manufactured. With the CFI structure thus fabricated, crosstalk of light to adjacent light-sensing units can be further reduced or eliminated, and more light can be collected to a target light-sensing unit. Thus, the light-entering amount of the target photosensitive unit can also be increased, thereby improving the image quality. In addition, the formation of the metal grid CFI structure through a metal filling process may overcome problems in forming a metal grid using photolithography and etching processes, whereby a high aspect ratio metal grid CFI structure may be realized.

The terms "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the exemplary embodiments of the disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

As used herein, the word "exemplary" means "serving as an example, instance, or illustration," and not as a "model" that is to be replicated accurately. Any implementation exemplarily described herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the disclosure is not limited by any expressed or implied theory presented in the preceding technical field, background, brief summary or the detailed description.

As used herein, the term "substantially" is intended to encompass any minor variation resulting from design or manufacturing imperfections, device or component tolerances, environmental influences, and/or other factors. The word "substantially" also allows for differences from a perfect or ideal situation due to parasitics, noise, and other practical considerations that may exist in a practical implementation.

In addition, the foregoing description may refer to elements or nodes or features being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/node/feature is directly connected to (or directly communicates with) another element/node/feature, either electrically, mechanically, logically, or otherwise. Similarly, unless expressly stated otherwise, "coupled" means that one element/node/feature may be mechanically, electrically, logically, or otherwise joined to another element/node/feature in a direct or indirect manner to allow for interaction, even though the two features may not be directly connected. That is, to "couple" is intended to include both direct and indirect joining of elements or other features, including connection with one or more intermediate elements.

In addition, "first," "second," and like terms may also be used herein for reference purposes only, and thus are not intended to be limiting. For example, the terms "first," "second," and other such numerical terms referring to structures or elements do not imply a sequence or order unless clearly indicated by the context.

It will be further understood that the terms "comprises/comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

In the present disclosure, the term "providing" is used broadly to encompass all ways of obtaining an object, and thus "providing an object" includes, but is not limited to, "purchasing," "preparing/manufacturing," "arranging/setting," "installing/assembling," and/or "ordering" the object, and the like.

Those skilled in the art will appreciate that the boundaries between the above described operations merely illustrative. Multiple operations may be combined into a single operation, single operations may be distributed in additional operations, and operations may be performed at least partially overlapping in time. Moreover, alternative exemplary embodiments may include multiple instances of a particular operation, and the order of operations may be altered in other various exemplary embodiments. However, other modifications, variations, and alternatives are also possible. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

In addition, embodiments of the present disclosure may also include the following examples:

item 1. a method of manufacturing an image sensor, the method comprising:

providing a substrate, wherein the substrate comprises a photosensitive unit array;

forming a first material layer on the substrate, the first material layer including a first portion disposed corresponding to the array of photosensitive cells and a second portion adjacent to the first portion;

removing a second portion of the first material layer to form a plurality of trenches in the first material layer;

forming a second layer of material overlying a first portion of the first layer of material and overlying sidewalls and a bottom of each of the plurality of trenches;

forming a metal layer covering the second material layer and filling each of the plurality of trenches;

removing a portion of the metal layer and a portion of the second material layer to leave the second material layer and the metal layer in each of the plurality of trenches;

removing a first portion of the first material layer to form a plurality of first openings.

Item 2. the method of item 1, wherein the second portion of the first material layer is removed by dry etching to form a plurality of trenches in the first material layer.

Item 3. the method of item 1, wherein a portion of the metal layer and a portion of the second material layer are removed by a chemical mechanical polishing process to leave the second material layer and the metal layer in each of the plurality of trenches.

Item 4. the method of item 1, wherein the first material layer and the second material layer are configured to have an etch selectivity, wherein a first portion of the first material layer is removed by wet etching to form a plurality of first openings.

Item 5. the method of item 1, wherein the method further comprises forming a third material layer on the substrate prior to forming the first material layer, the third material layer configured to have an etch selectivity relative to the first material layer and to act as an etch stop layer for forming the plurality of trenches.

Item 6. the method of item 4, wherein the first material layer is formed of SiN and the second material layer is formed of SiO₂And (4) forming.

Item 7 the method of item 5, wherein the third material layer is formed of SiO₂And (4) forming.

Item 8. the method of item 1, wherein the metal layer is formed from any of tungsten, aluminum, or copper.

Item 9. the method of item 1, wherein the method further comprises forming an antireflective layer on the substrate prior to forming the first material layer.

Item 10. a method of manufacturing an electronic device, the method comprising manufacturing an image sensor using the method of any one of items 1 to 9.

Although some specific exemplary embodiments of the present disclosure have been described in detail by way of illustration, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. The various exemplary embodiments disclosed herein may be combined in any combination without departing from the spirit and scope of the present disclosure. Those skilled in the art will also appreciate that various modifications may be made to the exemplary embodiments without departing from the scope and spirit of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A method of manufacturing an image sensor, the method comprising:

2. The method of claim 1, wherein the second portion of the first material layer is removed by dry etching to form a plurality of trenches in the first material layer.

3. The method of claim 1, wherein a portion of the metal layer and a portion of the second material layer are removed by a chemical mechanical polishing process to leave the second material layer and the metal layer in each of the plurality of trenches.

4. The method of claim 1, wherein the first material layer and the second material layer are configured to have an etch selectivity, wherein a first portion of the first material layer is removed by wet etching to form a plurality of first openings.

5. The method of claim 1, further comprising forming a third material layer on the substrate prior to forming the first material layer, the third material layer configured to have an etch selectivity relative to the first material layer and to act as an etch stop layer for forming the plurality of trenches.

6. The method of claim 4, wherein the first layer of material is formed fromSiN, and the second material layer is made of SiO₂And (4) forming.

7. The method of claim 5, wherein the third material layer is formed of SiO₂And (4) forming.

8. The method of claim 1, wherein the metal layer is formed of any of tungsten, aluminum, or copper.

9. The method of claim 1, further comprising forming an anti-reflective layer on the substrate prior to forming the first material layer.

10. A method of manufacturing an electronic device, the method comprising manufacturing an image sensor using the method of any of claims 1 to 9.