CN110660640A

CN110660640A - Method for forming semiconductor structure

Info

Publication number: CN110660640A
Application number: CN201910565992.5A
Authority: CN
Inventors: 彭羽筠
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-06-29
Filing date: 2019-06-27
Publication date: 2020-01-07

Abstract

Dielectric material compositions and related methods are provided herein. A method of forming a semiconductor structure includes patterning a substrate to form a first structure, a second structure adjacent to the first structure, and a trench between the first and second structures. The method also includes depositing a dielectric material over the first structure and in the trench. In some embodiments, the step of depositing the dielectric material comprises: a first precursor, a second precursor, and a reactant gas are flowed into a process chamber. In addition, a plasma is formed in the process chamber to deposit the dielectric material while flowing the first precursor, the second precursor, and the reactant gas into the process chamber.

Description

Method for forming semiconductor structure

Technical Field

Embodiments of the present disclosure relate to methods of forming semiconductor structures, and more particularly, to methods of forming synthetic nanofilled dielectric layers.

Background

The electronic industry is increasingly demanding smaller and faster electronic devices that simultaneously support a greater number of increasingly complex functions. In summary, there is a continuing trend in the semiconductor industry to form integrated circuits with lower cost, higher performance, and lower power consumption. Thus, the remote target is realized mainly by reducing the size of the semiconductor integrated circuit (e.g., the minimum structure size), thereby improving the productivity and reducing the associated cost. However, the reduction in size also increases the complexity of the semiconductor process. Similar advances in semiconductor processing and technology are needed to realize the continuing advances in semiconductor integrated circuits and devices.

As integrated circuit dimensions continue to shrink, semiconductor processes often necessitate filling high aspect ratio gaps with insulating materials. This process may be referred to as a gap-fill process. For example, the gap-fill process may be used for shallow trench isolation, inter-metal dielectric, passivation, hard mask, or other types of layers. In at least some conventional processes, poor material fill processes, such as poor gap fill processes, may result in gaps or voids, such as in metal gates, trenches, or the like, that degrade device performance. To alleviate the gap fill problem, flowable chemical vapor deposition processes have been introduced. Although flowable chemical vapor deposition deposits oxides with excellent flowability, they have poor chemical resistance to the etching process. Furthermore, at least some of the chemical units that are flowable chemical vapor deposition precursors have large stereochemistry, which is not conducive to gap fill applications.

The prior art is therefore not fully satisfactory in all respects.

Disclosure of Invention

The method for forming a semiconductor structure provided by one embodiment of the present disclosure includes: patterning the substrate to form a first structure, a second structure adjacent to the first structure, and a trench between the first structure and the second structure; and depositing a dielectric material on the first structure and in the trench, wherein the step of depositing the dielectric material comprises: flowing a first precursor, a second precursor, and a reactant gas into a process chamber; and forming a plasma in the process chamber to deposit the dielectric material while flowing the first precursor, the second precursor, and the reactant gas into the process chamber.

The method provided by one embodiment of the disclosure comprises the following steps: providing a substrate comprising a trench; conformably depositing a liner layer in the trench; and forming an isolation structure on the liner layer in the trench, wherein the isolation structure comprises silicon oxycarbonitride, silicon carbonitride, or silicon oxycarbide, and the step of forming the isolation structure comprises: flowing a silicon precursor and a carbon precursor into a process chamber; and pulsing power to the plasma source while flowing the silicon precursor and the carbon precursor into the process chamber to form the isolation structure.

The method provided by one embodiment of the disclosure comprises the following steps: providing a grid structure on a substrate, wherein a channel region is positioned below the grid structure; forming a trench on the gate structure; and depositing a mask layer in the trench, wherein the mask layer is deposited in a chemical vapor deposition process chamber, the chemical vapor deposition process chamber including a plasma module, and the step of depositing the mask layer includes flowing a silicon precursor and a carbon precursor into the chemical vapor deposition process chamber.

Drawings

FIG. 1 is a flow diagram of a method for using a synthetic nanofilled dielectric layer as a gap fill material in various embodiments.

Figure 2A is a cross-sectional view of a device having a composite nanofilled dielectric layer and a plurality of structures formed using the method of figure 1, in various embodiments.

Fig. 2B is a cross-sectional view of the device of fig. 2A after a chemical mechanical polishing process in some embodiments.

FIG. 3 is a flow diagram of a method for using a composite nanofilled dielectric layer as a hardmask in various embodiments.

Figure 4A is a cross-sectional view of a device having a gate structure and a synthetic nanofilled dielectric layer formed using the method of figure 3 in some embodiments.

Fig. 4B is a cross-sectional view of the device of fig. 4A after a chemical mechanical polishing process in some embodiments.

Fig. 5 is an exemplary reaction for forming a synthetic nanofilled dielectric layer, in some embodiments.

Fig. 6, 7, and 8 are exemplary silicon precursors in some embodiments.

Fig. 9, 10, 11, 12, 13, 14, 15, 16, 17, and 18 are exemplary carbon precursors in some embodiments.

Fig. 19 is an exemplary timing diagram for plasma power, reaction gases, carbon source, and silicon source during deposition of a synthetic fill nanolayered dielectric layer, in some embodiments.

Fig. 20 is an exemplary chemical vapor deposition system in which a synthetic nanofilled dielectric layer may be deposited.

Description of reference numerals:

height H

S、S_minSpace(s)

T, T' thickness

W1, W2 Width

100. 300 method

102. 104, 106, 108, 302, 304, 306, 308, 310

200. 400 device

202. 402 base plate

204 structure

206. 412, 510 synthetic nanofiller dielectric composition

403 gate structure

404 gate stack

406 spacer layer

408 dielectric layer

410 liner layer

502 silicon source

504 carbon source

506 reaction gas

508 reactive free radical

1900 timing diagram

2000 system

2002 process chamber

2004 crystal base

2006 wafer

2008 rod

2010 gas injection end

2012 exhaust end

2014 spray head

2016 power supply

Detailed Description

The different embodiments or examples provided below may implement different configurations of the present disclosure. The particular components and arrangements are provided to simplify the present disclosure and not to limit the same. For example, the formation of a first element on a second element is described as including direct or physical contact between the two elements, or the separation of additional elements other than direct contact between the two elements. Moreover, the various examples of the present disclosure may be repeated with reference numbers, but such repetition is merely intended to simplify and clarify the description and does not imply that there is a similar correspondence between elements having the same reference numbers in different embodiments and/or arrangements.

Also, spatially relative terms such as "below," "lower," "above," "upper," and the like may be used for ease of description to describe one element relative to another in the figures. Spatially relative terms may be extended to elements used in other orientations than the orientation illustrated. The elements may also be rotated 90 or other angles, and thus directional terms are used only to describe directions in the drawings.

It should be noted that the embodiments described herein may be used to design and/or fabricate any form of integrated circuit or portion thereof, it may include any of a variety of devices and/or components, such as static random access memory and/or other logic circuitry, passive components (e.g., resistors, capacitors, or inductors), and active components (e.g., p-channel field effect transistors, n-channel field effect transistors, metal oxide semiconductor field effect transistors, complementary metal oxide semiconductor transistors, bipolar transistors, high voltage transistors, high frequency transistors, fin field effect transistor devices, all-around gate devices, omega gate devices, or Π -gate devices, strained semiconductor devices, silicon-on-insulator devices, partially depleted silicon-on-insulator devices, fully depleted silicon-on-insulator devices, other memories), or other devices known in the art. It should be appreciated by those skilled in the art that other embodiments of semiconductor devices and/or circuits, including methods of designing and fabricating the same, may benefit from the embodiments of the present disclosure.

In semiconductor processing, it is often necessary to fill high aspect ratio gaps with an insulating material by a gap-fill process. In various embodiments, the gap-fill process may be used for shallow trench isolation, intermetal dielectric layers, passivation layers, hard mask layers, or other types of layers. In addition, poor gap-fill processes may or may cause gaps or voids (e.g., formed in metal gates, trenches, or the like) that degrade device performance. To address these problems, flowable chemical vapor deposition processes have been introduced. Although flowable chemical vapor deposition deposits oxides with excellent flowability, they have poor chemical resistance to the etching process. Furthermore, at least some of the chemical units that are flowable chemical vapor deposition precursors have large stereochemistry, which is not conducive to gap fill applications. The prior art is therefore not satisfactory in all respects.

The disclosed embodiments have many advantages over the prior art, but it is understood that other embodiments may provide different advantages, all of which need not be described herein, and all of which need not have a particular advantage. For example, embodiments described herein include dielectric material compositions and related methods of formation that can effectively alleviate at least some of the disadvantages of existing methods. In some embodiments, a synthetic nanofiller dielectric layer is employed to form a dielectric layer (e.g., an isolation structure). In some examples, the synthetic nanofilled dielectric layer may serve as a gap fill material, a hardmask material, or a general dielectric material layer. In some embodiments, the method of forming the synthetic nanofilled dielectric material may employ a chemical vapor deposition chamber equipped with a rotating susceptor and a plasma module. In some embodiments, methods of forming a synthetic nanofilled dielectric material include using one or more precursors, one precursor as a silicon and/or carbon source and another precursor as an additional carbon source to adjust the carbon content. In some embodiments, at least one precursor used to form the synthetic nanofilled dielectric material comprises silicon. In general, various embodiments of the present disclosure provide carbon-containing nanofilled dielectric materials that have excellent jar flow and chemical selectivity, and that are formed by synthetically incorporating Si-C-Si units into a network having-O-or-N-bridging groups. As such, the carbon content and framework species are adjusted to provide chemical selectivity, the dendrimers are applied to provide a level of mobility, and a means for producing a ternary or quaternary dielectric material of appropriate mobility is provided. Other embodiments and advantages will be apparent to those skilled in the art from consideration of the specification and practice of the disclosed embodiments.

It should be further noted that the dielectric material composition and method of forming the same according to the embodiments of the present disclosure are not limited to a particular substrate configuration, mask configuration, photoresist configuration, radiation source (e.g., radiation wavelength), and/or photolithography system configuration. For example, the material compositions and methods may be used to pattern structures and/or devices on a substrate, and the various substrate materials may be silicon, germanium, silicon carbide, silicon germanium, diamond, semiconductor compounds, or semiconductor alloys, and the substrate may optionally include one or more epitaxial layers, may be stressed to enhance performance, may include silicon-on-insulator structures, and/or may have other suitable enhancements. The processes to which embodiments of the present disclosure can be applied employ reflective masks (such as those used for extreme ultraviolet lithography), transmissive masks, binary intensity masks, phase shift masks, or other masks known in the art. In some examples, the embodiments described herein can be applied to various types of photoresist, and the photoresist can be polymethyl methacrylate, SU-8, extreme ultraviolet, positive, negative, or other types of photoresist known in the art. Furthermore, embodiments of the present disclosure may be used in a variety of lithography systems and/or alignment modalities, such as contact aligner, proximity aligner, projection aligner, or extreme ultraviolet lithography systems. Thus, embodiments of the present disclosure may further be used in systems employing any source of radiation (radiation wavelength) such as ultraviolet, deep ultraviolet, extreme ultraviolet, or other sources of radiation known in the art.

As shown in various embodiments in FIG. 1, the flow diagram of method 100 employs a synthetic nano-filled dielectric layer as a gap-fill material. It will be understood that additional steps may be provided before, during, and after the method 100, and that additional embodiments of the method may replace, omit, or swap some of the described steps. It should be noted that the method 100 is only used for example and not for limiting the embodiments of the disclosure to the places that are not actually recited in the claims. The method 100 will be described below in conjunction with fig. 2A and 2B.

The method 100 begins with step 102 by patterning a substrate to include a plurality of structures. In one embodiment of step 102, the apparatus 200 includes a substrate 202 having a plurality of structures 204 formed on the substrate 202, as shown in cross-section in FIG. 2A. In some embodiments, the substrate 202 may comprise one or more substrate materials such as silicon, germanium, silicon carbide, silicon germanium, semiconductor compounds, or the like, which may comprise one or more epitaxial layers, one or more conductive or insulating layers formed on the substrate 202, and/or various enhancement structures as described above. The substrate 202 may also include various doping arrangements depending on design requirements known in the art.

Further, the structure 204 of fig. 2A in various embodiments may correspond to a metal layer, an oxide layer, a nitride layer, a semiconductor layer, or other layers that constitute components of an integrated electrical device. In some examples, structure 204 may be combined with other structures to form various portions of an integrated circuit device and/or circuit. In some embodiments, the structure 204 may comprise a variety of structures known in the art that may be formed and/or deposited on the substrate 202. For example, the structure 204 of some embodiments may comprise a structural composition that may be silicon, silicon germanium, a silicon-based dielectric layer, a metal oxide, a metal nitride, a metal, or other material, and may comprise simple or complex structures such as fin structures used in forming finfet transistors, or other structures.

In various embodiments shown in fig. 2A, the plurality of structures 204 have various widths (e.g., width W1, W2, or the like) and heights H. The space between adjacent structures may be referred to as space S, and the minimum structural space may be referred to as space S_min. Various embodiments Prior to depositing the composite nanofiller dielectric composition, the plurality of structures 204 formed on the substrate 202 may define a plurality of trench or via structures (e.g., between adjacent structures) having a space S defined at least in part by the space between adjacent structuresThe variable width of the sense. In some embodiments, the space S between adjacent structures is greater than or equal to about 6 nm. In some examples, the width W1 or W2 is greater than or equal to about 6 nm. Aspect ratios (e.g., H/W1) refer to the aspect ratio of trench or via structures (e.g., located between adjacent structures). In some embodiments, the aspect ratio may be greater than or equal to about 8. Generally, the width W1 or W2 in various examples can be greater than or equal to about 6nm and less than or equal to about 50 nm. The height H may be greater than or equal to about 48nm and less than or equal to about 150 nm. The aspect ratio (H/W1 or H/W2) may be greater than or equal to about 1 and less than or equal to about 18.

Step 104 of method 100 deposits a composite nanofilled dielectric composition on the plurality of structures. In one embodiment of step 104, the apparatus 200 includes depositing a composite nanofilled dielectric material composition 206 on a substrate 202 and a plurality of structures 204, as shown in the cross-sectional view of the apparatus 200 of fig. 2A. As previously described, the method of forming the composite nanofilled dielectric composition 206 may be performed using a chemical vapor deposition process chamber equipped with a rotating susceptor and a plasma module. Additional details of an exemplary system and method for depositing the synthetic nanofilled dielectric material composition 206 are described below in conjunction with fig. 19 and 20. In some embodiments, a thickness T (e.g., in a trench or hole structure between adjacent structures 204) and a thickness T' (e.g., over one or more of the plurality of structures 204 on the substrate 202) of the composite nanofilled dielectric material composition 206 may be defined. In some embodiments, T/T' may be defined as the mobility of the synthetic nanofilled dielectric composition 206. In one example, T/T' may be greater than about 5 when the space S between adjacent structures is about 100 nm. Fluidity can be increased to improve the gap-filling process.

In some embodiments, the method of forming the composite nanofilled dielectric composition 206 (e.g., in a chemical vapor deposition process chamber) may employ one or two precursors, one precursor serving as the silicon and/or carbon source and the other precursor serving as an additional carbon source to adjust the carbon content. In some embodiments, at least one precursor for forming the synthetic nanofilled dielectric material comprises silicon. In some examples, the method of depositing the synthetic nanofiller dielectric composition 206 further comprises using ammoniaNitrogen, nitric oxide, nitrogen dioxide, oxygen, carbon dioxide, and/or hydrogen are reactive gases and may form radicals when a plasma is ignited, such as in a chemical vapor deposition process chamber. For example, a precursor having silicon and/or carbon may be reacted with nitrogen radicals, oxygen radicals, and/or hydrogen radicals in combination with the respective elements to deposit a composite nanofiller composition 206 having a composition such as silicon oxycarbonitride, silicon carbonitride, or silicon oxycarbide, i.e., to form the composite nanofiller composition 206. Using fig. 5 as an example, a composite nanofilled dielectric material composition 206 comprising carbon-containing silicon oxynitride may be fabricated. For example, the silicon source 502 (e.g., silicon precursor) has Si-C-Si bonds and the carbon source 504 (e.g., carbon precursor) has Si-CH₃The silicon source 502 and the carbon source 504 may be bonded together and reacted with a reaction gas 506 of ammonia or oxygen (e.g., in a chemical vapor deposition process chamber), wherein the reaction gas is converted into reactive radicals 508 (e.g., via a plasma reactor of an inductively coupled plasma). In some embodiments, the reactive radicals 508 may also react to form a synthetic nanofilled dielectric composition 510 of silicon oxycarbonitride having a network of Si-N-Si and Si-O-Si. Various additional structures and/or embodiments of the composition of the nanofilled dielectric material are synthesized, as described in detail below in conjunction with figures 6-18.

Step 106 of method 100 may optionally be subjected to a thermal annealing or ultraviolet curing process. For example, in some instances, after depositing the synthetic nanofiller dielectric composition 206, the device 200 may be subjected to a thermal anneal or uv curing process to reduce the hydrogen content, create cross-linking bonds, and increase the density of the synthetic nanofiller dielectric composition 206. In some embodiments, the temperature of the thermal annealing or uv curing process may be between about 300 ℃ to 450 ℃.

The method 100 continues with step 108 in which a chemical mechanical polishing process is performed. In one embodiment of step 108, a chemical mechanical polish may be performed to remove excess material from the composite nanofiller dielectric composition 206 and planarize the top surface of the device 200, as shown in fig. 2B. In some embodiments, after the chemical mechanical polishing process, an upper surface of the composite nanofiller dielectric composition 206 may be substantially coplanar with an upper surface of the plurality of structures 204 formed on the substrate 202.

Subsequent processing of the device 200 may be performed to form various structures and regions as is known in the art. For example, subsequent processes may form gate structures, contact openings, contact metals, various contacts/vias/lines, and multilayer interconnect structures (e.g., metal layers and interlevel dielectric layers) on the substrate 202 configured to connect the various structures to form functional circuits containing one or more multi-gate devices. In this case, the multilevel interconnects may include vertical interconnects such as vias or contacts, and horizontal interconnects such as metal lines. Various interconnect structures may employ various conductive materials such as copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper-related multilevel interconnect structure.

As shown in the flow diagram of FIG. 3, the method 300 of various embodiments employs a synthetic nanofilled dielectric layer as a hard mask. In some embodiments, method 300 is similar to method 100. However, the method 300 provides other examples of uses for synthesizing a nanofilled dielectric layer. It is understood that additional steps may be provided before, during, and after the method 300, and that additional embodiments of the method may replace, omit, or swap some of the described steps. It is noted that the method 300 is only for example and not limiting to the present disclosure where not actually recited in the claims. The method 300 may be further described below in conjunction with fig. 4A and 4B.

The method 300 begins with step 302 in which a substrate is patterned to include a gate structure. In one embodiment of step 302, the apparatus 400 includes a substrate 402, shown in cross-section in FIG. 4A. In some embodiments, the substrate 402 may be substantially the same as the substrate 202 described above in conjunction with the method 100. In various examples, the device 400 further includes a plurality of gate structures 403 (including gate stacks 404), one or more spacer layers 406, and a dielectric layer 408 electrically isolating adjacent gate stacks 404 and sandwiched between adjacent gate stacks 404. In some embodiments, a channel region of a transistor, such as a finfet, is located under gate stack 404. In various examples, the dielectric layer 408 comprises an interlayer dielectric layer comprising a material that can be tetraethoxysilane oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass, fluorine-doped silica glass, phosphosilicate glass, borosilicate glass, and/or other suitable dielectric materials. The deposition method of the dielectric layer 408 may be a plasma enhanced chemical vapor deposition process or other suitable deposition technique. In some embodiments, a contact etch stop layer may be deposited prior to depositing dielectric layer 408.

In some embodiments, the gate stack 404 includes a gate dielectric layer and a metal layer formed on the gate dielectric layer. In some embodiments, the gate dielectric layer may include an interfacial layer formed on the channel region, and a high-k dielectric layer formed on the interfacial layer. The interfacial layer may comprise a dielectric material such as silicon oxide or silicon oxynitride. The high-k dielectric layer may comprise hafnium oxide, titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium silicon oxide, combinations thereof, or other suitable materials. In other embodiments, the gate dielectric layer may comprise silicon oxide or another suitable dielectric layer. The gate dielectric layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition, physical vapor deposition, chemical vapor deposition, and/or other suitable methods. The metal layer may comprise a conductive layer such as tungsten, titanium nitride, tantalum nitride, tungsten nitride, rhenium, iridium, ruthenium, molybdenum, aluminum, copper, cobalt, nickel, combinations thereof, and/or other suitable compositions. In some embodiments, the metal layer may include a first metal material for an n-type finfet and a second metal material for a p-type finfet. The device 400 may include an arrangement of dual work function metal gates. In some embodiments, the metal layer may instead comprise a polysilicon layer. The metal layer may be formed by physical vapor deposition, chemical vapor deposition, e-beam evaporation, and/or other suitable processes. In some embodiments, one or more spacer layers 406 are formed on sidewalls of the gate structure 403. The one or more spacer layers may comprise a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof. It is noted that the gate structure 403 may include a high-k gate dielectric layer and a metal gate. The gate structure 403 in some examples comprises a dummy gate stack, which may be replaced by a final gate stack in a later process stage of manufacturing the device 400, wherein the final gate stack comprises a high-k gate dielectric layer and a metal gate.

In an intermediate stage of the fabrication of the device 400, such as after forming the plurality of gate structures 403, the one or more spacer layers 406, and the dielectric layer 408, a plurality of trench or hole structures (such as defined between the adjacent dielectric layer 408 and the gate stack 404) may be defined. In some embodiments, the trench or hole structure may have a depth and width ratio as shown in FIG. 4A, which may be defined in a manner similar to that described above in conjunction with FIG. 2A.

The method 300 proceeds to step 304 by depositing a liner layer in the plurality of trenches or holes in the gate stack. In one embodiment of step 304, the device 400 includes a liner layer 410 deposited on the substrate 402 and the gate stack 404, as shown in the cross-sectional view of FIG. 4A. In some embodiments, the deposition method of the liner layer 410 is atomic layer deposition to conformably deposit the liner layer 410. In other embodiments, the liner layer 410 is deposited by physical vapor deposition, chemical vapor deposition, or other suitable techniques. In various embodiments, the liner layer may comprise a nitride layer (e.g., titanium nitride, tantalum nitride, silicon-based nitride, or other nitride layer), an oxide layer, or other suitable layer.

Step 306 of method 300 deposits a hard mask layer over the liner layer. In various embodiments, the hardmask layer of the method comprises a composition of synthetic nanofilled dielectric material as described herein. In one embodiment of step 306, the device 400 includes a composite nanofilled dielectric material composition 412 deposited on the substrate 402 and the gate stack 404, as shown in the cross-sectional view of fig. 4A. In some embodiments, the synthetic nanofiller composition 412 may be similar to the synthetic nanofiller composition 206 described above in conjunction with the method 100.

Thus, the method of forming the composite nanofiller composition 412 may employ a chemical vapor deposition process chamber equipped with a spin chuck and a plasma module. Additionally, the method of forming the composite nanofiller composition 412 may comprise a plurality of precursors. One precursor serves as a silicon and/or carbon source and the other precursor serves as an additional carbon source to adjust the carbon content. In some embodiments, at least one precursor used to form the synthetic nanofilled dielectric material composition 412 comprises silicon. In some embodiments, the synthetic nanofiller composition 412 may comprise a synthetic nanofiller composition of silicon oxycarbonitride having a network of Si-N-Si and Si-O-Si as described above. Various other configurations and/or embodiments of the synthetic nanofiller composition 412 may be similar to the synthetic nanofiller composition 206 described above and/or described in detail below in conjunction with figures 6-18.

Step 308 of method 300 may optionally be subjected to a thermal annealing or ultraviolet curing process. In some embodiments, after depositing the synthetic nanofiller composition 412, the device 400 may be subjected to a thermal annealing or uv curing process to reduce the hydrogen content, create cross-linking bonds, and increase the density of the synthetic nanofiller composition 412. In some embodiments, the temperature of the thermal annealing or uv curing process may be between about 300 ℃ to 450 ℃.

The method 300 continues with step 310 in which a chemical mechanical polishing process is performed. In one embodiment of step 310, a chemical mechanical polishing process may be performed to remove excess material from the composite nanofiller composition 412 and planarize the upper surface of the device 400, as shown in fig. 4B. In some embodiments, the chemical mechanical polishing process may also etch the liner layer 410 from the top surface of the dielectric layer 408. In some examples, the upper surface of the resultant nanofilled dielectric material composition 412 after the chemical mechanical polishing process may be substantially coplanar with the upper surface of the dielectric layer 408.

Subsequent processing of the device 400 may be performed to form various structures and regions as is known in the art. For example, subsequent processes may form contact openings, contact metals, various contacts/vias/lines, and multilayer interconnect structures (e.g., metal layers and interlevel dielectric layers) on the substrate 402 configured to connect the various structures to form functional circuits including one or more multi-gate devices. In this case, the multilevel interconnect structure may include vertical interconnects such as vias or contacts, and horizontal interconnects such as metal lines. Various interconnect structures may employ various conductive materials such as copper, tungsten, and/or silicide. In one example, a copper-related multilayer interconnect structure may be formed using a damascene and/or dual damascene process.

Various structures of nanofilled dielectric material compositions are synthesized as described in further detail below. As described above, the synthetic nanofilled dielectric compositions described herein may be used to form isolation structures containing at least one silicon precursor. In some examples, the silicon precursor may contain at least two silicon atoms and include a Si-C-Si bonded structure. For example, an exemplary silicon precursor may be written as formula CH_x(SiH₃)_yWherein x + y is 4 and y is greater than or equal to about 2. For example, the silicon precursor may comprise CH₂(SiH₃)₂、CH(SiH₃)₃Or C (SiH)₃)₄As shown in fig. 6, 7, and 8, respectively. In some examples, the other precursor includes at least one Si-CH₃An end group, which may be defined as a carbon precursor added to the composite nanofilled dielectric composition, is adjusted by carbon content to optimize the carbon/silicon ratio of the composite nanofilled dielectric composition. In some embodiments, the carbon precursor may comprise methylsilane, aminosilane, silazane, or the like. In some examples, methylsilane as the carbon precursor may be written as SiH_x(CH₃)_yWherein x + y is 4 and y is greater than or equal to about 1. For example, methylsilane may comprise SiH₃(CH₃)、SiH₂(CH₃)₂、SiH(CH₃)₃Or Si (CH)₃)₄Which correspond to fig. 9, 10, 11, or 12, respectively. In some embodiments, the aminosilane used as the carbon precursor may be written to have the formula SiH_x(R₁)_y(R₂)_zWherein R is₁Is CH₃，R₂Is NH₂、NH(CH₃) Or N (CH)₃)₂Wherein x + y + z is 4, and y and z are greater than or equal to about 1. For example, the aminosilane may comprise Si (CH)₃)₃(NH₂)、Si(CH₃)₃(N(CH₃)₂)、SiH(CH₃)(NH(CH₃))₂Or Si (CH)₃)₂(NH(CH₃))₂Which correspond to fig. 13, 14, 15, or 16, respectively. In some embodiments, the silazane used as the carbon precursor may be written as Si (NH) SiH_2x(CH₃)_2yWherein x + y is 3 and y is greater than or equal to about 1. For example, the silazane can comprise Si (NH) SiH corresponding to FIG. 17₂(CH₃)₄Si (NH) Si (CH) corresponding to FIG. 18₃)₆. While some examples of chemical structures for silicon and carbon precursors have been provided, it is understood that other structures and other precursors may be employed without departing from the scope of the embodiments of the present disclosure.

Such as the exemplary chemical vapor deposition system 2000 shown in fig. 20, in which processes may be performed to form the synthetic nanofilled dielectric layers described herein. In some embodiments, the system 2000 includes a process chamber 2002 and a susceptor 2004 on which one or more wafers 2006 may be placed. In some examples, the susceptor 2004 may be held in place by a rod 2008, wherein the rod 2008 is coupled to a drive unit to rotate the susceptor 2004 during processing. In some embodiments, the system 2000 may also include a plurality of gas injection ports 2010 (to provide a plurality of precursors, carrier gases, and/or reactant gases) and exhaust ports 2012. In various examples, the system 2000 may include one or more heating units to heat the susceptor 2004, the wafer 2006, and/or the process chamber 2002. Additionally, the process chamber 2002 may be fluidly coupled to a vacuum/pumping system, and the vacuum pumping system is used to maintain vacuum conditions of the process chamber 2002. In various examples, the vacuum/pumping system may include one or more load lock chambers, turbomolecular pumping, cryogenic pumping, mechanical pumping, or other suitable vacuum/pumping system units.

In various embodiments, the system 2000 also includes a plasma module having a showerhead 2014 coupled to a power supply 2016 (e.g., an rf power supply) to generate a plasma in the process chamber 2002 (e.g., using one or more gases delivered through a gas injection port 2010). In various examples, the plasma module may include an inductively coupled plasma source, a continuous microwave plasma, a pulsed capacitively coupled plasma generator, or a pulsed microwave plasma generator. In some embodiments, helium is used as a carrier gas, and ammonia, nitrogen, nitric oxide, nitrogen dioxide, oxygen, carbon dioxide, and/or hydrogen are used as reactant gases (e.g., via the plurality of gas injection ports 2010) for forming a plasma and depositing a synthetic nanofilled dielectric layer. In some examples, the deposition temperature (such as used to deposit the synthetic nanofilled dielectric layer on wafer 2006) is between about 40 ℃ to about 150 ℃. In some embodiments, an inductively coupled plasma source or a microwave plasma generator (2.45GHz) may be used to generate the radicals for the reactions in the process chamber 2002.

Fig. 19 is a timing diagram 1900 illustrating the timing of the silicon source, the carbon source, the reactant gas, and the plasma power (e.g., pulsed plasma module) during deposition of a composite nanofilled dielectric layer (e.g., using the system 2000 of fig. 20). In various embodiments, as shown, the process for synthesizing a nanofilled dielectric deposition includes a flow stabilization step and a main deposition step. In the above steps, a silicon source, a carbon source, and a reaction gas may be flowed into the process chamber 2002. However, in various examples, the silicon precursor and the carbon precursor are mixed without reaction in the flow stabilization step, and the reaction gas and the precursor are not reacted with each other.

As described above, a plasma source (such as the plasma module described above) and a pulse cycle period may be employed in depositing the synthetic nanofilled dielectric layer. For example, a pulsed capacitively coupled plasma generator (10MHz to 70MHz) or a pulsed microwave plasma generator may be employed. In some embodiments, the pulsed plasma module includes a pulse-on period and a pulse-off period, as shown in fig. 19. In some embodiments, the pulse-on period/pulse-off period is defined as the duty cycle of the pulsed plasma source. In some examples, 1/(pulse-on period + pulse-off period) is defined as the pulse repetition frequency of the pulsed plasma source. In some embodiments, the pulse on period may be between μ s to ms, and the duty cycle may be between about 5% to 95%. In some examples, the pulse repetition frequency may be between about 50kHz to 100 kHz. In various examples, the operation, pulsing, or tuning of the pulsed plasma source occurs during the main deposition step.

Additional embodiments of synthetic nanofilled dielectric layers and methods of deposition thereof are provided herein. For example, some embodiments of a method for forming a silicon oxycarbide composite nanofilled dielectric layer may employ C (SiH)₃)₄As a silicon source and oxygen gas as a reaction gas. In some embodiments, the temperature of the process and/or deposition is between about 50 ℃ to 80 ℃, and the inductively coupled plasma source may generate oxygen radicals for subsequent reactions. In some examples, a carbon precursor SiH may be added₂(CH₃)₂To be co-flowed with the silicon precursor. In some embodiments, the temperature of the post thermal anneal is between about 300 ℃ to 450 ℃ to condense the film (e.g., reduce moisture content) and increase the density of the resultant nanofilled dielectric layer. In the case of a synthetic nanofilled dielectric layer of silicon oxycarbide, the carbon content% of the synthetic nanofilled dielectric layer is between about 4% and 18% and the density is about 1.5g/cm³To 2.1g/cm³In the meantime. In various embodiments, the etch selectivity of dilute hydrofluoric acid (100: 1) to the synthetic nanofilled dielectric layer and oxide is greater than about 10. In some embodiments, the etch selectivity of nitrogen trifluoride and ammonia to the synthetic nanofilled dielectric layer and oxide is greater than about 20. In some examples, the dielectric constant of the deposited synthetic nanofilled dielectric layer is between about 3 and 4.5 and the leakage current density is between about 10^-9A/cm²To 10^-7A/cm²And a breakdown field of between 3MV/cm and 6 MV/cm.

In some embodiments, the method of forming the silicon carbonitride nanofilled dielectric layer may employ C (SiH)₃)₄As a silicon source and ammonia is used as a reaction gas. In some embodiments, the temperature of the process and/or deposition is between about 75 ℃ to 110 ℃, while the pulsed microwave plasma generator may generate ammonia radicals for subsequent reactions. In various examples, carbon precursors (including Si (CH)) may be added₃)₃(N(CH₃)₂) To co-flow with the silicon precursor. At one endIn some embodiments, the temperature of the UV curing process is between about 300 ℃ and 450 ℃ to reduce the hydrogen content and condense the film. In some embodiments, the% carbon content of the synthetic nanofilled dielectric layer of silicon carbonitride is between about 3% and 10% and the density is between about 1.7g/cm³To 2.4g/cm³In the meantime. In some embodiments, the etch selectivity of dilute hydrofluoric acid (100: 1) to the synthetic nanofilled dielectric layer and oxide is greater than about 10. In some embodiments, the phosphoric acid has an etch selectivity to the synthetic nanofilled dielectric layer and the silicon nitride of greater than about 5. In some examples, the dry etch selectivity of the plasma of hydrocarbon fluoride and oxygen to the composite nanofilled dielectric layer and silicon nitride is greater than about 1.5.

In some examples, a method of forming a silicon oxycarbonitride composite nanofilled dielectric layer may employ C (SiH)₃)₄As a silicon source and ammonia/oxygen gas as a reaction gas. In various examples, the ratio of ammonia to oxygen is between about 0.2 and 0.5. In some embodiments, the temperature of the process and/or deposition is between about 60 ℃ to 100 ℃, while the pulsed microwave plasma generator can generate ammonia and oxygen radicals for subsequent reactions. In some examples, the pulse-on period of fig. 19 is between about 100 μ s to 1ms and the duty cycle is between about 40% to 70%. In some embodiments, a carbon precursor (containing Si (NH) SiH) may be added₂(CH₃)₄) To be co-flowed with the silicon precursor. In some examples, the temperature of the thermal annealing process is between about 300 ℃ to 450 ℃ to reduce the hydrogen content of the membrane and to condense the membrane. In some embodiments, the carbon content% of the silicon oxycarbonitride synthetic nanofilled dielectric layer is between about 8% to 18%, the nitrogen/oxygen ratio is between about 0.3 to 0.7, and the density is between about 1.9g/cm³To 2.4g/cm³In the meantime. In various embodiments, the dielectric constant of the composite nanofilled dielectric layer is between about 4.5 and 5.5 and the leakage current density is between about 10^-10A/cm²To 10^-8A/cm²And the breakdown field is between 4MV/cm and 6 MV/cm. In some embodiments, the etch selectivity of dilute hydrofluoric acid (100: 1) to the synthetic nanofilled dielectric layer and oxide is greater than about 10. In thatIn some embodiments, the etch selectivity of nitrogen trifluoride and ammonia to the synthetic nanofilled dielectric layer and oxide is greater than about 20. For example, the chlorine-based etch has an etch selectivity to the synthetic nanofilled dielectric layer and silicon of greater than about 12. In some embodiments, the dry etch selectivity of the hydrocarbon fluoride and oxygen plasma to the synthetic nanofilled dielectric layer and silicon nitride (and silicon oxide) is greater than about 4.

The disclosed embodiments have many advantages over the prior art, but it is understood that other embodiments may provide different advantages, all of which need not be described herein, and all of which need not have a particular advantage. For example, embodiments described herein include dielectric material compositions and related methods that effectively mitigate at least some of the disadvantages of prior methods. In some embodiments, a synthetic nanofilled dielectric layer is used to form the dielectric layer. In some examples, the synthetic nanofilled dielectric layer may serve as a gap fill material, a hardmask material, or a general dielectric material layer. In some embodiments, the method of forming the synthetic nanofilled dielectric material may employ a chemical vapor deposition process chamber equipped with a rotating susceptor and a plasma module. In some embodiments, the method of forming the composite nanofiller includes using one or two precursors, one precursor as the silicon and/or carbon source and the other precursor as an additional carbon source to adjust the carbon content. In some examples, the carbon content is adjusted to adjust the etch selectivity. In some embodiments, at least one precursor for forming the synthetic nanofilled dielectric material comprises silicon. In general, various embodiments of the present disclosure provide methods for forming carbon-containing nanofilled dielectric materials having excellent flow properties and chemical selectivity. It will be appreciated by those skilled in the art that the methods described herein may be applied to a variety of other semiconductor structures, semiconductor devices, and semiconductor processes to achieve similar advantages as described herein without departing from the scope of the embodiments of the present disclosure.

Thus, a method of an embodiment of the present disclosure includes patterning a substrate to form a first structure, a second structure adjacent to the first structure, and a trench between the first structure and the second structure. The method also includes depositing a dielectric material over the first structure and in the trench. In some embodiments, the step of depositing the dielectric material comprises: a first precursor, a second precursor, and a reactant gas are flowed into a process chamber. In addition, a plasma is formed in the process chamber to deposit the dielectric material while flowing the first precursor, the second precursor, and the reactant gas into the process chamber.

In some embodiments, the reactant gas comprises at least one of ammonia, nitrogen, nitric oxide, nitrogen dioxide, oxygen, carbon dioxide, and hydrogen.

In some embodiments, the composition of the dielectric material includes a network of Si-N-Si bonds and Si-O-Si bonds.

In some embodiments, the first precursor comprises a silicon precursor and the second precursor comprises a carbon precursor.

In some embodiments, the silicon precursor includes a Si-C-Si bonded structure and the carbon precursor includes Si-CH₃And (3) a terminal group.

In some embodiments, the carbon precursor comprises methylsilane, aminosilane, or azasilane.

In some embodiments, the% carbon content of the dielectric material is between 3% and 18%.

In some embodiments, the dielectric material comprises silicon oxycarbonitride, silicon carbonitride, or silicon oxycarbide.

In another embodiment, a method includes providing a substrate including a trench; conformably depositing a liner layer in the trench; and forming an isolation structure on the liner layer in the trench. In some embodiments, the isolation structure comprises silicon oxycarbonitride, silicon carbonitride, or silicon oxycarbide. In various examples, the step of forming the isolation structure includes: a silicon precursor and a carbon precursor are flowed into a process chamber. Some embodiments pulse the power of the plasma source to form the isolation structure while flowing the silicon precursor and the carbon precursor into the process chamber.

In some embodiments, the step of forming the isolation structure comprises a flow stabilization step and a main deposition step, wherein the plasma source power is pulsed during the main deposition step.

In some embodiments, the first precursor and the second precursor are not reacted during the flow stabilization step, and the reaction gas is not reacted with the first precursor or the second precursor.

In some embodiments, the plasma source comprises an inductively coupled plasma source, a continuous microwave plasma, a pulsed capacitively coupled plasma generator, or a pulsed microwave plasma generator.

In some embodiments, the step of forming the isolation structure includes depositing an isolation structure of a first thickness in the trench and depositing an isolation structure of a second thickness on the first structure, wherein a ratio of the first thickness to the second thickness is greater than 5.

In some embodiments, the method further comprises: after the isolation structure is formed, an annealing process is performed to reduce the hydrogen content of the isolation structure and increase the density of the isolation structure, wherein the annealing process is performed at a temperature between 300 ℃ and 450 ℃.

In some embodiments, the temperature at which the isolation structure is formed is between 40 ℃ and 150 ℃.

In some embodiments, the space between the first structure and the second structure is greater than or equal to 6nm, wherein the width of each of the first structure and the second structure is greater than or equal to 6nm and less than or equal to 50nm, and wherein the height of the first structure and the second structure is greater than or equal to 48nm and less than or equal to 150 nm.

In other embodiments, a method comprises: providing a gate structure on the substrate, wherein the channel region is located under the gate structure. The method further includes forming a trench over the gate structure and depositing a mask layer in the trench. The masking layer is deposited within a chemical vapor deposition process chamber, and the chemical vapor deposition process chamber includes a plasma module. In some embodiments, depositing the masking layer includes flowing a silicon precursor and a carbon precursor into the chemical vapor deposition process chamber.

In some embodiments, the method further comprises depositing a liner layer in the trench and depositing a mask layer on the liner layer prior to depositing the mask layer.

In some embodiments, the method further comprises: the mask layer is annealed after deposition of the mask layer, and a chemical mechanical polishing process is performed to planarize the upper surface of the gate structure.

In some embodiments, the masking layer comprises silicon oxycarbonitride, silicon carbonitride, or silicon oxycarbide.

Claims

1. A method of forming a semiconductor structure, comprising:

patterning a substrate to form a first structure, a second structure adjacent to the first structure, and a trench between the first structure and the second structure; and

depositing a dielectric material on the first structure and in the trench, wherein the step of depositing the dielectric material comprises:

flowing a first precursor, a second precursor, and a reactant gas into a process chamber; and

a plasma is formed in the process chamber to deposit the dielectric material while flowing the first precursor, the second precursor, and the reactant gas into the process chamber.