CN110658879B - Apparatus for improving performance of sigma delta modulator - Google Patents

Apparatus for improving performance of sigma delta modulator Download PDF

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CN110658879B
CN110658879B CN201910575990.4A CN201910575990A CN110658879B CN 110658879 B CN110658879 B CN 110658879B CN 201910575990 A CN201910575990 A CN 201910575990A CN 110658879 B CN110658879 B CN 110658879B
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transistor
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drain
current
voltage
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CN110658879A (en
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A·马丁·马林森
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Silicon Valley Intervention Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

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Abstract

The invention provides a low noise quantization feedback configuration. In particular, described herein are improved apparatus for improving the performance of a Σ Δ modulator, which may be used as an ADC. In one embodiment, a Σ Δ modulator includes: the differential input circuit includes a voltage-to-current converter, a capacitor connected between two output terminals of the voltage-to-current converter to receive a differential input current, and a switch switchable between connecting each output terminal of the voltage-to-current converter to ground while disconnecting the other output terminal of the voltage-to-current converter. In this embodiment, the Σ Δ modulator has no common-mode control loop and no reference current. This results in a reduced complexity, i.e. fewer components and reduced noise.

Description

Apparatus for improving performance of sigma delta modulator
Cross Reference to Related Applications
This application claims priority to provisional application No. 62/691,504 filed on 28.6.2018, which is incorporated herein by reference in its entirety.
Technical Field
The present invention relates generally to sigma delta modulators and more particularly to sigma delta modulators without a common mode control loop.
Background
The analog to digital conversion may be performed in a control loop using quantization feedback. Analog-to-digital converters (ADCs) having such characteristics are commonly referred to as sigma delta converters or sigma delta modulators, the modulator term referring to the output digital data stream having a certain symbol pattern or modulation applied thereto by the control loop. The terms Σ Δ modulator and noise shaping control loop are often used interchangeably in the art, although the latter is more descriptive. Circuit designers often prefer to use such sigma delta modulators because, in many cases, such sigma delta modulators may be easier to design and less costly to manufacture than other types of ADCs.
In such a noise shaping control loop, a continuous analog signal is applied at the input and a digital pattern representing the signal appears from the output. The digital signal is generated by controlling one or more quantization elements in the loop, for example by a non-linear element in the loop, such as a flip-flop or comparator, having a discrete set of non-continuous output values for any given continuous input quantity.
Σ Δ modulation works by constraining the feedback parameter to one of a set of at least two specific values, and a control loop of arbitrary order ensures that the average feedback value is equal to the input. The instantaneous deviation from the ideal continuous feedback necessarily introduced by the quantising element represents noise and a complex, possibly high order, control loop can suppress or "shape" this noise. "shaping" the noise means filtering it, usually so that it does not occur in certain frequency bands. Thus, the loop operates to suppress this noise in certain frequency bands of interest, typically at the expense of increased noise in application-independent frequency bands. Therefore, the Σ Δ modulator is sometimes also referred to as a "noise shaping loop".
In some sigma delta modulators, the input parameter is a current (or current difference) in a portion of the circuit, and two or more currents (or difference currents) are generated to provide feedback. Fig. 1 shows an example of a prior art circuit 100 in which an input differential current is made to flow in the drains of transistors M1 and M2. In this case the "common mode currents" have to be balanced, i.e. the sum of the currents through the drains of M1 and M2 has to be equal to the sum of the currents in the current sources I3, I4 and I5.
The components below the common mode control portion of the circuit 100, i.e., transistors M1 and M2, add complexity and cost. Furthermore, whenever the circuit operates by zeroing the difference of two quantities, as in circuit 100, this only makes the nominal values of these quantities equal; if a quantity has correlated noise, the noise is not cancelled but remains in the difference of the two quantities as the square root of the sum of the individual noise components.
For these reasons, a simple and inexpensive way to improve the performance of a Σ Δ modulator by eliminating any common-mode control may be useful.
Disclosure of Invention
The present application describes apparatus and methods for improving the performance of a Σ Δ modulator.
One embodiment describes an apparatus comprising: a voltage-to-current converter, the voltage-to-current converter comprising: a first transistor and a second transistor, each transistor having a gate, a source, and a drain; an input signal source connected between a gate of the first transistor and a gate of the second transistor and providing an input signal; a resistor connected between the source of the first transistor and the source of the second transistor; a first current source connected to a source of the first transistor and to a power supply; a second current source connected to the source of the second transistor and to the power supply; wherein there is a difference between a current from the drain of the first transistor and a current from the drain of the second transistor, the difference between the currents representing the input signal; a capacitor connected between the drain of the first transistor and the drain of the second transistor; a switch connected to the drain of the first transistor and the drain of the second transistor and having two positions, a first position connecting the drain of the first transistor to ground and leaving the drain of the second transistor unconnected to ground, and a second position connecting the drain of the second transistor to ground and leaving the drain of the first transistor unconnected to ground; and a control circuit that measures the voltage across the capacitor and causes the switch to change between two positions so that the average value of the charge on the capacitor remains zero.
Another embodiment describes an apparatus comprising: a voltage-to-current converter, the voltage-to-current converter comprising: a first transistor and a second transistor, each transistor having a gate, a source, and a drain; an input signal source connected between a gate of the first transistor and a gate of the second transistor; a resistor connected between the source of the first transistor and the source of the second transistor; a first current source connected to a source of the first transistor and to a power supply; a second current source connected to the source of the second transistor and to the power supply; wherein there is a difference between a current from the drain of the first transistor and a current from the drain of the second transistor, the difference between the currents representing the input signal; a capacitor connected between the drain of the first transistor and the drain of the second transistor; a third transistor having a gate, a source, and a drain, the source and the gate being connected to the drain of the first transistor; a fourth transistor having a gate, a source, and a drain, the source being connected to the drain of the first transistor; a fifth transistor having a gate, a source, and a drain, the source and the gate being connected to the drain of the second transistor and the gate of the fourth transistor; a sixth transistor having a gate, a source, and a drain, the source being connected to the drain of the first transistor and the gate of the third transistor; a switch connected to the drain of the third transistor, the drain of the fourth transistor, the drain of the fifth transistor, and the drain of the sixth transistor and having two positions, a first position connecting the drain of the third transistor and the drain of the fourth transistor to ground and leaving the drain of the fifth transistor and the drain of the sixth transistor unconnected to ground, and a second position connecting the drain of the fifth transistor and the drain of the sixth transistor to ground and leaving the drain of the third transistor and the drain of the fourth transistor unconnected to ground; and a control circuit that measures the voltage across the capacitor and causes the switch to change between two positions so that the average value of the charge on the capacitor remains zero.
Drawings
Fig. 1 is a diagram of a Σ Δ modulator known in the prior art.
Fig. 2 is a diagram of another sigma delta modulator known in the prior art.
Fig. 3 is a diagram of a Σ Δ modulator without a common-mode control loop, according to an embodiment.
Fig. 4 is a diagram of a Σ Δ modulator without a common-mode control loop, according to another embodiment.
Fig. 5 is a diagram of a Σ Δ modulator without a common-mode control loop according to yet another embodiment.
Detailed Description
The present application describes an improved Σ Δ modulator that can be used as an ADC. In one embodiment, the Σ Δ modulator has no common-mode control loop and no reference current. This results in reduced complexity, i.e. fewer components, and reduced noise.
As described above, fig. 1 shows an example of a prior art Σ Δ modulator circuit 100 in which an input differential current is made to flow in the drains of transistors M1 and M2. This occurs because a portion of the nominally equal current of current sources I1 and I2 flows through resistor RSIG1 due to input voltage VSIG1, which VSIG1 is applied to the gates of transistors M1 and M2.
Such a configuration of the upper part of the circuit 100 with current sources I1 and I2, transistors M1 and M2, resistor RSIG1 and input voltage source VSIG1 is well known to a person skilled in the art and constitutes what is commonly referred to as a voltage-to-current (V-to-I) converter. The V-to-I converter converts the input voltage VSIG1 into an input differential current IinThe input differential current IinFrom the drains of transistors M1 and M2 to the lower portion of circuit 100. (in some applications, the input current source applied between the source terminals of M1 and M2 may replace input voltage source VSIG 1.)
Input differential current IinInto current sources I4 and I5, current sources I4 and I5 are also nominally equal currents. Therefore, if the reference current source I3 and the switch S1 are not present, the input differential current I isinCannot pass through equal current sources I4 and I5 and will therefore accumulate on capacitor C1.
However, the presence of the reference current source I3 and the switch S1 causes the current of I3 to be added to the current of the current source I4 or I5, and thus a different amount of current appears at the drains of transistors M1 and M2. Thus, the difference is added to the input difference current IinOr from the input of a differential current IinSubtracting, thereby changing the voltage across capacitor C1.
A control loop (not shown) checks the voltage across capacitor C1 by checking the voltage difference between the outputs Out and Outb. The control loop then drives switch S1 to change its position as needed to ensure an average input differential current IinEqual to the I3 current modified by switch S1, i.e., the I3 current multiplied by the difference in time that switch S1 spends in its two states.
In addition to this, the "common mode currents" must be balanced; that is, the sum of the currents through the M1 and M2 drains must be equal to the sum of the currents through the sources I3, I4, and I5. If this is not the case, the voltages on the left and right sides of capacitor C1 will move toward the power supply potential or ground, respectively. The voltages on the left and right sides of the capacitor C1 are common mode voltages, and the average voltage accumulated across the capacitor is the normal mode voltage. The normal mode voltage is checked by the control loop and changes switch S1. In the prior art, there must also be a common mode voltage control loop that keeps the voltage from being too high or too low.
Fig. 1 includes one example of a common mode voltage control loop. One input of amplifier U1 is the voltage at the center tap of resistors R1 and R2, and the other input is voltage CMV. Amplifier U1 sums the voltages across resistors R1 and R2 and adjusts currents I4 and I5 to maintain the common mode voltage at value CMV.
Another example of a prior art sigma delta modulator of this type is the circuit 200 of fig. 2, which is a single bit first order sigma delta modulator used in a philips PM 2517 automatic digital multimeter; see philips technical manual, vol 38,1978/79, No.7/8, page 187. Also, a common mode loop is used, wherein the current difference between transistors T1 and T2 is balanced with the current from transistors T3 and T4. Current flows down one side or the other of circuit 200; the voltage on the right side is constant, while the voltage on the left side can vary up and down. The quantized signal feeds back both the left and right sides.
In circuit 200, transistors T1 and T2 each receive nominally equal current (from a current source below them). Common mode control is achieved by modifying the current through transistors T1 and T2 based on the input signal on resistor Rconv. Thus, the current through transistor T1 is different from the current through transistor T2, and the output of comparator 201 is fed to flip-flop 202, which flip-flop 202 is used to apply a voltage to the gates of transistors T3 and T4, causing transistors T3 and T4 to switch the Iref current to compensate for the difference.
Another problem in the prior art circuits of fig. 1 and 2 is the presence of noise. As described above, each time the circuit operates by zeroing the difference of the two quantities (which can be seen in the case of the prior art circuits 100 and 200 of fig. 1 and 2), only the nominal values of the quantities are made equal. Therefore, if the amount has correlated noise, the correlated noise is not eliminated; instead, correlated noise still exists in the difference between the two quantities as the square root of the sum of the individual noises.
For example, to obtain an average value of zero, a series of values may be generated, such as:
1 -1 1 -1
to obtain an average value of 1, the sequence may be:
1 1 1 1
and an average value of 0.5 can be expressed as:
1 1 1 -1 1 1 1 -1
however, the values of 1 and-1 may have noise, so instead of these expected values, the actual values may be, for example, 0.9 and-0.95.
In the circuit 200 of fig. 2, the noise present in the signal Iref is added to the noise of the two adjustable current sources in the V-to-I converter block. The common mode circuit matches the absolute value of Iref to the sum of the two adjustable currents but does not reduce noise. Similarly, in the circuit 100 of fig. 1, the noise present in the current source I3 adds noise to the noise of the adjustable current sources I4 and I5.
Fig. 3 illustrates a sigma delta modulator circuit 300 according to an embodiment. As with the circuit 100 of fig. 1, the upper portion of the circuit 300 includes current sources I1 and I2, transistors M1 and M2, a resistor RSIG1, and an input voltage source VSIG1, which again includes a V-to-I converter.
Input difference current I between currents from drains of transistors M1 and M2 in circuit 300inIs generated in the same manner as in circuit 100 and the action of switch S1 is similarly controlled by a control circuit (not shown). However, there is no balancing current in the circuit 300, i.e. the current sources I4 and I5 of the circuit 100 are not present in the circuit 300. There is also no feedback current of current source I3 of circuit 100 in circuit 300. Alternatively, switch S1 forces one side or the other of circuit 300 to ground and opens the other side to a common mode voltage because the current on that side has no place to goOnly capacitor C1 can be entered.
Without the feedback current I3 of the circuit 100 or the reference current Iref of the circuit 200, there seems to be no reference in fig. 3. Instead of comparing the input signal with the reference current, the input signal is compared with the largest possible signal. That is, this is used as a reference when all input current passes through the RSIG1 in one direction or the other.
The circuit 300 operates to provide quantized feedback despite the absence of a reference current or feedback current. This can be seen by comparing the effect of circuit 300 with the effect of circuit 100.
In the circuit 100 of fig. 1, it can be seen that: depending on the state of switch S1, capacitor C1 will be equal to the difference current IinPlus or minus the current I3 (i.e., I)in+ I3 or Iin-I3), again assuming that currents I1, I2, I3 and I4 are all equal.
In the circuit 300 of fig. 3, the current sources I3, I4, and I5 are no longer present. In this case, also depending on the state of switch S1, capacitor C1 will be at Iin+ I1 or Iin-current charging of I2; the voltage across the capacitor C1 is compared and used to control the switch S1 by means of the control signal C to keep the average across the capacitor C1 equal to zero. Since the currents of I1 and I2 are assumed to be equal, the role of current source I3 is replaced by these current sources, which now serve as reference currents.
Thus, in both circuit 100 and circuit 300, the control loop feedback of switch S1 will keep the average value of the charge on the capacitor at zero, and in both circuit 100 and circuit 300, the control loop output is thus a measure of the input voltage in the usual way of operation of the sigma delta modulator. However, embodiments of circuit 300 do not require most of the components of the common mode feedback circuit of circuit 100, i.e., resistors R1 and R2, amplifier U1, and current sources I3, I4, and I5, while providing the normal mode voltage across capacitor C1 that is expected.
As described above, in the circuit 200 of fig. 2 and the circuit 100 of fig. 1, the noise present in the signal Iref or I3 is added to the noise of the two adjustable current sources, respectively. The common mode feedback circuit matches the absolute value of Iref to the sum of the two adjustable currents in circuit 200 and the sum of the currents I1 and I2 to the sum of the currents I3, I4 and I5 in circuit 100, but it does not reduce noise. In contrast, in the embodiment of circuit 300 of fig. 3, noise is reduced because there is no reference current. The only noise is that of currents I1 and I2. Therefore, the present embodiment removes components from the circuit and also reduces noise in the circuit because common mode control is not required.
As described above, the normal mode voltage across capacitor C1 in circuit 300 of fig. 3 is expected. However, in some cases, the voltage on each side of C1 may have a discontinuous odd waveform because the voltage ramps up to the common mode voltage or down to ground.
Fig. 4 illustrates another embodiment in which additional components may be added to the circuit 300 to avoid these discontinuities while preserving the two advantages of the circuit 300, namely the lack of common mode control and noise reduction. In the circuit 400, transistors M3, M4, M5, and M6 are added to the configuration of the circuit 300 so that when a differential current I is inputinWhen the current does not flow to the capacitor C1, the differential current I is inputinNo longer flows directly to ground through switch S1, but rather through some transistors.
Thus, when switch S1 is in place, the voltage on each side of capacitor C1 is no longer grounded, reaching the gate voltages of transistors M3-M6 operating at the current levels of the I1 and I2 sources.
When the switch S1 is in the position shown in fig. 4, current from transistor M2 cannot flow into either transistor M4 or M6 because their sources are off. This current cannot enter the gate of transistor M5. Therefore, all current from M2 must flow into capacitor C1, as in circuit 300 of fig. 3.
The transistor M3 is diode-connected, i.e., its gate and drain are connected. Its threshold voltage is therefore the threshold voltage of transistor M6. When the switch S1 changes position, all current from the transistor M2 will be pulled to the transistor M6 and thus to ground, but the voltage to the right of the capacitor C1 will reach the threshold voltage instead of ground, while the voltage on the capacitor C1 will remain at the normal mode voltage.
The circuit 400 is how the differential current I is input in the present embodimentinTo a low impedance (ground in these examples) or allowed to flow in a capacitor. As long as all currents are switched in this way, the noise in the circuit remains low. If the current is not all directed to the low impedance node or allowed to charge the capacitor, there is additional noise due to the splitting of the current into two parts.
For example, if the circuit is configured to allow alternately 80% of the current to flow to the capacitor and 20% to ground, followed by 20% to the capacitor and 80% to ground, there will be additional noise due to the implementation of the means to divide the current into 80% and 20% portions. This emphasises the fact that the present embodiment is characterized firstly by the absence of a separate reference source, and secondly by the fact that 100% of the current is directed to the feedback means.
Fig. 5 shows an alternative embodiment of fig. 4, in which the input voltage source VSIG1 is replaced by an input current source ISIG 1. In the embodiments of fig. 3 and 4, the differential current I is inputinAs in the prior art of fig. 1 and 2, by a well-known prior art V-to-I converter. Due to input differential current IinOnly the difference between the currents from the drains of transistors M1 and M2, so the differential current I is inputinAs shown in the circuit 500 of fig. 5, the input current source ISIG1 between the V to I devices may be generated from an input voltage source instead of from an input voltage source. Similarly, the input voltage source VSIG1 in the circuit 300 of fig. 3 may be replaced by an input current source.
By combining these features, a Σ Δ modulator can be constructed that reduces both the number of components and the amount of noise present. Those skilled in the art will appreciate that sigma delta modulators of any order may be constructed according to these principles.
The disclosed system has been described above with reference to several embodiments. Other embodiments will be apparent to those skilled in the art in view of this disclosure. Certain aspects of the described methods and apparatus may be readily implemented using configurations other than those described in the above-described embodiments, or in conjunction with elements other than, or in addition to, those described above.
For example, various options will be apparent to those skilled in the art, as are well known to those skilled in the art. Further, the illustration of transistors and associated feedback loops, resistors, etc. is exemplary; those skilled in the art will be able to select an appropriate number of transistors and associated components as appropriate for a particular application.
These and other variations to the embodiments are intended to be covered by the present disclosure, which is limited only by the appended claims.

Claims (6)

1. An apparatus for improving performance of a Σ Δ modulator, comprising:
a voltage-to-current converter comprising:
a first transistor and a second transistor, each transistor having a gate, a source, and a drain;
an input signal source connected between the gate of the first transistor and the gate of the second transistor and providing an input signal;
a resistor connected between the source of the first transistor and the source of the second transistor;
a first current source connected to a source of the first transistor and to a power supply;
a second current source connected to the source of the second transistor and to a power supply;
wherein there is a difference between a current from the drain of the first transistor and a current from the drain of the second transistor, the difference between the currents being representative of the input signal;
a capacitor connected between the drain of the first transistor and the drain of the second transistor;
a switch connected to the drain of the first transistor and the drain of the second transistor and having two positions, a first position connecting the drain of the first transistor to ground and leaving the drain of the second transistor unconnected to the ground, and a second position connecting the drain of the second transistor to the ground and leaving the drain of the first transistor unconnected to the ground; and
a control circuit that measures the voltage across the capacitor and causes the switch to change between the two positions so that the average value of the charge on the capacitor remains zero.
2. The apparatus of claim 1, wherein the input signal source is a voltage source.
3. The apparatus of claim 1, wherein the input signal source is a current source.
4. An apparatus for improving performance of a Σ Δ modulator, comprising:
a voltage-to-current converter comprising:
a first transistor and a second transistor, each transistor having a gate, a source, and a drain;
an input signal source connected between the gate of the first transistor and the gate of the second transistor;
a resistor connected between the source of the first transistor and the source of the second transistor;
a first current source connected to a source of the first transistor and to a power supply;
a second current source connected to the source of the second transistor and to a power supply;
wherein there is a difference between a current from the drain of the first transistor and a current from the drain of the second transistor, the difference between the currents being representative of an input signal;
a capacitor connected between the drain of the first transistor and the drain of the second transistor;
a third transistor having a gate, a source, and a drain, the drain and the gate being connected to the drain of the first transistor;
a fourth transistor having a gate, a source, and a drain connected to the drain of the first transistor;
a fifth transistor having a gate, a source, and a drain, the drain and the gate being connected to the drain of the second transistor and the gate of the fourth transistor;
a sixth transistor having a gate, a source, and a drain, the drain being connected to the drain of the second transistor and the gate of the fifth transistor, and the gate of the sixth transistor being connected to the gate of the third transistor;
a switch connected to the source of the third transistor, the source of the fourth transistor, the source of the fifth transistor, and the source of the sixth transistor and having two positions, a first position connecting the source of the third transistor and the source of the fourth transistor to ground and not connecting the source of the fifth transistor and the source of the sixth transistor to the ground, and a second position connecting the source of the fifth transistor and the source of the sixth transistor to the ground and not connecting the source of the third transistor and the source of the fourth transistor to the ground; and
a control circuit that measures the voltage across the capacitor and causes the switch to change between the two positions so that the average value of the charge on the capacitor remains zero.
5. The apparatus of claim 4, wherein the input signal source is a voltage source.
6. The apparatus of claim 4, wherein the input signal source is a current source.
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US16/454,010 US10637496B2 (en) 2018-06-28 2019-06-26 Low noise quantized feedback configuration

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US5699386A (en) * 1994-04-19 1997-12-16 Gec Plessey Semiconductors, Inc. System and method for data signal communication using a high-pass function before a low-pass function with quantized feedback technique
CN1547804A (en) * 2000-07-07 2004-11-17 �ʼҷ����ֵ������޹�˾ Sigma-delta modulator with an adjustable feedback factor
CN1832333A (en) * 2006-04-14 2006-09-13 清华大学 CMOS digital control LC oscillator on chip
CN101056090A (en) * 2007-04-06 2007-10-17 清华大学 Low-noise digital control LC oscillator using the back-to-back serial MOS varactor
CN107070456A (en) * 2015-09-15 2017-08-18 联发科技股份有限公司 Current D-A conveter and the method for converting digital signals into analog signal
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