CN110647493A - Data transmission method, processor and PCIE system - Google Patents

Data transmission method, processor and PCIE system Download PDF

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CN110647493A
CN110647493A CN201810672242.3A CN201810672242A CN110647493A CN 110647493 A CN110647493 A CN 110647493A CN 201810672242 A CN201810672242 A CN 201810672242A CN 110647493 A CN110647493 A CN 110647493A
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address
processor
data
shared
transmitted
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CN110647493B (en
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胡朝新
刘江浩
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Datang Mobile Communications Equipment Co Ltd
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Datang Mobile Communications Equipment Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Abstract

The embodiment of the invention relates to the technical field of communication, in particular to a data transmission method, a processor and a PCIE system, which are used for solving the problem of low data transmission efficiency. The first address field of the first processor address space and the preset address field of the PCIE bus domain address space have a first mapping relation, and the second address field of the second processor address space and the preset address field of the PCIE bus domain address space have a second mapping relation. If the first processor has a data transmission requirement, acquiring first address information; the first address information is used to indicate the addresses of available data carriers in a predetermined address field; determining a shared address used for storing data to be transmitted in a preset address segment according to the first address information; and writing the data to be transmitted into the storage area indicated by the shared address. Therefore, the second processor can access the storage area corresponding to the shared address without copying the data to be transmitted to the address space of the second processor, and the data transmission efficiency can be improved.

Description

Data transmission method, processor and PCIE system
Technical Field
The embodiment of the invention relates to the technical field of communication, in particular to a data transmission method, a processor and a PCIE system.
Background
Peripheral Component Interconnect Express (PCIE) bus is used as a local bus, and currently, a PCIE bus is required between processors in most multiprocessor communication systems to perform data transmission. Compared with other data communication modes, such as ethernet, Inter-integrated circuit (I2C for short), Serial Peripheral Interface (SPI for short), Local process Call (LPC for short), etc., a PCIE link can increase bandwidth and be in a point-to-point communication mode according to system design requirements, thereby ensuring the security of a data link and the real-time performance of large data transmission, and therefore, the PCIE link has important applications.
Taking TD-LTE or TDD-LTE base station system as an example, when PCIE is used between base station multiprocessors for data transmission, a data copy process occurs many times during the data transmission process, and a Central Processing Unit (CPU) is used for a serious time, so that other real-time data cannot be processed by the CPU. In the prior art, if the processor a needs to transmit data to the processor B, the adopted scheme is as follows: the processor A copies the data to be transmitted in the address space of the processor A to the address space of the PCIE bus domain, and then informs the processor B, and the processor B copies the data to be transmitted to the address space of the processor B from the address space of the PCIE bus domain. The two copying operations affect the processing of real-time data, and especially when the amount of data to be transmitted is large, the effect is more obvious, and even the base station system is broken down when the amount is serious.
Disclosure of Invention
The embodiment of the invention provides a data transmission method, a processor and a PCIE system, which are used for solving the problem of low data transmission efficiency.
In a first aspect, an embodiment of the present invention provides a data transmission method, where a first address field of an address space of a first processor and a preset address field of an address space of a PCIE bus domain have a first mapping relationship, and a second address field of an address space of a second processor and a preset address field of an address space of a PCIE bus domain have a second mapping relationship. Therefore, the first address field and the second address field are mapped to the preset address field of the same PCIE bus domain address space, the first processor can access the address in the preset address field through the first address field, and the second processor can also access the address in the preset address field through the second address field.
If the first processor has a data transmission requirement, the first processor obtains first address information, and the first address information is used for indicating the addresses of the available data carriers in the preset address field. And the first processor determines a shared address used for storing the data to be transmitted in the preset address segment according to the first address information. The shared address is used for the first processor to determine a first address in a first address field corresponding to the shared address according to the first mapping relation, and is used for the second processor to determine a second address in a second address field corresponding to the shared address according to the second mapping relation. And the first processor writes the data to be transmitted into the storage area indicated by the shared address. Therefore, when the first processor transmits data to the second processor, only the data to be transmitted needs to be written into the shared address, the second processor can directly access the storage area corresponding to the shared address, the second processor does not need to copy the data to be transmitted into the address space of the second processor, and the data transmission efficiency can be improved.
Optionally, the PCIE bus domain address space includes a first data structure, configured to indicate a state of each data carrier in the preset address segment; the first processor acquires first address information, and comprises: if the first processor determines that at least one continuous data carrier in the preset address field is in an idle state according to the first data structure, the first processor takes the at least one continuous data carrier in the idle state as a group of available data carriers; the first processor uses the addresses of each group of available data carriers in the preset address field as first address information.
By means of the embodiment, one or more groups of available data carriers are determined according to the first data structure, the first address information is determined, and since the first data structure indicates the state of each data carrier in the preset address segment, the available data carriers in the idle state can be rapidly determined, and therefore the efficiency of determining the first address information is high.
Optionally, the determining, by the first processor, the shared address used for storing the data to be transmitted in the preset address segment according to the first address information includes: and the first processor determines the addresses of a group of available data carriers with the total capacity larger than the data quantity of the data to be transmitted and the minimum difference value with the data quantity of the data to be transmitted from the preset address section according to the first address information, and the addresses serve as shared addresses for storing the data to be transmitted. Therefore, the available data carriers can be utilized to the maximum extent, so that each group of available data carriers bears the data to be transmitted with the minimum difference value between the data volume and the total capacity of the group of data carriers, and further resource waste is avoided.
Optionally, the PCIE bus domain address space includes a message queue, where the message queue is used to buffer address offsets corresponding to the shared address; after the first processor writes the data to be transmitted into the storage area indicated by the shared address, the method further includes: the first processor stores the address offset corresponding to the shared address in a message queue; the address offset is used by the second processor to determine a second address in a second address field corresponding to the shared address.
By the example, the conversion time delay from the shared address to the second address can be shortened, the second processor can finish the conversion from the second address to the shared address while the first processor sends a piece of data to be transmitted and caches the information related to the shared address to the message queue, and the data synchronization function is realized.
Optionally, the PCIE bus domain address space further includes a second data structure and a third data structure; the second data structure is used for recording the currently stored message sequence number in the message queue, and the third data structure is used for recording the currently deleted message sequence number in the message queue; after the first processor writes the data to be transmitted into the storage area indicated by the shared address, the method further includes: the first processor sends an interrupt message to the second processor; the interrupt message is used for triggering the second processor to determine the number of the messages left in the message queue according to the second data structure and the third data structure, so that the second processor acquires the address offset stored in the message queue when the number of the messages is determined to be larger than zero. Therefore, the second processor is informed of storing new data to be transmitted in the PICE bus domain address space by the way that the first processor sends the interrupt message to the second processor, so that the second processor can process the data to be transmitted in the PICE bus domain address space in time.
In a second aspect, an embodiment of the present invention provides a data transmission method, where a first address field of an address space of a first processor and a preset address field of an address space of a PCIE bus domain have a first mapping relationship, and a second address field of an address space of a second processor and a preset address field of an address space of a PCIE bus domain have a second mapping relationship; the method comprises the following steps: the second processor acquires a shared address for storing data to be transmitted; the shared address is an address in a preset address segment; the second processor determines a second address in a second address field corresponding to the shared address according to the shared address and the second mapping relation; and the second processor accesses the data to be transmitted stored in the shared address through the second address.
According to the embodiment, when the second processor receives the data transmitted by the first processor, because the second address field of the second processor has the second mapping relation with the preset address field, the data to be transmitted is written into the shared address in the preset address field, the second processor can access the storage area corresponding to the shared address through the second address in the second address field corresponding to the shared address, and directly perform task processing on the data to be transmitted in the storage area corresponding to the shared address, and the second processor is not required to copy the data to be transmitted into the address space of the second processor, so that the data transmission efficiency can be improved.
Optionally, the PCIE bus domain address space includes a message queue, where the message queue is used to buffer address offsets corresponding to the shared address; the second processor acquires a shared address for storing data to be transmitted, and the method comprises the following steps: the second processor acquires the address offset corresponding to the shared address from the message queue; and the second processor determines the shared address according to the address offset corresponding to the shared address and the initial address of the preset address field.
Optionally, the PCIE bus domain address space further includes a second data structure and a third data structure; the second data structure is used for recording the currently stored message sequence number in the message queue, and the third data structure is used for recording the currently deleted message sequence number in the message queue; before the second processor obtains the address offset corresponding to the shared address from the message queue, the method further includes: the second processor receives an interrupt message sent by the first processor; the second processor determines the number of the messages left in the message queue according to the second data structure and the third data structure; the second processor obtains an address offset corresponding to the shared address from the message queue, and the method comprises the following steps: if the second processor determines that the number of the messages is larger than zero, the second processor obtains the address offset corresponding to the shared address from the message queue; the second processor deletes the address offset corresponding to the shared address from the message queue. In this manner, the second processor can shorten the time to determine the second address by retrieving the address offset from the message queue.
In a third aspect, an embodiment of the present invention provides a first processor, configured to perform the method in any of the first aspect and the first aspect; a first mapping relation exists between a first address field of a first processor address space and a preset address field of a PCIE bus domain address space, and a second mapping relation exists between a second address field of a second processor address space and the preset address field of the PCIE bus domain address space; the first processor includes: the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is used for acquiring first address information if the first processor has a data transmission requirement; the first address information is used to indicate the addresses of available data carriers in a predetermined address field; the processing unit is used for determining a shared address used for storing data to be transmitted in a preset address segment according to the first address information; the shared address is used for the processing unit to determine a first address in a first address field corresponding to the shared address according to the first mapping relation, and is used for the second processor to determine a second address in a second address field corresponding to the shared address according to the second mapping relation; and the writing unit is used for writing the data to be transmitted into the storage area indicated by the shared address.
In a fourth aspect, an embodiment of the present invention provides a second processor, configured to perform the method in any of the second and third aspects; a first mapping relation exists between a first address field of a first processor address space and a preset address field of a PCIE bus domain address space, and a second mapping relation exists between a second address field of a second processor address space and the preset address field of the PCIE bus domain address space; the second processor includes: the device comprises an acquisition unit, a transmission unit and a processing unit, wherein the acquisition unit is used for acquiring a shared address used for storing data to be transmitted; the shared address is an address in a preset address segment; the processing unit is used for determining a second address in a second address field corresponding to the shared address according to the shared address and the second mapping relation; and the access unit is used for accessing the data to be transmitted stored in the shared address through the second address.
In a fifth aspect, an embodiment of the present invention provides a PCIE system, including the first processor in any embodiment and the second processor in any embodiment.
In a sixth aspect, an embodiment of the present invention provides a computer device, including:
a memory for storing program instructions;
a processor for calling the program instructions stored in the memory, executing the method according to the first aspect or any embodiment of the first aspect, or executing the method according to the second aspect or any embodiment of the second aspect.
In a seventh aspect, the present invention provides a computer-readable storage medium, which stores computer-executable instructions for causing a computer to perform the method according to any one of the first aspect and the first aspect, or perform the method according to any one of the second aspect and the second aspect.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that are required to be used in the description of the embodiments will be briefly described below.
Fig. 1 is a schematic diagram of a PCIE system architecture according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a data transmission method according to an embodiment of the present invention;
fig. 3 is a schematic flow chart of another data transmission method according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a message queue structure according to an embodiment of the present invention;
fig. 5 is a schematic flow chart of another data transmission method according to an embodiment of the present invention;
FIG. 6 is a block diagram of a first processor according to an embodiment of the present invention;
FIG. 7 is a block diagram of a second processor according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a computer device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the data transmission method based on PCIE in the prior art, between any two processors, the sending end copies source data in the address space of the local processor to the PCIE domain address space, and the receiving end copies source data in the PCIE domain address space to the address space of the local processor of the receiving end again, which is low in transmission efficiency. Especially, under the condition of large amount of transmitted data, two data copying operations seriously affect the processing of real-time data and even lead to the paralysis of a base station system.
In order to solve the above problems, in the implementation of the present invention, a PCIE bus domain address space is simulated as a shared memory pool between processors, and a sending end processor and a receiving end processor are respectively mapped to the same address space of the shared memory pool, thereby implementing mapping transmission of data between the two processors. The data transmission method provided by the embodiment of the invention is suitable for the base station for PCIE data transmission among the multiple processors.
Fig. 1 exemplarily shows a schematic architecture of a PCIE system applicable to the embodiment of the present invention, where the PCIE system includes at least two processors, and as shown in fig. 1, the PCIE system 100 includes a first processor 110, a second processor 120, and a PCIE controller 130.
Before data transmission is performed between the first processor 110 and the second processor 120, the PCIE controller 130 establishes a first mapping relationship between a first address segment in an address space of the first processor 110 and a preset address segment in an address space of a PCIE bus domain, and establishes a second mapping relationship between a second address segment in an address space of the second processor 120 and a preset address segment in an address space of a PCIE bus domain. That is to say, the first address field and the second address field are mapped to a preset address field of the same PCIE bus domain address space, the first processor 110 may access an address in the preset address field through the first address field, and the second processor 120 may also access an address in the preset address field through the second address field.
Based on the system architecture shown in fig. 1, fig. 2 exemplarily shows a flow diagram of a data transmission method provided by an embodiment of the present invention.
In the data transmission method provided in the embodiment of the present invention, a first address field of an address space of a first processor and a preset address field of an address space of a PCIE bus domain have a first mapping relationship, and a second address field of an address space of a second processor and a preset address field of an address space of a PCIE bus domain have a second mapping relationship. Therefore, the first address field and the second address field are mapped to the preset address field of the same PCIE bus domain address space, the first processor can access the address in the preset address field through the first address field, and the second processor can also access the address in the preset address field through the second address field. As shown in fig. 2, the method comprises the steps of:
in step 201, if there is a data transmission requirement for the first processor, the first processor obtains first address information, where the first address information is used to indicate addresses of available data carriers in a preset address segment.
In this step 201, the PCIE bus domain address space includes at least one data carrier for carrying data, and the data capacity that each data carrier can carry is the same. The usable data carrier is an unoccupied data carrier, i.e. a data carrier in an idle state.
Step 202, the first processor determines a shared address used for storing data to be transmitted in a preset address segment according to the first address information. The shared address is used for the first processor to determine a first address in a first address field corresponding to the shared address according to the first mapping relation, and is used for the second processor to determine a second address in a second address field corresponding to the shared address according to the second mapping relation.
In step 203, the first processor writes the data to be transmitted into the storage area indicated by the shared address.
According to the embodiment, when the first processor transmits data to the second processor, only the data to be transmitted needs to be written into the shared address, the second processor can directly access the storage area corresponding to the shared address and directly perform task processing on the data to be transmitted in the storage area corresponding to the shared address, the second processor does not need to copy the data to be transmitted into the address space of the second processor, and therefore the data transmission efficiency can be improved.
Based on the system architecture shown in fig. 1 and fig. 2, fig. 3 schematically illustrates another flow chart of a data transmission method provided by the embodiment of the present invention. The first address field of the first processor address space and the preset address field of the PCIE bus domain address space have a first mapping relation, and the second address field of the second processor address space and the preset address field of the PCIE bus domain address space have a second mapping relation. As shown in fig. 3, the method comprises the steps of:
step 301, a second processor acquires a shared address for storing data to be transmitted; the shared address is an address in the preset address field.
Step 302, the second processor determines a second address in a second address field corresponding to the shared address according to the shared address and the second mapping relationship.
Step 303, the second processor accesses the data to be transmitted stored in the shared address through the second address.
According to the embodiment, when the second processor receives the data transmitted by the first processor, because the second address field of the second processor has the second mapping relation with the preset address field, the data to be transmitted is written into the shared address in the preset address field, the second processor can access the storage area corresponding to the shared address through the second address in the second address field corresponding to the shared address, and directly perform task processing on the data to be transmitted in the storage area corresponding to the shared address, and the second processor is not required to copy the data to be transmitted into the address space of the second processor, so that the data transmission efficiency can be improved.
In the embodiment of the present invention, in order to improve the data transmission efficiency, the PCIE domain address space includes a data structure for managing data, including PiData Structure, CiData structure, Padding data structure, PXData Structure, AXData Structure, BXA data structure.
PiAnd the data structure is used for managing sending data, and the Pi (producer) data structure is increased progressively every time the sending end sends the PCIE data message. Optionally, PiData structure after sending data P at sending endiThe data structure value is changed incrementally; read-only P when receiving data at receiving endiData structure value, does not change PiA data structure value. P as shown in Table 1 belowi。
TABLE 1 data Structure
Pi Ci Padding Padding Padding
P1 P2 P3 P4 P5
P6 P7 P8 P9 PN
A1 A2 A3 A4 A5
A6 A7 A8 A9 AN
B1 B2 B3 B4 B5
B6 B7 B8 B9 BN
CiAnd a data structure for managing received data, wherein the Ci (consumer) data structure is incremented each time the second processor receives a PCIE data message. Optionally, CiData structure read-only when transmitting data at receiving endiData structure value, does not change CiA data structure value; after receiving data by receiving end CiData structure value changed increment. C as shown in Table 1 abovei。
And the Padding data structure is used for ensuring that the address of the data structure is aligned with the extension reserved data bits.
PXA data structure, configured to organize a PCIE data message queue for circular transceiving, as shown in the schematic diagram of a circular message queue structure shown in fig. 4. Each PXThe value identifies an address to which a data message is to be sent, and stores the address of the data to be sent in P when the sender sends the dataXReleasing P when receiving data at the receiving endX. Optionally, PXIs an array of pointers, each element value pointing to an address corresponding to a transmitted data. P as shown in Table 1 above1、P2、……、P9、……、PN。
AXData structure for identifying BX(data carrier) state, X being an integer greater than 0. A as shown in Table 1 above1、A2、……、A9、……、AN。
BXData structure for carrying data messages for transmission, each BXThe size of the data carried is the same, and the specific size of the data carried can be set according to actual requirements, for example, set to 1024 bytes. A BXCorresponds to aXData Structure, implementation BXAnd A ofXIn a one-to-one correspondence. B as shown in Table 1 above1、B2、……、B9、……、BN。
Before step 201, available data carriers may be determined, wherein consecutive available data carriers are used as a set of available data carriers, i.e. each set of available data carriers comprises at least one consecutive available data carrier. The PCIE bus domain address space includes a first data structure for indicating a status of each data carrier in the preset address segment. The first data structure may be aXA data structure.
In step 201, if the first processor determines that there is at least one idle and continuous data carrier in the preset address field according to the first data structure, the first processor regards the at least one idle and continuous data carrier as a group of available data carriers.
In one example, several alternative implementations of the first processor determining the first address information are described, taking as an example the preset address field comprising M groups of available data carriers. Wherein M is an integer greater than 0.
In an alternative implementation the first processor determines the addresses of the M groups of available data carriers as the first address information.
In another alternative implementation, the first processor determines any one of the available data carriers from the M groups of available data carriers, and determines the address of the available data carrier as the first address information if the available data carrier group needs to satisfy a condition that the total capacity is greater than or equal to the data amount of the data to be transmitted.
In a further alternative implementation, K groups of available data carriers are determined from the M groups of available data carriers, the total capacity of the K groups of available data carriers being greater than or equal to the data amount of the data to be transmitted, and the address of the data amount of the data to be transmitted is determined as the first address information. Wherein K is an integer less than M.
By means of the embodiment, one or more groups of available data carriers are determined according to the first data structure, the first address information is determined, and since the first data structure indicates the state of each data carrier in the preset address segment, the available data carriers in the idle state can be rapidly determined, and therefore the efficiency of determining the first address information is high.
Furthermore, the first processor may determine the shared address according to the first address information in various ways.
In an alternative embodiment, the first processor determines, from the preset address segment, at least one group of available data carriers each having a total capacity greater than the data amount of the data to be transmitted, and randomly determines one group of available data carriers from the at least one group of available data carriers, and uses the address of the one group of available data carriers as a shared address for storing the data to be transmitted.
In another optional embodiment, the first processor determines, from the preset address segment, addresses of a group of available data carriers, which have a total capacity greater than the data amount of the data to be transmitted and a minimum difference value with the data amount of the data to be transmitted, according to the first address information, and uses the addresses as shared addresses for storing the data to be transmitted. Therefore, the available data carriers can be utilized to the maximum extent, so that each group of available data carriers bears the data to be transmitted with the minimum difference value between the data volume and the total capacity of the group of data carriers, and further resource waste is avoided.
If the total capacity of each group of available data carriers is smaller, in order to avoid the problem that the shared address cannot be determined because the total capacity of one group of available data carriers is larger than the data volume of the data to be transmitted, several groups of available data carriers with the total capacity larger than the data volume of the data to be transmitted can be determined from the preset address segment, and the determined addresses of the several groups of available data carriers with the total capacity larger than the data volume of the data to be transmitted are used as the shared address for storing the data to be transmitted. Therefore, each data to be transmitted can be ensured to determine an available data carrier, and the problem that the data to be transmitted cannot be transmitted in time is avoided.
After step 203, how the second processor obtains the shared address, an alternative embodiment is provided below, where the PCIE bus domain address space includes a message queue, and the second processor obtains the shared address by buffering information related to the shared address in the message queue. The following are two examples:
in one example, a first processor caches a shared address in a message queue, and correspondingly, a second processor directly obtains the shared address from the message queue, and further accesses to-be-transmitted data in a storage area corresponding to the shared address through a second address corresponding to the shared address.
In another example, the message queue is configured to buffer an address offset corresponding to a shared address, where the address offset corresponding to the shared address is an offset of the shared address with respect to an initial address of a preset address segment. That is, after step 203, the first processor stores the address offset corresponding to the shared address in the message queue; the address offset is used by the second processor to determine a second address in a second address field corresponding to the shared address.
Correspondingly, the second processor acquires the address offset corresponding to the shared address from the message queue; and the second processor determines the shared address according to the address offset corresponding to the shared address and the initial address of the preset address field, and further accesses the data to be transmitted in the storage area corresponding to the shared address through the second address corresponding to the shared address.
By the example, the conversion time delay from the shared address to the second address can be shortened, the second processor can finish the conversion from the second address to the shared address while the first processor sends a piece of data to be transmitted and caches the information related to the shared address to the message queue, and the data synchronization function is realized.
Optionally, the PCIE bus domain address space further includes a second data structure and a third data structure; the second data structure is used for recording the message sequence number currently stored in the message queue, namely the PiData structure, P as shown in FIG. 4i(ii) a The third data structure is used for recording the currently deleted message sequence number in the message queue, namely CiData structure, C as shown in FIG. 4i；。
After step 203, the first processor sends an interrupt message to the second processor; the interrupt message is used for triggering the second processor to determine the number of the messages left in the message queue according to the second data structure and the third data structure, so that the second processor acquires the address offset stored in the message queue when the number of the messages is determined to be larger than zero. Therefore, the second processor is informed of storing new data to be transmitted in the PICE bus domain address space by the way that the first processor sends the interrupt message to the second processor, so that the second processor can process the data to be transmitted in the PICE bus domain address space in time.
Correspondingly, before the second processor acquires the address offset corresponding to the shared address from the message queue, the method further includes: and the second processor receives the interrupt message sent by the first processor, and determines the number of the messages left in the message queue according to the second data structure and the third data structure. Specifically, the second processor may determine the number of remaining messages in the message queue according to a difference between the sequence number recorded in the second data structure and the sequence number recorded in the third data structure. If the number of the messages is larger than zero, indicating that unprocessed data to be transmitted still exist in the message queue; and if the number of the messages is less than or equal to zero, indicating that the unprocessed data to be transmitted does not exist in the message queue.
Further, the obtaining, by the second processor, an address offset corresponding to the shared address from the message queue includes: if the second processor determines that the number of the messages is larger than zero, the second processor obtains the address offset corresponding to the shared address from the message queue; and the second processor deletes the address offset corresponding to the shared address from the message queue, and further determines a second address corresponding to the shared address according to the address offset, so that the data to be transmitted in the storage area corresponding to the shared address is accessed through the second address corresponding to the shared address. In this manner, the second processor can shorten the time to determine the second address by retrieving the address offset from the message queue.
To more clearly describe the data transmission method, the following examples are provided in the embodiments of the present invention.
Fig. 5 is a schematic method flow diagram illustrating another data transmission method according to an embodiment of the present invention. As shown in fig. 5, the method comprises the steps of:
in step 501, the first processor determines the size of the data to be transmitted and each data carrier BXCapacity of (2), Y successive B's are required for calculationX。
Step 502, the first processor traverses AXA data structure for determining whether there is at least one group of continuous B in preset address and the number of B in idle state is more than YX(ii) a If yes, go to step 503; if not, no BX is available for carrying data.
In step 503, the first processor determines a set of consecutive B's that are in an idle state and have a number greater than YXAnd combining the group BXAs a shared address.
Step 504, the first processor writes the data to be transmitted to the B indicated by the shared addressXIn (1).
In step 505, the first processor stores the address offset of the shared address in a message queue, PiThe serial number of the record is incremented by one.
At step 506, the first processor sends an interrupt message to the second processor.
In step 507, the second processor receives the interrupt message.
Step 508, the second processor determines CiWhether the difference between the recorded sequence number and the sequence number recorded by Pi is greater than zero; if yes, go to step 509; if not, go to step 510.
Step 509, through message queue PXIndexing an address offset in a message queue, removing the address offset from the message queue after indexing to the address offset, CiAdding one; execution continues with step 508.
Step 510 stops fetching address offsets from the message queue.
The data transmission method provided by the embodiment has data backtracking, and each data to be transmitted has a corresponding counting statistic at a sending end (a first processor) and a receiving end (a second processor) of the communication system and states of the data to be transmitted at each stage, so that the data can be ensured not to be lost during high data throughput, and message accumulation caused by slow processing bottleneck can not occur to time-efficient messages with higher requirements.
Fig. 6 illustrates a schematic structural diagram of a first processor according to an embodiment of the present invention.
Based on the same concept, in a first processor provided in an embodiment of the present invention, for executing a method flow executed by the first processor in the foregoing embodiment, a first mapping relationship exists between a first address field of an address space of the first processor and a preset address field of an address space of a PCIE bus domain, and a second mapping relationship exists between a second address field of an address space of a second processor and a preset address field of an address space of a PCIE bus domain. As shown in fig. 6, the first processor 600 includes an acquisition unit 601, a processing unit 602, and a writing unit 603; optionally, the system further comprises a storage unit 604 and a sending unit 605; wherein:
an obtaining unit 601, configured to obtain first address information if there is a data transmission need in the first processor; the first address information is used to indicate the addresses of available data carriers in a predetermined address field;
a processing unit 602, configured to determine, according to the first address information, a shared address used for storing data to be transmitted in a preset address segment; the shared address is used for the processing unit 602 to determine a first address in a first address field corresponding to the shared address according to the first mapping relationship, and is used for the second processor to determine a second address in a second address field corresponding to the shared address according to the second mapping relationship; the writing unit 603 is configured to write the data to be transmitted into the storage area indicated by the shared address.
Optionally, the PCIE bus domain address space includes a first data structure, configured to indicate a state of each data carrier in the preset address segment; an obtaining unit 601, configured to: if at least one data carrier which is in an idle state and continuous exists in the preset address field is determined according to the first data structure, the at least one data carrier which is in the idle state and continuous is used as a group of available data carriers; the address of each group of available data carriers in the preset address field is taken as the first address information.
Optionally, the processing unit 602 is configured to: and determining a group of addresses of the available data carriers with the total capacity larger than the data volume of the data to be transmitted and the minimum difference value with the data volume of the data to be transmitted from the preset address section according to the first address information, wherein the group of addresses serve as shared addresses for storing the data to be transmitted.
Optionally, the PCIE bus domain address space includes a message queue, where the message queue is used to buffer address offsets corresponding to the shared address; the first processor further comprises a memory unit 604 for: storing the address offset corresponding to the shared address in a message queue; the address offset is used by the second processor to determine a second address in a second address field corresponding to the shared address.
Optionally, the PCIE bus domain address space further includes a second data structure and a third data structure; the second data structure is used for recording the currently stored message sequence number in the message queue, and the third data structure is used for recording the currently deleted message sequence number in the message queue; the first processor further comprises a sending unit 605 for: sending an interrupt message to the second processor; the interrupt message is used for triggering the second processor to determine the number of the messages left in the message queue according to the second data structure and the third data structure, so that the second processor acquires the address offset stored in the message queue when the number of the messages is determined to be larger than zero.
For the concepts, explanations, detailed descriptions and other steps related to the technical solutions provided by the embodiments of the present invention related to the first processor, reference is made to the foregoing data transmission method or descriptions related to these contents in other embodiments, which are not described herein again.
Fig. 7 is a schematic structural diagram illustrating a second processor according to an embodiment of the present invention.
Based on the same concept, in a second processor provided in an embodiment of the present invention, for executing a method flow executed by the second processor in the foregoing embodiment, a first address field of an address space of a first processor and a preset address field of an address space of a PCIE bus domain have a first mapping relationship, and a second address field of the address space of the second processor and the preset address field of the address space of the PCIE bus domain have a second mapping relationship. As shown in fig. 7, the second processor 700 includes an obtaining unit 701, a processing unit 702, and an accessing unit 703; optionally, a receiving unit 704 is further included; wherein:
an obtaining unit 701, configured to obtain a shared address used for storing data to be transmitted; the shared address is an address in a preset address segment; a processing unit 702, configured to determine a second address in a second address field corresponding to the shared address according to the shared address and the second mapping relationship; an accessing unit 703 is configured to access, through the second address, the to-be-transmitted data stored in the shared address.
Optionally, the PCIE bus domain address space includes a message queue, where the message queue is used to buffer address offsets corresponding to the shared address; an obtaining unit 701 configured to: acquiring an address offset corresponding to the shared address from the message queue; and determining the shared address according to the address offset corresponding to the shared address and the initial address of the preset address field.
Optionally, the PCIE bus domain address space further includes a second data structure and a third data structure; the second data structure is used for recording the currently stored message sequence number in the message queue, and the third data structure is used for recording the currently deleted message sequence number in the message queue; the second processor further comprises a receiving unit 704 for: receiving an interrupt message sent by a first processor; a processing unit 702 configured to: determining the number of the remaining messages in the message queue according to the second data structure and the third data structure; an obtaining unit 701 configured to: if the message quantity is larger than zero, the second processor acquires the address offset corresponding to the shared address from the message queue; a processing unit 702 configured to: and deleting the address offset corresponding to the shared address from the message queue.
For the concepts, explanations, detailed descriptions and other steps related to the technical solutions provided by the embodiments of the present invention related to the second processor, reference is made to the foregoing data transmission method or descriptions related to these contents in other embodiments, which are not described herein again.
Based on the same concept, a PCIE system provided in the embodiment of the present invention includes the first processor 600 and the second processor 700 in the foregoing embodiment. The first address field of the first processor address space and the preset address field of the PCIE bus domain address space have a first mapping relation, and the second address field of the second processor address space and the preset address field of the PCIE bus domain address space have a second mapping relation.
For the concepts, explanations, detailed descriptions and other steps related to the first processor and the second processor related to the technical solution provided by the embodiment of the present invention, please refer to the foregoing data transmission method or the descriptions related to these contents in other embodiments, which are not described herein again.
Based on the above embodiments and the same concept, the embodiments of the present invention also provide a computer device.
Fig. 8 is a schematic structural diagram of a computer device according to an embodiment of the present invention. As shown in fig. 8, the computer apparatus 800 includes:
a memory 801 for storing program instructions;
the processor 802 is configured to call the program instructions stored in the memory, and execute the data transmission method executed by the first processor or the data transmission method executed by the second processor according to any of the foregoing embodiments according to the obtained program.
Based on the above embodiments and the same concept, embodiments of the present invention further provide a computer storage medium, where computer-executable instructions are stored, and the computer-executable instructions are configured to enable a computer to execute a data transmission method executed by a first processor or a data transmission method executed by a second processor in any one of the foregoing embodiments.
It should be understood that the above division of each unit is only a division of a logic function, and the actual implementation may be wholly or partially integrated into one physical entity, or may be physically separated.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various modifications and variations can be made in the embodiments of the present invention without departing from the spirit and scope of the application. Thus, if such modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present application and their equivalents, the present application is also intended to encompass such modifications and variations.

Claims (13)

1. A data transmission method is characterized in that a first address field of a first processor address space has a first mapping relation with a preset address field of a PCIE bus domain address space, and a second address field of a second processor address space has a second mapping relation with the preset address field of the PCIE bus domain address space; the method comprises the following steps:
if the first processor has a data transmission requirement, the first processor acquires first address information; the first address information is used to indicate the addresses of available data carriers in the preset address field;
the first processor determines a shared address used for storing data to be transmitted in the preset address section according to the first address information; the shared address is used for the first processor to determine a first address in the first address field corresponding to the shared address according to the first mapping relation, and is used for the second processor to determine a second address in the second address field corresponding to the shared address according to the second mapping relation;
and the first processor writes the data to be transmitted into a storage area indicated by the shared address.
2. The method of claim 1, wherein the PCIE bus domain address space comprises a first data structure for indicating a status of each data carrier in the preset address segment;
the first processor acquires first address information, and the method comprises the following steps:
if the first processor determines that at least one data carrier which is in an idle state and continuous exists in the preset address field according to the first data structure, the first processor takes the at least one data carrier which is in the idle state and continuous as a group of available data carriers;
the first processor takes the address of each group of available data carriers in the preset address field as the first address information.
3. The method of claim 2, wherein the first processor determining, according to the first address information, a shared address for storing data to be transmitted in the preset address segment, comprises:
and the first processor determines a group of addresses of available data carriers, of which the total capacity is greater than the data volume of the data to be transmitted and the difference value with the data volume of the data to be transmitted is minimum, from the preset address section according to the first address information, and the addresses are used as the shared addresses for storing the data to be transmitted.
4. The method of claim 1, wherein the PCIE bus domain address space comprises a message queue, and the message queue is configured to buffer an address offset corresponding to the shared address;
after the first processor writes the data to be transmitted into the storage area indicated by the shared address, the method further includes:
the first processor stores an address offset corresponding to the shared address in the message queue; the address offset is used for the second processor to determine a second address in the second address field corresponding to the shared address.
5. The method of claim 1, wherein the PCIE bus domain address space further comprises a second data structure and a third data structure; the second data structure is used for recording the currently stored message sequence number in the message queue, and the third data structure is used for recording the currently deleted message sequence number in the message queue;
after the first processor writes the data to be transmitted into the storage area indicated by the shared address, the method further includes:
the first processor sends an interrupt message to a second processor; the interrupt message is used for triggering the second processor to determine the number of the messages left in the message queue according to the second data structure and the third data structure, so that the second processor acquires the address offset stored in the message queue when determining that the number of the messages is larger than zero.
6. A data transmission method is characterized in that a first address field of a first processor address space has a first mapping relation with a preset address field of a PCIE bus domain address space, and a second address field of a second processor address space has a second mapping relation with the preset address field of the PCIE bus domain address space; the method comprises the following steps:
the second processor acquires a shared address for storing data to be transmitted; the shared address is an address in the preset address field;
the second processor determines a second address in the second address field corresponding to the shared address according to the shared address and the second mapping relation;
and the second processor accesses the data to be transmitted stored in the shared address through the second address.
7. The method of claim 6, wherein the PCIE bus domain address space includes a message queue for buffering address offsets corresponding to the shared addresses; the second processor obtaining a shared address for storing data to be transmitted, including:
the second processor acquires an address offset corresponding to the shared address from the message queue;
and the second processor determines the shared address according to the address offset corresponding to the shared address and the initial address of the preset address field.
8. The method of claim 7, wherein the PCIE bus domain address space further comprises a second data structure and a third data structure; the second data structure is used for recording the currently stored message sequence number in the message queue, and the third data structure is used for recording the currently deleted message sequence number in the message queue;
before the second processor obtains the address offset corresponding to the shared address from the message queue, the method further includes:
the second processor receives an interrupt message sent by the first processor;
the second processor determines the number of messages remaining in the message queue according to the second data structure and the third data structure;
the second processor obtains an address offset corresponding to the shared address from the message queue, and the method includes:
if the second processor determines that the number of the messages is larger than zero, the second processor obtains an address offset corresponding to the shared address from the message queue;
and the second processor deletes the address offset corresponding to the shared address from the message queue.
9. A first processor arranged to perform the method of any of claims 1 to 5; a first mapping relation exists between a first address field of the first processor address space and a preset address field of a PCIE bus domain address space, and a second mapping relation exists between a second address field of a second processor address space and the preset address field of the PCIE bus domain address space; the first processor comprises:
the first processor is used for acquiring first address information if the first processor has a data transmission requirement; the first address information is used to indicate the addresses of available data carriers in the preset address field;
the processing unit is used for determining a shared address used for storing data to be transmitted in the preset address segment according to the first address information; the shared address is used for the processing unit to determine a first address in the first address field corresponding to the shared address according to the first mapping relation, and the second processor to determine a second address in the second address field corresponding to the shared address according to the second mapping relation;
and the writing unit is used for writing the data to be transmitted into the storage area indicated by the shared address.
10. A second processor arranged to perform the method of any of claims 6 to 8; a first mapping relation exists between a first address field of a first processor address space and a preset address field of a PCIE bus domain address space, and a second mapping relation exists between a second address field of a second processor address space and the preset address field of the PCIE bus domain address space; the second processor comprises:
the acquisition unit is used for acquiring a shared address for storing data to be transmitted; the shared address is an address in the preset address field;
the processing unit is configured to determine a second address in the second address field corresponding to the shared address according to the shared address and the second mapping relationship;
the access unit is configured to access the to-be-transmitted data stored in the shared address through the second address.
11. A PCIE system comprising the first processor of claim 9 and the second processor of claim 10.
12. A computer device, comprising:
a memory for storing program instructions;
a processor for calling program instructions stored in said memory, for performing the method of any of claims 1 to 5, or for performing the method of any of claims 6 to 8, in accordance with the obtained program.
13. A computer-readable storage medium storing computer-executable instructions for causing a computer to perform the method of any one of claims 1 to 5 or to perform the method of any one of claims 6 to 8.
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