CN110635801A - Injection locking clock frequency multiplier for suppressing reference stray - Google Patents
Injection locking clock frequency multiplier for suppressing reference stray Download PDFInfo
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
- H03L7/0997—Controlling the number of delay elements connected in series in the ring oscillator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
- H03L7/0998—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator using phase interpolation
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Abstract
The invention belongs to the technical field of integrated circuits, and particularly relates to an injection locking clock frequency multiplier for inhibiting reference stray. The invention comprises the following steps: the device comprises a frequency locking unit, a phase locking unit, a delay correction unit, an injection pulse generation circuit, an injection locking digital controlled oscillator and a clock and snapshot generation circuit; the frequency locking unit is used for controlling the frequency of the output clock signal; the phase locking unit is used for locking the frequency and the phase of the output clock signal; the delay correction unit is used for reducing the delay on the phase error path; injecting a locked digital controlled oscillator for generating an output high frequency clock signal; the clock and snapshot generating circuit is used for converting a high-frequency clock signal of the oscillator into a low-frequency snapshot signal. The invention generates a pulse signal by a reference clock signal, and the oscillator is locked at a target frequency by injecting the stable low-frequency pulse signal into the oscillator, phase locking and delay correction, and the output clock signal has lower phase noise and reference stray.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, and particularly relates to an injection locking clock frequency multiplier.
Background
Clock generation circuits are widely used in various circuit systems. An Injection-Locked Clock Multiplier (ILCM) is a Clock generation circuit that can lock to the frequency multiplication of a low-frequency signal and suppress phase noise in the low-frequency part of an oscillator by injecting a clean and stable low-frequency pulse signal into the oscillator, and can realize excellent jitter/phase noise performance with a simple system complexity, low power consumption, and low cost design. The output signal of the ILCM may be locked to an integer multiple of the frequency of the low frequency pulse signal, thus requiring an auxiliary frequency control loop to ensure that it is locked to the target frequency. In the ILCM, an error exists between the free oscillation frequency of the oscillator and the target frequency, and when the pulse signal is injected, the output of the injection locking clock frequency multiplier has abrupt phase change, and shows deterministic jitter in the time domain and shows reference spurs in the frequency domain, so that the application of the ILCM in many scenes is limited. The performance of the injection-locked clock frequency multiplier is also highly susceptible to degradation by PVT effects, since the error between the free-running frequency of the oscillator and the target frequency is very sensitive to process, supply voltage, and temperature (PVT) variations. In order to solve the above-mentioned problems caused by frequency errors, the auxiliary frequency control loop needs to accurately lock the frequency of the oscillator. In the prior art, frequency locking is usually achieved by phase locking, that is, a phase error between an output signal and an input reference clock signal is detected, and the frequency of an oscillator is adjusted to a target frequency by a negative feedback loop. If the feedback signal in the phase locking loop is a frequency-divided signal, the error detection circuit works at the frequency of the reference clock, and the noise in a system band is large; if a sub-sampling frequency discriminator is used in the loop, the in-band noise of the system can be reduced, but the error detection circuit needs to process the output signal of the oscillator with high frequency, which is usually up to more than several gigahertz, and the design difficulty is higher. On the other hand, there may be delay errors between different signal paths in the secondary frequency control loop, which may also cause phase jump at the injection time and deteriorate the performance.
In order to solve the problem of jitter/reference spurious introduced by a frequency error in an injection locking clock frequency multiplier, optimize system performance, expand application scenarios of the injection locking clock frequency multiplier, reduce design difficulty of an error detection circuit and improve system working efficiency, a person skilled in the relevant field expects to design a frequency control loop capable of being accurate and avoid introducing an additional delay error into the control loop.
Disclosure of Invention
The invention aims to provide an injection locking clock frequency multiplier capable of inhibiting reference stray, which is used for generating a frequency multiplication clock of a reference clock, and a control method.
The injection locking clock frequency multiplier provided by the invention at least comprises:
the frequency locking unit is used for comparing the output clock frequency of the output clock with the frequency control word and preliminarily controlling the frequency of the output clock signal;
the phase locking unit is used for comparing output phase signals with different delays, accurately locking the frequency and the phase of the output clock signal and suppressing reference stray;
the delay correction unit is used for reducing delay errors on different signal paths when the injection locking digital controlled oscillator outputs to the phase locking unit;
the injection pulse generating circuit is used for generating a pulse signal from a reference clock, injecting the pulse signal into the injection locking digital controlled oscillator and inhibiting the low-frequency noise of the oscillator;
injecting a locked digital controlled oscillator for generating an output high frequency clock signal;
and the clock and snapshot generating circuit is used for converting a high-frequency clock signal of the oscillator into a low-frequency snapshot signal and generating clock and control signals required by the system.
In the present invention, the frequency locking unit generates a frequency error control word for adjusting the oscillator frequency control word, and the frequency locking flag signal is valid when the frequency error control word is less than a set value for a plurality of consecutive cycles. The frequency locking unit includes at least: the counter is used for accumulating 1 in each output clock period, resetting after a frequency counting reset signal is effective and counting the period number of the output clock in each reference period; the subtracter is triggered by the error detection clock and is used for solving the error between the frequency control word and the frequency counting of the output clock; the integrator is triggered by the error detection clock and used for accumulating the frequency error and providing a first-order pole for the frequency control loop; and the gain control is used for multiplying the accumulated frequency error output by the integrator by a set gain coefficient and controlling the loop gain.
In the present invention, the phase locking unit detects a phase difference between two phase signals input thereto, and at least includes: a time amplifier for amplifying a phase error of the two input signals; the phase discriminator is used for judging the phase relation of two input signals; the integrator is triggered by the error detection clock and is used for accumulating the phase difference output by the phase discriminator and providing a first-order pole for the phase control loop; and the gain control is used for multiplying the accumulated phase error output by the integrator by a set gain coefficient and controlling the loop gain.
In the invention, the delay correction unit adjusts the delay relationship between the two phase signals, so that the two phase signals input into the phase locking unit are aligned when no pulse signal is injected, namely the phase error of the two phase signals is 0. This means that when the injection pulse signal is active, the phase error detected by the phase locking unit is introduced by the injection pulse, thereby eliminating other delay errors in the signal path. The delay correction unit includes at least: the integrator is triggered by the delay correction clock and is used for accumulating the phase error output by the phase discriminator and providing a first-order pole for the delay control loop; the numerical control delay chain A and the numerical control delay chain B are used for delaying the input signal for a specified time according to the delay control word; the delay control word A of the numerical control delay chain A is the output of the integrator, and the delay control word B of the numerical control delay chain B is fixed to be 0.
In the invention, the injection locking digital controlled oscillator is a ring oscillator and comprises a plurality of delay units, wherein the output stage delay unit is an injection unit, and the other delay units are common units; the output frequency is controlled by a digital control word; the injection unit consists of two groups of tri-state inverters, and when the injection pulse is effective, one group of tri-state inverters is effective and directly outputs a specified voltage, such as a power supply voltage or a ground; otherwise, the other set of tri-state inverters is active, with the output being the delay of the input.
In the present invention, the clock and snapshot generating circuit at least includes: the clock generating circuit is used for generating an error detection clock, a frequency counting reset signal, a delay correction clock and a control signal of the snapshot circuit, which are required by the system work; and the two snapshot circuits output a change edge after the change edge of the input signal arrives after the control signal is effective, and output a rising edge if the rising edge of the input signal arrives, so that the conversion from the frequency of the input signal to the frequency of the control signal is realized, and the output signal of the two snapshot circuits represents the phase information of the input signal.
According to the injection locking clock frequency multiplier capable of inhibiting the reference stray, the reference clock signal generates the pulse signal, the clean and stable low-frequency pulse signal is injected into the oscillator, the phase locking and the delay correction are performed, the oscillator is locked at the target frequency, and the output clock signal has low phase noise and reference stray.
The injection locking clock frequency multiplier capable of inhibiting the reference stray has the control principle that when the ring oscillator oscillates at a specific frequency, the phase relation among the outputs of all delay units in the ring oscillator is fixed. If the free oscillation frequency of the oscillator is the target frequency, namely the frequency multiplication of the reference clock, when the injected pulse signal is effective, the output clock signal of the oscillator has no phase and frequency and cannot generate mutation; if an error exists between the free oscillation frequency of the oscillator and the target frequency, the phase jump of the output clock signal of the oscillator is caused by injecting the pulse signal. The invention can accurately control the free oscillation frequency of the oscillator by detecting the sudden change and adjusting the frequency of the oscillator, thereby realizing the locking of the phase and the frequency. Since this control method reduces the frequency error of the oscillator, the reference spurs introduced by it are also suppressed.
The method for suppressing the reference stray of the injection locking clock frequency multiplier provided by the invention at least comprises the following parts:
(1) when the system is started, the injection pulse signal is closed by default;
(2) converting a high-frequency signal output by the oscillator into a low frequency by using a snapshot circuit, and then carrying out error detection;
(3) in each reference period, detecting a phase error between two different phase signals of the oscillator after a rising edge and a falling edge of a reference clock;
(4) and (3) time delay correction: after the falling edge of the reference clock, adjusting the time delay of two different phase signal paths of the oscillator according to the detected phase error to enable the phase difference of the two different phase signal paths to be 0;
(5) frequency locking:
(A) coarse locking: controlling the frequency of the output clock signal to be close to the target frequency by the frequency locking loop, enabling the injected pulse signal to be effective, and closing the frequency coarse locking loop;
(B) fine locking: after the injection pulse signal starts to be effective, controlling the frequency of the output clock signal according to the detected phase error after the rising edge of the reference clock, so that the frequency and the phase are accurately locked;
(6) if the frequency control word is changed, the injection pulse signal is closed, and the frequency coarse locking loop is opened again.
The injection locking clock frequency multiplier provided by the invention adopts a control method, wherein two different phase signals of a detected oscillator are respectively the output signal of an injection unit and the output signal of a common unit.
Drawings
Fig. 1 is a top level structural block diagram of an embodiment of the present invention.
Fig. 2 is a block diagram of a frequency locking unit according to an embodiment of the present invention.
Fig. 3 is a timing diagram of a frequency locking unit according to an embodiment of the invention.
Fig. 4 is a block diagram of a phase locking unit according to an embodiment of the present invention.
Fig. 5 is a timing diagram of a phase-locked loop unit according to an embodiment of the invention.
Fig. 6 is a block diagram of a delay correction unit according to an embodiment of the present invention.
Fig. 7 is a timing diagram of the delay correction unit according to the embodiment of the present invention.
Fig. 8 is a block diagram of a clock and snapshot circuit according to an embodiment of the present invention.
Fig. 9 is a timing diagram of a clock and snapshot circuit according to an embodiment of the present invention.
Fig. 10 is a block diagram of an injection locked oscillator according to an embodiment of the present invention.
Fig. 11 is a circuit diagram of an injection unit according to an embodiment of the present invention.
Fig. 12 is an injection timing diagram according to an embodiment of the invention.
Fig. 13 is a circuit diagram of an injection pulse generation circuit according to an embodiment of the present invention.
Fig. 14 is a flowchart of a control method according to an embodiment of the present invention.
Detailed Description
The present invention is described in further detail below by way of a specific example. The present invention will be described more fully hereinafter in the reference to the accompanying drawings, which provide preferred embodiments of the invention, and which are not to be considered as limited to the embodiments set forth herein.
Fig. 1 is a block diagram of a top-level structure of an embodiment of the present invention, which includes a frequency locking unit (100) for comparing an output clock frequency with a frequency control word to obtain a frequency error control word for adjusting an oscillator frequency control word; the phase locking unit (200) is used for comparing output phase signals with different delays, in the output signals, the phase error control word is used for adjusting the frequency control word of the oscillator, and the phase error is used for demonstration correction; the delay correction unit (300) adjusts the delay on different signal paths according to the phase error, namely when the injection pulse signal is closed, the snapshot of the delayed output phase A signal is aligned with the snapshot of the delayed output phase B signal, and the phase errors of the two signals are 0; an injection pulse generation circuit (400) for generating an injection pulse signal from a reference clock and injecting the injection pulse signal into an injection locking digital controlled oscillator to suppress low-frequency noise of the oscillator; an injection locked digitally controlled oscillator (500) for generating an output clock signal, outputting a phase a signal and outputting a phase B signal; and a clock and snapshot generating circuit (600) for converting the high frequency clock signal of the oscillator into a low frequency snapshot signal, outputting a snapshot of the phase a signal and a snapshot of the phase B signal, and generating clock and control signals required by the system.
Fig. 2 is a block diagram of a frequency locking unit according to an embodiment of the present invention, which includes a counter (101), which increments by 1 every output clock cycle, and resets after a frequency count reset signal is asserted, for counting the number of output clock cycles per reference cycle; a subtractor (102) triggered by the error detection clock, for obtaining an error between the frequency control word and the output clock frequency count; an integrator (103) triggered by the error detection clock for accumulating the frequency error and providing a first order pole for the frequency control loop; and the gain control (104) is used for multiplying the accumulated frequency error output by the integrator by a set gain coefficient, controlling the loop gain and obtaining a frequency error control word. Fig. 3 is a timing diagram of a frequency locking unit according to an embodiment of the invention.
Fig. 4 is a block diagram of a phase-locked unit according to an embodiment of the present invention, configured to detect a phase difference between two phase signals input to the phase-locked unit, where the phase-locked unit includes: a time amplifier (201) for amplifying a phase error of the two input signals; a phase detector (202) for determining a phase relationship of two input signals; the integrator (203) is triggered by the error detection clock and is used for accumulating the phase difference output by the phase discriminator and providing a first-order pole for the phase control loop; and the gain control (204) is used for multiplying the accumulated phase error output by the integrator by a set gain coefficient to obtain a phase error control word and control the loop gain. The phase locking unit detects a phase error of the output signal twice in one reference clock cycle, including: detecting the phase relation between two phase signals of an oscillator when the injection pulse signal is effective after the rising edge of the reference clock; the phase relationship between the two phase signals of the oscillator is detected when the injection pulse signal is off after the falling edge of the reference clock. The former is the phase error accumulated from the frequency error and the latter is the other delay error on the signal path. Because the detection of the two is realized by using one phase detector, the error detection is not influenced by the offset of the phase detector. Fig. 5 is a timing diagram of a phase-locked loop unit according to an embodiment of the invention.
Fig. 6 is a block diagram of a delay correction unit according to an embodiment of the present invention, where the delay correction unit includes: the integrator (301) is triggered by the delay correction clock and is used for accumulating the phase error output by the phase discriminator and providing a first-order pole for the delay control loop; the numerical control delay chain A (302) and the numerical control delay chain B (303) are used for delaying the input signal for a specified time according to the delay control word; the delay control word A of the numerical control delay chain A (302) is the output of the integrator, and the delay control word B of the numerical control delay chain B (303) is fixed to be 0. The delay correction unit is used for adjusting the delay relationship between the two phase signals, so that when no pulse signal is injected, the two phase signals input into the phase locking unit are aligned, namely, the phase error of the two phase signals is 0. This means that when the injection pulse signal is active, the phase error detected by the phase locking unit is introduced by the injection pulse, thereby eliminating other delay errors in the signal path. Fig. 7 is a timing diagram of the delay correction unit according to the embodiment.
Fig. 8 is a block diagram of a clock and snapshot circuit according to an embodiment of the present invention, including: the clock generating circuit (602) generates an error detection clock, a frequency counting reset signal, a delay correction clock and a control signal of the snapshot circuit, which are required by the system operation; two snapshot circuits, snapshot circuit a (601) and snapshot circuit B (603). And after the control signal is effective and the change edge of the input signal arrives, outputting a change edge, for example, outputting a rising edge after the rising edge of the input signal arrives, so as to realize the conversion from the frequency of the input signal to the frequency of the control signal, wherein the output signal represents the phase information of the input signal. The circuit also provides an error detection clock, a frequency counting reset signal and a delay correction signal which are required by the system work. Fig. 9 is a timing diagram of a clock and snapshot circuit according to an embodiment of the present invention, where after a rising edge of a reference clock arrives, a frequency counting reset signal is valid, an output is turned off after a certain time delay, an error detection clock outputs a rising edge, a delay correction clock outputs a falling edge, a snapshot circuit a outputs a rising edge, and outputs a falling edge after a certain time delay, so as to obtain a snapshot of an output phase a signal, a snapshot circuit B outputs a rising edge, and outputs a falling edge after a certain time delay, so as to obtain a snapshot of an output phase B signal; after the falling edge of the reference clock comes, the error detection clock outputs a falling edge, the delay correction clock outputs a rising edge, the snapshot circuit A outputs a rising edge, a falling edge is output after certain delay to obtain a snapshot of the output phase A signal, the snapshot circuit B outputs a rising edge, and a falling edge is output after certain delay to obtain a snapshot of the output phase B signal. Thus, the snapshot of the output phase B signal and the snapshot of the output phase B signal reflect the phase relation of the original signals, the frequency technology reset signal is used for resetting a counter of the frequency locking unit, the error detection clock is used for phase locking, and the delay correction clock is used for delay correction.
Fig. 10 is a block diagram of an injection locked oscillator according to an embodiment of the present invention, which is a ring oscillator, and includes 3 delay units, i.e., normal units (501) and (502), and an injection unit (503); the output frequency is controlled by a digital control word. FIG. 11 is a circuit diagram of an injection unit comprising two tri-state inverters, wherein one tri-state inverter is active to directly output a specified voltage, such as a power supply voltage or ground, when an injection pulse is active; otherwise, the other set of tri-state inverters is active, with the output being the delay of the input. FIG. 12 is an injection timing diagram of the present invention, wherein the phase A signal is ahead of the phase B signal when the input pulse signal is low, and the phase relationship between the two signals is fixed at a certain frequency; when the input pulse signal is high, the rising edge of the phase B signal is aligned with the rising edge of the injection pulse signal, and there may be a phase jump: if the free oscillation frequency of the oscillator is lower than the expected frequency, injecting a pulse signal to cause the phase B signal to be relatively advanced; if the free-running frequency of the oscillator is higher than the expected frequency, the injection pulse signal causes the phase B signal to lag relatively.
Fig. 13 is a circuit diagram of an injection pulse generating circuit according to an embodiment of the present invention, which can generate a narrow pulse after the rising edge of the reference clock signal, and the width of the pulse is determined by the magnitude of the insertion delay.
Fig. 14 is a flowchart of a control method according to an embodiment of the present invention:
(1) when the system is started, the injection pulse signal is closed by default;
(2) converting a high-frequency signal output by the oscillator into a low frequency by using a snapshot circuit, and then carrying out error detection;
(3) in each reference period, detecting a phase error between two different phase signals of the oscillator after a rising edge and a falling edge of a reference clock;
(4) and (3) time delay correction: after the falling edge of the reference clock, adjusting the time delay of two different phase signal paths of the oscillator according to the detected phase error to enable the phase difference of the two different phase signal paths to be 0;
(5) frequency locking:
(A) coarse locking: controlling the frequency of the output clock signal to be close to the target frequency by the frequency locking loop, enabling the injected pulse signal to be effective, and closing the frequency coarse locking loop;
(B) fine locking: after the injection pulse signal starts to be effective, controlling the frequency of the output clock signal according to the detected phase error after the rising edge of the reference clock, so that the frequency and the phase are accurately locked;
(6) if the frequency control word is changed, the injection pulse signal is closed, and the frequency coarse locking loop is opened again.
While the embodiments of the present invention have been described with reference to specific examples, those skilled in the art will readily appreciate that the various illustrative embodiments are capable of providing many other embodiments and that many other advantages and features of the invention are possible. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Claims (9)
1. An injection locked clock multiplier to suppress reference spurs, comprising:
the frequency locking unit is used for comparing the output clock frequency of the output clock with the frequency control word and preliminarily controlling the frequency of the output clock signal;
the phase locking unit is used for comparing output phase signals with different delays, accurately locking the frequency and the phase of the output clock signal and suppressing reference stray;
the delay correction unit is used for reducing delay errors on different signal paths when the injection locking digital controlled oscillator outputs to the phase locking unit;
the injection pulse generating circuit is used for generating a pulse signal from a reference clock, injecting the pulse signal into the injection locking digital controlled oscillator and inhibiting the low-frequency noise of the oscillator;
injecting a locked digital controlled oscillator for generating an output high frequency clock signal;
and the clock and snapshot generating circuit is used for converting a high-frequency clock signal of the oscillator into a low-frequency snapshot signal and generating clock and control signals required by the system.
2. The injection-locked clock multiplier of claim 1, wherein the frequency lock unit generates a frequency error control word for adjusting the oscillator frequency control word, and the frequency lock flag signal is asserted when the frequency error control word is less than the set value for a number of consecutive cycles.
3. The injection-locked clock multiplier of claim 1 or 2, wherein the frequency locking unit comprises:
the counter is used for accumulating 1 in each output clock period, resetting after a frequency counting reset signal is effective and counting the period number of the output clock in each reference period;
the subtracter is triggered by the error detection clock and is used for solving the error between the frequency control word and the frequency counting of the output clock;
the integrator is triggered by the error detection clock and used for accumulating the frequency error and providing a first-order pole for the frequency control loop;
and the gain control is used for multiplying the accumulated frequency error output by the integrator by a set gain coefficient and controlling the loop gain.
4. The injection-locked clock multiplier of claim 1, wherein the phase-lock unit comprises:
a time amplifier for amplifying a phase error of the two input signals;
the phase discriminator is used for judging the phase relation of two input signals;
the integrator is triggered by the error detection clock and is used for accumulating the phase difference output by the phase discriminator and providing a first-order pole for the phase control loop;
and the gain control is used for multiplying the accumulated phase error output by the integrator by a set gain coefficient and controlling the loop gain.
5. The injection-locked clock multiplier of claim 1, wherein the delay correction unit comprises:
the integrator is triggered by the delay correction clock and is used for accumulating the phase error output by the phase discriminator and providing a first-order pole for the delay control loop;
the numerical control delay chain A and the numerical control delay chain B are used for delaying the input signal for a specified time according to the delay control word; the delay control word A of the numerical control delay chain A is the output of the integrator, and the delay control word B of the numerical control delay chain B is fixed to be 0.
6. The injection-locked clock multiplier of claim 1, wherein the injection-locked digital controlled oscillator is a ring oscillator comprising a plurality of delay units, wherein the output stage delay units are injection units and the others are normal units;
the output frequency is controlled by a digital control word;
the injection unit consists of two groups of tri-state inverters, and when the injection pulse is effective, one group of tri-state inverters is effective and directly outputs a specified voltage, such as a power supply voltage or a ground; otherwise, the other set of tri-state inverters is active, with the output being the delay of the input.
7. The injection-locked clock multiplier of claim 1, wherein the clock and snapshot generation circuit comprises:
the clock generating circuit is used for generating an error detection clock, a frequency counting reset signal, a delay correction clock and a control signal of the snapshot circuit, which are required by the system work;
and the two snapshot circuits output a change edge after the change edge of the input signal arrives after the control signal is effective, and output a rising edge if the rising edge of the input signal arrives, so that the conversion from the frequency of the input signal to the frequency of the control signal is realized, and the output signal of the two snapshot circuits represents the phase information of the input signal.
8. A method of controlling an injection locked clock multiplier as claimed in any one of claims 1 to 7, characterized in that it comprises at least the following parts:
when the system is started, the injection pulse signal is closed by default;
converting a high-frequency signal output by the oscillator into a low frequency by using a snapshot circuit, and then carrying out error detection;
detecting a phase error between two different phase signals of the oscillator after a rising edge and a falling edge of a reference clock in each reference period;
and (3) time delay correction: after the falling edge of the reference clock, adjusting the time delay of two different phase signal paths of the oscillator according to the detected phase error to enable the phase difference of the two different phase signal paths to be 0;
frequency locking:
(1) coarse locking: controlling the frequency of the output clock signal to be close to the target frequency by the frequency locking loop, enabling the injected pulse signal to be effective, and closing the frequency coarse locking loop;
(2) fine locking: after the injection pulse signal starts to be effective, controlling the frequency of the output clock signal according to the detected phase error after the rising edge of the reference clock, so that the frequency and the phase are accurately locked;
if the frequency control word is changed, the injection pulse signal is closed, and the frequency coarse locking loop is opened again.
9. Control method according to claim 8, characterized in that the oscillator signals to be detected are two different phase signals, one being the output signal of the injection unit and the other being the output signal of the ordinary unit.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN115334264A (en) * | 2022-08-17 | 2022-11-11 | 中国电子科技集团公司第四十四研究所 | CMOS image sensor on-chip clock generation circuit, module and method |
| WO2023060847A1 (en) * | 2021-10-14 | 2023-04-20 | 浙江大学 | Circuit and method for widening locking range of injection-locked oscillator |
| US11967966B2 (en) | 2021-10-14 | 2024-04-23 | Zhejiang University | Circuit and method for expanding lock range of injection-locked oscillators |
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| WO2023060847A1 (en) * | 2021-10-14 | 2023-04-20 | 浙江大学 | Circuit and method for widening locking range of injection-locked oscillator |
| US11967966B2 (en) | 2021-10-14 | 2024-04-23 | Zhejiang University | Circuit and method for expanding lock range of injection-locked oscillators |
| CN115021726A (en) * | 2022-05-10 | 2022-09-06 | 上海韬润半导体有限公司 | Clock buffer circuit and analog-to-digital converter |
| CN115334264A (en) * | 2022-08-17 | 2022-11-11 | 中国电子科技集团公司第四十四研究所 | CMOS image sensor on-chip clock generation circuit, module and method |
| CN115334264B (en) * | 2022-08-17 | 2024-04-09 | 中国电子科技集团公司第四十四研究所 | CMOS image sensor on-chip clock generation circuit, module and method |
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