CN110634900A - Wafer-level packaging method and packaging structure of image sensor with FSI structure - Google Patents
Wafer-level packaging method and packaging structure of image sensor with FSI structure Download PDFInfo
- Publication number
- CN110634900A CN110634900A CN201910925286.7A CN201910925286A CN110634900A CN 110634900 A CN110634900 A CN 110634900A CN 201910925286 A CN201910925286 A CN 201910925286A CN 110634900 A CN110634900 A CN 110634900A
- Authority
- CN
- China
- Prior art keywords
- wafer
- layer
- bonding pad
- image sensor
- packaging method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 46
- 229910000679 solder Inorganic materials 0.000 claims abstract description 33
- 238000002161 passivation Methods 0.000 claims abstract description 28
- 238000007747 plating Methods 0.000 claims abstract description 21
- 239000011521 glass Substances 0.000 claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000000126 substance Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 102
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 37
- 239000010931 gold Substances 0.000 claims description 29
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 238000011161 development Methods 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 6
- 238000005728 strengthening Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 239000011241 protective layer Substances 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 96
- 238000010586 diagram Methods 0.000 description 8
- 230000003287 optical effect Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14632—Wafer-level processed structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The invention provides a wafer-level packaging method and a wafer-level packaging structure of an image sensor with an FSI structure, which can effectively increase the strength and reliability of a bonding pad and reduce the occurrence of the condition that the bonding pad is broken, and the packaging method comprises the following steps: providing a wafer, and plating a Ni/Au layer on a bonding pad of the wafer through a chemical Ni/Au plating process; bonding the wafer and the glass carrying plate together; etching the wafer to form a slot hole, so that the bonding pad on the wafer is exposed; forming a passivation layer on the wafer, and then, opening a window on the passivation layer to expose the bonding pad on the wafer; manufacturing a rewiring layer on the passivation layer, and connecting the bonding pad on the wafer through the rewiring layer; and forming a solder mask layer on the rewiring layer, windowing the solder mask layer and manufacturing solder balls, wherein the solder balls are connected with the rewiring layer.
Description
Technical Field
The invention relates to the technical field of semiconductor chip packaging, in particular to a wafer level packaging method and a wafer level packaging structure of an image sensor with an FSI structure.
Background
The image sensor is a Semiconductor Device that converts an optical signal into an electrical signal, and mainly includes a Charge Coupled Device (CCD) image sensor and a Complementary Metal Oxide Semiconductor (CMOS) image sensor. In recent years, CMOS image sensors have become the mainstream of replacing CCD image sensors with advantages such as low cost, high efficiency, and high transfer speed.
A CMOS image sensor is an image sensor manufactured based on a CMOS process for converting an analog optical signal into a digital electrical signal. And an external light source converges an image on the pixel array of the photosensitive area of the CMOS image sensor through an optical device. The pixel array converts the received optical signal into an analog electrical signal, and the analog electrical signal is amplified, denoised and sent to an analog-to-digital converter for digitalization. And finally, the digitized signal is operated by an image processing chip to obtain a clear and real image.
Conventionally, an image sensor is designed in accordance with a manufacturing flow. Thus, for the final device, light enters between the front metal control lines and is then focused on the photodetector. Conventionally, for larger pixels, fsi (front side illumination) is quite effective because the ratio of the pixel stack height to the pixel area is large, resulting in a large aperture of the pixel. Increasingly smaller pixels require a range of pixel technology innovations to address the material and manufacturing limitations of the previous illumination technologies. For example, FSI has taken many innovative techniques and process improvements, such as shape optimized microlenses, color optimized filtering, recessed pixel arrays, light pipes, and anti-reflective coatings, to optimize the optical path of the FSI pixels.
Fig. 1 illustrates a conventional chip package structure, which takes TSV wafer level Fan-in (Fan-in) as an example, to connect a circuit on a Pad (Pad) of a chip to a back side via TSV packaging technology, and then cut into single packages.
However, in the packaging structure, various materials connected with the bonding pad generate large forward stress, so that certain requirements are met on the strength of the bonding pad, most wafers are thick due to the fact that only 0.8um of Al is left on the bonding pad, and CP testing is conducted when the wafers leave a factory, namely, the bonding pad of only 0.8um is damaged, and when the bonding pad is subjected to reliable cold and hot circulation, the bonding pad is broken due to stress, so that the product fails.
Disclosure of Invention
In order to solve the problem of reliability failure caused by the fact that a bonding pad is thin in the process of packaging a wafer by using a TSV (through silicon via), the invention provides a wafer-level packaging method and a packaging structure of an image sensor with an FSI (frequency selective interface) structure, which can effectively increase the strength of the bonding pad, increase the reliability and reduce the occurrence of the condition that the bonding pad is broken.
The technical scheme is as follows: the wafer level packaging method of the image sensor with the FSI structure is characterized by comprising the following steps of:
step 1: providing a wafer, and plating a Ni/Au layer on a bonding pad of the wafer through a chemical Ni/Au plating process;
step 2: bonding the wafer and the glass carrying plate together;
and step 3: etching the wafer to form a slot hole, so that the bonding pad on the wafer is exposed;
and 4, step 4: forming a passivation layer on the wafer, and then, opening a window on the passivation layer to expose the bonding pad on the wafer;
and 5: manufacturing a rewiring layer on the passivation layer, and connecting the bonding pad on the wafer through the rewiring layer;
step 6: and forming a solder mask layer on the rewiring layer, windowing the solder mask layer and manufacturing solder balls, wherein the solder balls are connected with the rewiring layer.
Further, in step 1, the strength of the pad is adjusted by adjusting the thickness of the Ni plating.
Further, in step 1, the entire surface of the wafer is plated with Ni/Au by an electroless Ni/Au plating process, and then the surface of the wafer is cleaned to remove the Ni/Au layer on the surface of the wafer except for the pad.
Further, in step 2, after the wafer and the glass carrier plate are bonded together, the wafer is thinned to a target thickness.
Further, in step 3, a groove pattern is formed by photolithography through a yellow light process, an inclined groove is etched on the wafer through an etching process, a hole pattern is formed by photolithography through the yellow light process, and an inclined hole is etched on the wafer through the etching process, so that the bonding pad on the wafer is exposed.
Further, in step 4, a passivation layer is formed on the wafer by coating or vacuum lamination, and then the pad on the wafer is exposed by exposure and development.
Furthermore, in step 5, when the redistribution layer is fabricated, a seed layer is deposited, the seed layer adopts a Ti/Cu composite material or aluminum, then copper or aluminum is deposited to a target thickness, then the circuit is photoetched, etched and stripped, and then a protective layer is formed on the redistribution layer by adopting a chemical nickel plating or gold plating mode.
Further, in step 6, a solder mask layer is formed on the redistribution layer by coating, the redistribution lines required to be electrically led out are exposed by exposure and development, and solder balls are formed by printing solder paste or ball-planting.
Further, after the step 6, the following steps are also included: and cutting the wafer to form a single chip packaging structure.
A wafer level packaging structure of an image sensor with an FSI structure is characterized by comprising:
a glass carrier plate;
the wafer is provided with a bonding pad and a photosensitive area which are arranged on the first surface of the wafer, a slotted hole is formed in the second surface of the wafer so that the bonding pad is exposed, and a strengthening layer is arranged on the bonding pad and made of Ni/Au;
the cofferdam is arranged between the first surface of the wafer and the first surface of the glass carrier plate and forms a closed cavity with the first surface of the wafer and the first surface of the glass carrier plate;
the passivation layer is arranged on the second surface of the wafer, and a windowing area is arranged at the position corresponding to the bonding pad of the wafer;
the rewiring layer is arranged on the passivation layer and connected with the bonding pad of the wafer;
a solder resist layer disposed on the rewiring layer;
and the solder balls are connected with the heavy wiring layer.
The invention relates to a wafer level packaging method of an image sensor with an FSI structure, which comprises the steps of firstly plating a NiAu layer on the whole surface of a wafer, forming a Ni/Au layer on a bonding pad for reinforcing the bonding pad, then cleaning the surface of the wafer, removing the Ni/Au layer on the surface of the wafer except the bonding pad, adjusting the strength of the bonding pad by adjusting the thickness of the plated Ni, arranging the Ni/Au layer to effectively increase the strength of the bonding pad, increase the reliability and reduce the occurrence of the condition that the bonding pad is pulled apart, then bonding the wafer and a glass carrying plate together, etching the wafer to form a slotted hole, exposing the bonding pad on the wafer, forming a passivation layer on the wafer, then opening a window on the passivation layer to expose the bonding pad on the wafer, manufacturing a rewiring layer on the passivation layer, connecting the bonding pad on the wafer through the rewiring layer, forming a solder mask on the rewiring layer, opening the window on, the wafer level packaging method of the image sensor with the FSI structure has the advantages of high reliability, small packaging size, good overall performance, simple preparation process and high production efficiency.
Drawings
Fig. 1 is a schematic diagram of a conventional chip package structure;
FIG. 2 is a flow chart of a wafer level packaging method of the FSI image sensor of the present invention;
FIG. 3 is a schematic diagram of step 1 of the packaging method in an embodiment of the invention;
FIG. 4 is a schematic diagram of step 2 of the packaging method in an embodiment of the invention;
FIG. 5 is a schematic diagram of step 3 of the packaging method in an embodiment of the invention;
FIG. 6 is a schematic diagram of step 4 of the packaging method in an embodiment of the invention;
FIG. 7 is a schematic diagram of step 5 of the packaging method in an embodiment of the invention;
FIG. 8 is a schematic diagram of step 6 of the encapsulation method in an embodiment of the present invention;
fig. 9 is a schematic diagram of a wafer level package structure of an image sensor with an FSI structure according to the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, wherein the drawings provided in the present embodiments illustrate the basic idea of the invention only in a schematic way, and the elements related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the elements in actual implementation, and the type, number and proportion of the elements in actual implementation can be changed freely, and the layout of the elements may be more complex.
Referring to fig. 2, the wafer level packaging method of the image sensor with the FSI structure of the present invention includes the following steps:
step 1: providing a wafer, and plating a Ni/Au layer on a bonding pad of the wafer through a chemical Ni/Au plating process;
step 2: bonding the wafer and the glass carrying plate together;
and step 3: etching the wafer to form a slot hole, so that the bonding pad on the wafer is exposed;
and 4, step 4: forming a passivation layer on the wafer, and then, opening a window on the passivation layer to expose the bonding pad on the wafer;
and 5: manufacturing a rewiring layer on the passivation layer, and connecting the bonding pad on the wafer through the rewiring layer;
step 6: and forming a solder mask layer on the rewiring layer, windowing the solder mask layer and manufacturing solder balls, wherein the solder balls are connected with the rewiring layer.
Specifically, the present embodiment provides a wafer level packaging method for an image sensor with an FSI structure, where the packaging method includes the following steps:
step 1: referring to fig. 3, a wafer 100 is provided, the entire surface of the wafer 100 is plated with Ni/Au by an electroless Ni/Au plating process, then the surface of the wafer is cleaned, the Ni/Au layer on the surface of the wafer except for a pad 101 is removed, and a Ni/Au layer 200 is plated on the pad 101 of the wafer, wherein the strength of the pad 101 can be adjusted by adjusting the thickness of the plated Ni;
step 2: referring to fig. 4, the wafer 100 and the glass carrier 300 are bonded together, and the wafer 100 is thinned to a target thickness, where the thinning is performed to reduce the size after packaging, reduce the refraction and reflection of light, increase the light transmittance;
and step 3: referring to fig. 5, a wafer 100 is etched to form a slot 102, a slot pattern is first formed by photolithography with a yellow light process, an inclined slot is then etched on the wafer through an etching process, a hole pattern is then formed by photolithography with a yellow light process, and an inclined hole is then etched on the wafer through an etching process, so that a pad 101 on the wafer is exposed;
and 4, step 4: referring to fig. 6, a passivation layer 400 is formed on a wafer 100 by coating or vacuum lamination, and then a pad 101 on the wafer is exposed by exposure and development;
and 5: referring to fig. 7, a redistribution layer 500 is formed on a passivation layer 400, the redistribution layer 500 is connected to a pad on a wafer 100, when the redistribution layer is formed, a seed layer is deposited first, the seed layer is made of a Ti/Cu composite material or aluminum, copper or aluminum is deposited to a target thickness, then a circuit is photoetched, etched and stripped, and a protective layer is formed on the redistribution layer in a chemical nickel plating or gold plating manner;
step 6: referring to fig. 8, a solder mask layer 600 is formed on the redistribution layer 500 by coating, then the redistribution lines required to be electrically led out are exposed by exposure and development, and then solder balls 700 are formed by printing solder paste or ball-planting.
After the step 6, the following steps are also included: through wafer dicing, a single chip package structure is formed, see fig. 9.
The invention relates to a wafer level packaging method of an image sensor with an FSI structure, which comprises the steps of firstly plating a NiAu layer on the whole surface of a wafer, forming a Ni/Au layer on a bonding pad for reinforcing the bonding pad, then cleaning the surface of the wafer, removing the Ni/Au layer on the surface of the wafer except the bonding pad, adjusting the strength of the bonding pad by adjusting the thickness of the plated Ni, arranging the Ni/Au layer to effectively increase the strength of the bonding pad, increase the reliability and reduce the occurrence of the condition that the bonding pad is pulled apart, then bonding the wafer and a glass carrying plate together, etching the wafer to form a slotted hole, exposing the bonding pad on the wafer, forming a passivation layer on the wafer, then opening a window on the passivation layer to expose the bonding pad on the wafer, manufacturing a rewiring layer on the passivation layer, connecting the bonding pad on the wafer through the rewiring layer, forming a solder mask on the rewiring layer, opening the window on, the wafer level packaging method of the image sensor with the FSI structure has the advantages of high reliability, small packaging size, good overall performance, simple preparation process and high production efficiency.
Referring to fig. 9, in an embodiment of the present invention, there is also provided a wafer level package structure of an image sensor of an FSI structure, including:
a glass carrier plate 300;
a wafer 100, wherein a pad 101 and a photosensitive area 103 are arranged on a first surface of the wafer 100, a slot 102 is arranged on a second surface of the wafer 100 to expose the pad 101, and a strengthening layer is arranged on the pad 101 and is a Ni/Au layer 200;
the cofferdam 800 is arranged between the first surface of the wafer 100 and the first surface of the glass carrier 300, and forms a closed cavity 900 with the first surface of the wafer 100 and the first surface of the glass carrier 300;
the passivation layer 400 is arranged on the second surface of the wafer 100, and an open window area is arranged at the position corresponding to the pad 101 of the wafer;
a redistribution layer 500 disposed on the passivation layer 400, the redistribution layer 500 being connected to the pad 101 of the wafer;
a solder resist layer 600 disposed on the rewiring layer 500;
It is noted that the first surface described in this application is a surface facing the enclosed cavity 900, and the second surface is a surface disposed opposite to the first surface.
In the above embodiment, the package structure of the cut chip includes a single CMOS image sensor; of course, in other embodiments, multiple CMOS image sensors may be included, and may be arranged appropriately as needed.
According to the wafer-level packaging structure of the image sensor with the FSI structure, the strength of the bonding pad is increased by manufacturing the strengthening layer from Ni/Au, the reliability is improved, and the situation that the bonding pad is broken by pulling is reduced.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
- A wafer level packaging method of an image sensor of FSI structure, characterized in that the packaging method comprises the steps of:step 1: providing a wafer, and plating a Ni/Au layer on a bonding pad of the wafer through a chemical Ni/Au plating process;step 2: bonding the wafer and the glass carrying plate together;and step 3: etching the wafer to form a slot hole, so that the bonding pad on the wafer is exposed;and 4, step 4: forming a passivation layer on the wafer, and then, opening a window on the passivation layer to expose the bonding pad on the wafer;and 5: manufacturing a rewiring layer on the passivation layer, and connecting the bonding pad on the wafer through the rewiring layer;step 6: and forming a solder mask layer on the rewiring layer, windowing the solder mask layer and manufacturing solder balls, wherein the solder balls are connected with the rewiring layer.
- 2. The wafer level packaging method for the image sensor of the FSI structure as claimed in claim 1, wherein: in step 1, the strength of the pad is adjusted by adjusting the thickness of the Ni plating.
- 3. The wafer level packaging method for the image sensor of the FSI structure as claimed in claim 1, wherein: in step 1, Ni/Au is plated on the whole surface of the wafer through a chemical Ni/Au plating process, and then the surface of the wafer is cleaned to remove the Ni/Au layer on the surface of the wafer except the bonding pad.
- 4. The wafer level packaging method for the image sensor of the FSI structure as claimed in claim 1, wherein: in step 2, after the wafer and the glass carrier plate are bonded together, the wafer is thinned to a target thickness.
- 5. The wafer level packaging method for the image sensor of the FSI structure as claimed in claim 1, wherein: in step 3, a groove pattern is formed by photolithography through a yellow light process, an inclined groove is etched on the wafer through an etching process, a hole pattern is formed by photolithography through the yellow light process, and an inclined hole is etched on the wafer through the etching process, so that the bonding pad on the wafer is exposed.
- 6. The wafer level packaging method for the image sensor of the FSI structure as claimed in claim 1, wherein: in step 4, a passivation layer is formed on the wafer by coating or vacuum lamination, and then the pads on the wafer are exposed by exposure and development.
- 7. The wafer level packaging method for the image sensor of the FSI structure as claimed in claim 1, wherein: in step 5, when the redistribution layer is manufactured, a seed layer is deposited, the seed layer adopts Ti/Cu composite material or aluminum, then copper or aluminum is deposited to the target thickness, then the circuit is photoetched, etched and stripped, and then a protective layer is formed on the redistribution layer in a chemical nickel plating or gold plating mode.
- 8. The wafer level packaging method for the image sensor of the FSI structure as claimed in claim 1, wherein: in step 6, a solder mask layer is formed on the redistribution layer by coating, then the redistribution lines needing to be electrically led out are exposed by exposure and development, and then solder balls are formed by printing solder paste or ball planting.
- 9. The wafer level packaging method for the image sensor of the FSI structure as claimed in claim 1, wherein: after the step 6, the following steps are also included: and cutting the wafer to form a single chip packaging structure.
- 10. A wafer level packaging structure of an image sensor with an FSI structure is characterized by comprising:a glass carrier plate;the wafer is provided with a bonding pad and a photosensitive area which are arranged on the first surface of the wafer, a slotted hole is formed in the second surface of the wafer so that the bonding pad is exposed, and a strengthening layer is arranged on the bonding pad and made of Ni/Au;the cofferdam is arranged between the first surface of the wafer and the first surface of the glass carrier plate and forms a closed cavity with the first surface of the wafer and the first surface of the glass carrier plate;the passivation layer is arranged on the second surface of the wafer, and a windowing area is arranged at the position corresponding to the bonding pad of the wafer;the rewiring layer is arranged on the passivation layer and connected with the bonding pad of the wafer;a solder resist layer disposed on the rewiring layer;and the solder balls are connected with the heavy wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910925286.7A CN110634900A (en) | 2019-09-27 | 2019-09-27 | Wafer-level packaging method and packaging structure of image sensor with FSI structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910925286.7A CN110634900A (en) | 2019-09-27 | 2019-09-27 | Wafer-level packaging method and packaging structure of image sensor with FSI structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110634900A true CN110634900A (en) | 2019-12-31 |
Family
ID=68973313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910925286.7A Pending CN110634900A (en) | 2019-09-27 | 2019-09-27 | Wafer-level packaging method and packaging structure of image sensor with FSI structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110634900A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101075595A (en) * | 2006-05-15 | 2007-11-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor wafer welding material projected block structure and its production |
| CN102800651A (en) * | 2011-05-24 | 2012-11-28 | 索尼公司 | Semiconductor device and method of manufacturing semiconductor device |
| CN103474365A (en) * | 2013-09-04 | 2013-12-25 | 惠州硕贝德无线科技股份有限公司 | Method for packaging semiconductor |
| CN104409464A (en) * | 2014-11-23 | 2015-03-11 | 北京工业大学 | High-reliability image sensor packaging structure with stress protection structure |
| CN104576564A (en) * | 2015-01-26 | 2015-04-29 | 华天科技（昆山）电子有限公司 | Wafer level chip size packaging structure and manufacturing process thereof |
-
2019
- 2019-09-27 CN CN201910925286.7A patent/CN110634900A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101075595A (en) * | 2006-05-15 | 2007-11-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor wafer welding material projected block structure and its production |
| CN102800651A (en) * | 2011-05-24 | 2012-11-28 | 索尼公司 | Semiconductor device and method of manufacturing semiconductor device |
| CN103474365A (en) * | 2013-09-04 | 2013-12-25 | 惠州硕贝德无线科技股份有限公司 | Method for packaging semiconductor |
| CN104409464A (en) * | 2014-11-23 | 2015-03-11 | 北京工业大学 | High-reliability image sensor packaging structure with stress protection structure |
| CN104576564A (en) * | 2015-01-26 | 2015-04-29 | 华天科技（昆山）电子有限公司 | Wafer level chip size packaging structure and manufacturing process thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10991752B2 (en) | Vertically integrated image sensor chips and methods for forming the same | |
| US9859322B2 (en) | Methods and apparatus for glass removal in CMOS image sensors | |
| KR102460077B1 (en) | Stacked Image Sensor Package And Stacked Image Sensor Module | |
| TWI532155B (en) | Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device | |
| US8680635B2 (en) | CMOS image sensor big via bonding pad application for AICu process | |
| US7663213B2 (en) | Wafer level chip size packaged chip device with a double-layer lead structure and method of fabricating the same | |
| US20150061102A1 (en) | Electronic device package and fabrication method thereof | |
| US20190096866A1 (en) | Semiconductor package and manufacturing method thereof | |
| TW200834863A (en) | Wafer level image sensor package with die receiving cavity and method of the same | |
| TW201351629A (en) | Semiconductor device and manufacturing of the same | |
| JP2006216935A (en) | Image sensor module of wafer level and manufacturing method thereof | |
| CN111354652B (en) | High-reliability image sensor wafer-level fan-out packaging structure and method | |
| WO2011028245A1 (en) | Wafer level compliant packages for rear-face illuminated solid state image sensors | |
| KR20080084759A (en) | Image sensor module having build-in package cavity and the method of the same | |
| US11973095B2 (en) | Method for forming chip package with second opening surrounding first opening having conductive structure therein | |
| CN110649055A (en) | Wafer-level packaging method and packaging structure for improving glare problem of CIS chip | |
| TWI585959B (en) | Chip package and method thereof | |
| CN110797358B (en) | Chip package and method for manufacturing the same | |
| CN105023931A (en) | Backside illuminated image chip module structure and fabrication method thereof | |
| CN110634900A (en) | Wafer-level packaging method and packaging structure of image sensor with FSI structure | |
| CN111697017B (en) | Image sensor and preparation method thereof | |
| KR100634419B1 (en) | Image sensor and method of manufacturing thereof | |
| KR101116834B1 (en) | Wafer level package and method of manufacturing the same | |
| US20240021649A1 (en) | Through-substrate-via in photosensitive module | |
| KR20150071666A (en) | Image sensor devices, methods of manufacture thereof, and semiconductor device manufacturing methods |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20191231 |