CN110634810A

CN110634810A - Semiconductor device package and method of manufacturing the same

Info

Publication number: CN110634810A
Application number: CN201910337949.3A
Authority: CN
Inventors: 叶昶麟; 陈昱敞
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2018-06-22
Filing date: 2019-04-25
Publication date: 2019-12-31

Abstract

At least some embodiments of the present disclosure relate to a semiconductor device package and a method of manufacturing the semiconductor device package. The semiconductor device package includes a substrate, a first solder paste, electrical contacts, and a first encapsulation. The substrate includes a conductive pad. The first solder paste is disposed on the pad. The electrical contacts are disposed on the first solder paste. The first encapsulation encapsulates a portion of the electrical contacts and exposes surfaces of the electrical contacts. The electrical contacts have surfaces facing away from the substrate. The melting point of the electrical contact is greater than the melting point of the first solder paste. The first encapsulation includes a first surface facing the substrate and a second surface opposite the first surface. The second surface of the first encapsulation is exposed to air.

Description

Semiconductor device package and method of manufacturing the same

Cross reference to related applications

This application claims the benefit and priority of U.S. provisional application No. 62/688,937, filed on.2018, 6, month 22, the contents of which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates to a semiconductor device package. In particular, the present disclosure relates to semiconductor device packages that include electrical contacts having high melting point portions and encapsulants in contact with the high melting point portions of the electrical contacts.

Background

Semiconductor packaged devices may include multiple electronic components to increase their performance and functionality. To reduce the area or footprint of the semiconductor package device, electronic components may be mounted to both the upper and lower surfaces of the substrate. To protect electronic components mounted on the substrate, a package body may be formed on each of the upper and lower surfaces of the substrate using a double-sided molding technique. However, forming the package body on both sides of the substrate will increase the thickness of the semiconductor device package. Creating a double-sided molding module with a relatively thin thickness is challenging.

Disclosure of Invention

In some embodiments, according to one aspect, a semiconductor device package includes a substrate, a first solder paste, electrical contacts, and a first encapsulation. The substrate includes a conductive pad. The first solder paste is disposed on the pad. The electrical contacts are disposed on the first solder paste. The first encapsulation encapsulates a portion of the electrical contacts and exposes surfaces of the electrical contacts. The electrical contacts have surfaces facing away from the substrate. The melting point of the electrical contact is greater than the melting point of the first solder paste. The first encapsulation includes a first surface facing the substrate and a second surface opposite the first surface. The second surface of the first encapsulation is exposed to air.

In some embodiments, according to one aspect, a semiconductor device package includes a substrate, a first solder paste, electrical contacts, and an encapsulation. The substrate includes a conductive pad. The first solder paste is disposed on the conductive pad. Electrical contacts are disposed on the first solder paste. The encapsulation encapsulates the electrical contacts. The electrical contact includes a high melting point portion. The melting point of the high melting point portion of the electrical contact is greater than the melting point of the first solder paste. The encapsulation is in contact with the high melting point portion of the electrical contact.

In some embodiments, according to another aspect, a method for manufacturing a semiconductor device package is disclosed. The method comprises the following steps: disposing a first solder paste on a substrate; disposing an electrical contact on the first solder paste, wherein the electrical contact comprises a high melting point portion having a melting point greater than a melting point of the first solder paste; forming an encapsulation to encapsulate the electrical contacts, the encapsulation in contact with the high melting point portions of the electrical contacts; and disposing a second solder paste on the electrical contacts.

Drawings

Fig. 1A illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 1B illustrates a cross-sectional view of an enlarged view of a portion of a semiconductor packaging device, according to some embodiments of the present disclosure.

Fig. 2A illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 2B illustrates a cross-sectional view of an enlarged view of a portion of a semiconductor packaging device, according to some embodiments of the present disclosure.

Fig. 2C illustrates a cross-sectional view of an enlarged view of a portion of a semiconductor packaging device, according to some embodiments of the present disclosure.

Fig. 2D illustrates a cross-sectional view of an enlarged view of a portion of a semiconductor packaging device, according to some embodiments of the present disclosure.

Fig. 2E illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 2F illustrates a cross-sectional view of an enlarged view of a portion of a semiconductor packaging device, according to some embodiments of the present disclosure.

Fig. 3A illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 3B illustrates a cross-sectional view of an enlarged view of a portion of a semiconductor packaging device, according to some embodiments of the present disclosure.

Fig. 3C illustrates a cross-sectional view of an enlarged view of a portion of a semiconductor packaging device, according to some embodiments of the present disclosure.

Fig. 4A illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 4B illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 4C illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 5A-5C illustrate methods of fabricating semiconductor device packages according to some embodiments of the present disclosure.

Fig. 6A-6C illustrate methods of fabricating semiconductor device packages according to some embodiments of the present disclosure.

Fig. 7A-7D illustrate methods of manufacturing semiconductor device packages, according to some embodiments of the present disclosure.

Fig. 8A-8B illustrate methods of fabricating semiconductor device packages according to some embodiments of the present disclosure.

Detailed Description

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings.

Spatial descriptions, such as "above," "below," "up," "left," "right," "down," "top," "bottom," "vertical," "horizontal," "side," "upper," "lower," "upper," "above," "below," and the like, are specified with respect to a component or group of components or a plane of a component or group of components for orienting one or more components as shown in the associated figures. It is to be understood that the spatial description used herein is for illustrative purposes only and that actual implementations of the structures described herein may be spatially arranged in any orientation or manner, provided that the advantages of the embodiments of the present disclosure are not so arranged.

Fig. 1A is a cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure. The semiconductor device package 1 includes a substrate 10,

electronic components

11a, 11b, and 13,

encapsulation bodies

12 and 14, solder paste 15s, electrical contacts 15, and solder paste 16. In some embodiments, the semiconductor device package 1 is a double-sided module. The semiconductor device package 1 may include a conformal shield (not shown) disposed over the outer surfaces of the

encapsulation bodies

12, 14 and the substrate 10 to provide electromagnetic interference (EMI) shielding.

The substrate 10 may be, for example, a Printed Circuit Board (PCB), such as a paper copper foil laminate, a composite copper foil laminate, a polymer impregnated fiberglass-based copper foil laminate, or a combination of two or more thereof. Substrate 10 may include an interconnect structure such as a redistribution layer (RDL). The substrate 10 has an upper surface 101 and a lower surface 102 opposite the upper surface 101. The substrate 10 has a conductive pad 10p on the lower surface 102 or adjacent to the lower surface 102. The solder paste 15s is placed on the conductive pad 10 p.

Electronic components

11a and 11b are disposed on an upper surface 101 of substrate 10. The electronic component 11a may be an active component, such as an Integrated Circuit (IC) chip or die. The electronic component 11b may be a passive component, such as a capacitor, a resistor, or an inductor. The

electronic components

11a and 11b may be electrically connected to another electronic component and/or one or more of the substrates 10 (e.g., to an interconnect layer), and the electrical connection may be obtained by means of flip chip or wire bonding techniques.

The encapsulation 12 is disposed on the upper surface 101 of the substrate 10. The encapsulation body 12 covers or encapsulates the substrate 10 and the

electronic components

11a and 11 b. In some embodiments, the encapsulation 12 includes an epoxy with filler, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material having silicone dispersed therein, or a combination thereof.

The electronic components 13 are disposed on the lower surface 102 of the substrate 10. The electronic component 13 has a surface 131. In some embodiments, surface 131 is a backside surface of electronic component 13. The electronic component 13 is adjacent to the electrical contacts 15. The electronic components 13 may be active components (e.g., IC chips or dies) or passive components (e.g., capacitors, resistors, or inductors). The electronic components 13 may be electrically connected to the substrate 10 (e.g. to an interconnect layer), and the electrical connection may be obtained by means of flip-chip or wire bonding techniques. Electronic component 13 may be electrically connected to

electronic components

11a and 11b through interconnect layers within substrate 10.

The electrical contacts 15 are placed on the solder paste 15 s. The solder paste 15s may bond the electrical contacts 15 to the conductive pads 10 p. Electrical contacts 15 are disposed on the lower surface 102 of the substrate 10. The electrical contacts 15 may be electrically connected to the upper surface 101 of the substrate 10 through an interconnect structure. In some embodiments, the electrical contacts 15 are controlled collapse chip connection (C4) bumps, solder bumps, one or more Land Grid Arrays (LGAs), or a combination of two or more thereof.

A portion of the electrical contacts 15 are exposed from the encapsulation 14. For example, surfaces 151 (e.g., cutting surfaces) of the electrical contacts 15 are exposed from the encapsulation 14. In some embodiments, the surfaces 151 of the electrical contacts 15 are substantially coplanar with the lower surface 142 of the encapsulation 14. In some embodiments, the electrical contacts 15 are formed from or include copper (Cu), an alloy (e.g., CuAg or CuAu), or a high melting point solder material (e.g., high melting point Sn). The melting point of the electrical contacts 15 is greater than the melting points of the solder pastes 15s and 16. In some embodiments, the electrical contacts 15 are in the shape of a portion of a ball. In the case where the electrical contact 15 is part of a metal ball, the distance between the lower surface 102 of the substrate 10 and the surface 151 of the electrical contact 15 is less than the diameter of the entire metal ball. In some embodiments, the electrical contacts 15 may be part of metal balls, alloy balls, plastic balls, or metal posts.

The encapsulation 14 includes an upper surface 141 facing the substrate 10 and a lower surface 142 opposite the upper surface 141. The encapsulation 14 covers or encapsulates the lower surface 102 of the substrate 10 and the electronic components 13. The lower surface 142 of the encapsulation 14 at least partially exposes the surfaces 151 of the electrical contacts 15. The lower surface 142 of the capsule 14 is exposed to air. The lower surface 142 of the encapsulation 14 is substantially coplanar with the surfaces 151 of the electrical contacts 15. The lower surface 142 of the encapsulation 14 is substantially coplanar with the surface 131 of the electronic component 13. In some embodiments, surfaces 131 of electronic component 13 and surfaces 151 of electrical contacts 15 are exposed from encapsulation 14. In some embodiments, the encapsulation 14 may comprise the same material as the encapsulation 12. The encapsulation 14 may comprise a different material than the encapsulation 12.

Solder paste 16 is disposed on the surfaces 151 of the electrical contacts 15 to prevent oxidation of the electrical contacts 15 and to provide an electrical connection between the semiconductor device package 1 and any other device or component. The solder paste 16 may serve as a conductive pad. In some embodiments, solder paste 16 may comprise the same material as solder paste 15 s. The solder paste 16 may contain a different material from the solder paste 15 s. In some embodiments, the solder paste 16 may be omitted.

Fig. 1B is a cross-sectional view of an enlarged view of a portion of a semiconductor package device 1, according to some embodiments of the present disclosure. The substrate 10 includes a dielectric/insulating layer 10 i. The dielectric layer 10i may be a solder resist layer. The dielectric layer 10i partially covers the conductive pad 10 p. The dielectric layer 10i is spaced apart from the solder paste 15s by the encapsulation 14. The encapsulation 14 is in contact with the dielectric layer 10i, the conductive pad 10p, the solder paste 15s and the electrical contact 15. The encapsulation 14 may be in contact with solder paste 16. In some embodiments, the encapsulation 14 may be spaced apart from the solder paste 16.

The electrical contacts 15 are part of a whole copper ball or a high melting point solder ball. The encapsulation 14 covers more than half of the entire ball to form a locking structure (encircled by a dashed circle) to prevent delamination (e.g., ball drop) between the electrical contacts 15 and the encapsulation 14. In other words, the distance H between the lower surface 102 of the substrate 10 and the surface 151 (e.g., the cutting surface) of the electrical contact 15 is less than the diameter of the entire metal ball. The surface 151 of the contact 15 has a width greater than the radius of the entire metal ball. The surface 151 of the contact 15 has a width less than the diameter of the entire ball (D1). The diameter of the electrical contact 15 can be adjusted as small as possible to meet the fine pitch requirement, so that a plurality of input/output terminals will be added.

In some embodiments, the electrical contacts 15 have a high melting point that is greater than the reflow temperature (e.g., 260 ℃). The electrical contact 15 includes a high melting point portion. The entire electrical contact 15 has a high melting point. The melting point of the high melting point portion of the electric contact 15 is larger than the melting points of the solder pastes 15s and 16. Therefore, the appearance of the electrical contact 15 will not be affected by high temperatures during the reflow operation, and thus the electrical contact 15 will be prevented from being deformed. Since the electrical contacts 15 can withstand the temperatures of the reflow operation, the distance H between the lower surface 102 of the substrate 10 and the surface 151 of the electrical contacts 15 is not limited (e.g., can be greater than, equal to, or less than the radius of the entire refractory ball). The distance H between the lower surface 102 of the substrate 10 and the surface 151 of the electrical contact 15 can be easily controlled so that the design window can be flexible. The thickness of the encapsulation 14 may be reduced. The size of the semiconductor device package 1 may be scaled.

Fig. 2A is a cross-sectional view of a semiconductor device package 2 according to some embodiments of the present disclosure. The semiconductor device package 2 is similar to the semiconductor device package 1 in fig. 1A, except that the electrical contacts 25 of the semiconductor device package 2 are full refractory metal balls (e.g., copper balls or refractory solder balls).

The encapsulation 14 includes recesses 14c to accommodate the electrical contacts 25. The electrical contacts 25 are disposed on conductive pads 10p on the surface 102 of the substrate 10. In some embodiments, the electrical contacts 25 extend beyond the surface 142 of the encapsulation 14 by a distance greater than or equal to 30 μm. In some embodiments, the electrical contacts 25 are in contact with the sidewalls of the recess 14c of the encapsulation 14. Alternatively, the electrical contacts 25 are spaced from the side walls of the recess 14c of the encapsulation 14. Depending on the different embodiments, the surface 131 of the electronic component 13 may be covered by the encapsulation 14 or exposed from the encapsulation 14.

In the case where the thickness of the encapsulation body 14 is thick, the size of the electrical contact 25 may be large. In a case where the thickness of the encapsulation body 14 is thin, the size of the electrical contact 25 may be small. The size of the groove 14c can be adjusted.

Fig. 2B is a cross-sectional view of an enlarged view of a portion of a semiconductor package device 2, according to some embodiments of the present disclosure. The electrical contacts 25 may be copper balls. In some embodiments, the electrical contacts 25 may be covered by a nickel (Ni) layer. In some embodiments, the thickness of the Ni layer is about 1 μm. The electrical contacts 25 are connected to the conductive pads 10p of the substrate 10 by solder paste 25 s.

The substrate 10 includes a dielectric layer 10 i. The dielectric layer 10i partially covers the conductive pad 10 p. The dielectric layer 10i is spaced apart from the solder paste 25s and the electrical contact 25. The encapsulation 14 is in contact with the dielectric layer 10i and the conductive pads 10 p. The encapsulation 14 may be in contact with the electrical contacts 25. The encapsulation 14 is spaced apart from the solder paste 25 s.

The recess 14c exposes at least a portion of the conductive pad 10p of the substrate 10. The grooves 14c expose the solder paste 25s and the electrical contacts 25.

Fig. 2C is a cross-sectional view of an enlarged view of a portion of a semiconductor package device 2' according to some embodiments of the present disclosure. The semiconductor package device 2' is similar to the semiconductor package device 2 except that the semiconductor package device 2' includes electrical contacts 25' having a relatively small size. For example, the electrical contacts 25' do not protrude beyond the lower surface 142 of the encapsulation 14. For example, the diameter of the electrical contact 25' is equal to or less than the depth of the groove 14 c. This arrangement will reduce the size of the electrical contacts 25' and the grooves 14c, which is suitable for fine pitch connections. The electrical contacts 25' may be copper balls. In some embodiments, the electrical contacts 25' may be covered by a Ni layer. In some embodiments, the thickness of the Ni layer is about 1 μm. The electrical contacts 25' are connected to the conductive pads 10p of the substrate 10 by solder paste 25 s.

Solder paste 26 is disposed on the electrical contacts 25' to prevent oxidation of the electrical contacts 25' and to provide an electrical connection between the semiconductor device package 2' and any other device or component. The solder paste 26 may serve as a conductive pad. The solder paste 26 is spaced from the encapsulation 14. In some embodiments, solder paste 26 may comprise the same material as solder paste 25 s. The solder paste 26 may contain a different material from the solder paste 25 s.

The recess 14c exposes at least a portion of the conductive pad 10p of the substrate 10. The grooves 14c expose the solder paste 25s, the electrical contacts 25, and the solder paste 26.

Fig. 2D is a cross-sectional view of a semiconductor device package 2 "in accordance with some embodiments of the present disclosure. The semiconductor device package 2 "is similar to the semiconductor device package 2 in fig. 2B, except that solder paste 25's is disposed on the conductive pads 10p and in contact with the dielectric layer 10 i. The electrical contacts 25 are disposed on the solder paste 25's. The solder paste 25's are exposed by the groove 14c of the encapsulation body 14.

The encapsulation 14 is in contact with the dielectric layer 10i and the solder paste 25's. The encapsulation 14 is in contact with the electrical contacts 25. In some embodiments, the encapsulation 14 is spaced apart from the electrical contacts 25.

Fig. 2E is a cross-sectional view of a semiconductor device package 2' ″ according to some embodiments of the present disclosure. Semiconductor device package 2' "is similar to semiconductor device package 2 in fig. 2A, except that conductive layer 21 is disposed on

encapsulants

12 and 14, and substrate 10 and a portion of electrical contacts 25" are disposed on conductive pads 10 p. The electrical contacts 25 "may include a solder material (e.g., Sn).

The conductive layer 21 is in contact with the

encapsulation

12 and 14 and the sidewalls of the substrate 10. Conductive layer 21 may serve as a shielding layer to improve electromagnetic interference (EMI) shielding. The conductive layer 21 may be added to the structure as illustrated and described with reference to fig. 1A, fig. 2A, fig. 3A, fig. 4B, or fig. 4C, within the spirit of the present disclosure.

Fig. 2F is a cross-sectional view of an enlarged view of a portion of a semiconductor package device 2' ″ according to some embodiments of the present disclosure. The substrate 10 includes a dielectric layer 10 i. The dielectric layer 10i partially covers the conductive pad 10 p. The dielectric layer 10i is spaced apart from the electrical contacts 25 ". The encapsulation 14 is in contact with the dielectric layer 10i and the conductive pads 10 p. The encapsulation 14 may be in contact with the electrical contacts 25 ".

The conductive pad 10p is partially exposed from the dielectric layer 10 i. The conductive pad 10p is partially exposed from the groove 14c of the encapsulation body 14. An electrical contact 25 "is disposed at least partially within the recess 14c and on a portion of the conductive pad 10 p.

Fig. 3A is a cross-sectional view of a semiconductor device package 3 according to some embodiments of the present disclosure. The semiconductor device package 3 is similar to the semiconductor device package 1 in fig. 1A, except that the electrical contacts 35 of the semiconductor device package 3 are whole refractory metal balls (e.g., copper balls or refractory solder balls).

The encapsulation 14 covers or encapsulates a portion of the electrical contacts 35. The encapsulation 14 partially exposes another portion of the electrical contacts 35. The portion of the electrical contact 35 is a high melting point portion. Solder paste 36 is disposed on the exposed portions of the electrical contacts 35 to provide an electrical connection. The solder paste 36 may act as a conductive pad. The solder paste 36 may prevent oxidation of the electrical contacts 35 and facilitate connection between the semiconductor device package 3 and any other device or component. The encapsulation 14 includes recesses 14c to accommodate the electrical contacts 35 and solder paste 36. The encapsulation 14 is spaced apart from the solder paste 36.

Fig. 3B is a cross-sectional view of an enlarged view of a portion of a semiconductor package device 3, according to some embodiments of the present disclosure. The electrical contacts 35 may be copper balls. In some embodiments, the electrical contacts 35 may be covered by a Ni layer. In some embodiments, the thickness of the Ni layer is about 1 μm. The electrical contacts 35 are connected to the conductive pads 10p of the substrate 10 by solder paste 35 s. The thickness of the electrical contacts 35 exposed from the encapsulation 14 is less than the radius of the electrical contacts 35.

The substrate 10 includes a dielectric layer 10 i. The dielectric layer 10i partially covers the conductive pad 10 p. The dielectric layer 10i is spaced apart from the solder paste 35s and the electrical contact 35. The encapsulation 14 is in contact with the dielectric layer 10i, the conductive pads 10p, the solder paste 35s, and the electrical contacts 35. The capsule 14 is in contact with the high melting point portions of the electrical contacts 35.

The diameter of the electrical contacts 35 is equal to or less than the thickness of the encapsulation 14. The electrical contacts 35 may not protrude beyond the surface 142 of the encapsulation 14 to provide an electrical connection. Accordingly, solder paste 36 (e.g., a solder pad) may be formed on the electrical contacts 35 to prevent oxidation of the electrical contacts 35 and provide a better electrical connection between the semiconductor device package 3 and any other device or component. This arrangement will reduce the size of the electrical contacts 35, suitable for fine pitch connections.

Fig. 3C is a cross-sectional view of an enlarged view of a portion of a semiconductor package device 3' according to some embodiments of the present disclosure. The semiconductor device package 3 'is similar to the semiconductor device package 3 in fig. 3B, except that the solder paste 35's completely covers the conductive pads 10'p of the substrate 10'. The substrate 10 'includes a dielectric layer 10' i. The dielectric layer 10'i is spaced apart from the solder paste 35's. The solder paste 35's are partially exposed by the groove 14c of the encapsulation body 14.

The encapsulation 14 is in contact with the dielectric layer 10'i and the solder paste 35's. The encapsulation 14 is in contact with the electrical contacts 35. In some embodiments, the encapsulation 14 is spaced apart from the electrical contacts 35.

In some embodiments, solder paste may be optionally formed on the electrical contacts 35 to prevent oxidation.

Fig. 4A is a cross-sectional view of a semiconductor device package 4, according to some embodiments of the present disclosure. The semiconductor device package 4 is similar to the semiconductor device package 1 in fig. 1A, except that the electrical contacts 45 are full metal balls and the encapsulation 44 has a stepped profile.

The encapsulation 44 is disposed on the lower surface 102 of the substrate 10 to cover or encapsulate the electronic component 13. Encapsulation body 44 includes an upper surface 441, a lower surface 442 opposite upper surface 441, and a lower surface 443 between upper surface 441 and lower surface 442. The distance between the lower surface 442 of the encapsulation 44 and the lower surface 102 of the substrate 10 is greater than the distance between the lower surface 443 of the encapsulation 44 and the lower surface 102 of the substrate 10.

The electrical contacts 45 are placed on the solder paste 45 s. The electrical contacts 45 are exposed by the encapsulation 44. The thickness of the encapsulation 44 (e.g., the distance between the upper surface 441 and the lower surface 443) may be flexibly adjusted depending on different design requirements.

The electrical contacts 45 include copper (Cu), an alloy (e.g., CuAg or CuAu), or a high melting point solder material (e.g., high melting point Sn).

Fig. 4B is a cross-sectional view of a semiconductor device package 4' according to some embodiments of the present disclosure. The semiconductor device package 4' is similar to the semiconductor device package 4 in fig. 4A, except that the surface 131 of the electronic component 13 is exposed by the encapsulation 44. The surface 131 of the electronic component 13 is substantially coplanar with the lower surface 442 of the encapsulation 44.

Fig. 4C is a cross-sectional view of a semiconductor device package 4 "according to some embodiments of the present disclosure. The semiconductor device package 4 "is similar to the semiconductor device package 4 in fig. 4A, except that the electrical contacts 45' comprise a solder material. Electrical contacts 45' are disposed on the conductive pads 10 p. The electrical contacts 45' are in contact with the substrate 10 and the encapsulation 44. The electrical contacts 45' are integrally formed.

Fig. 5A-5C illustrate some embodiments of methods of manufacturing a semiconductor device package 1, according to some embodiments of the present disclosure. The various figures have been simplified to more clearly present aspects of the disclosure.

Referring to fig. 5A, a method for manufacturing the semiconductor device package 1 includes providing a substrate 10. The solder paste 15s is disposed on the substrate 10.

Electronic components

11a and 11b are disposed on the upper surface 101 of the substrate 10. The electronic components 13 and the metal balls 15' are arranged on the lower surface 102 of the substrate 10. The metal balls 15' are placed on the solder paste 15 s. In some embodiments, the metal balls 15' may be formed by ball dropping, screen printing, electroplating, or any other suitable operation.

Encapsulation bodies

12 and 14 are formed on the upper surface 101 and the lower surface 102 of the substrate 10, respectively, to substantially cover the

electronic components

11a, 11b, and 13 and the metal balls 15'. In some embodiments, the

encapsulation bodies

12 and 14 are formed in a single molding operation. Alternatively, the

encapsulation bodies

12 and 14 may be formed in a separate molding operation.

In some embodiments, the metal balls 15' are formed of or include copper (Cu), an alloy (e.g., CuAg or CuAu), or a high melting point solder material (e.g., high melting point Sn). The melting point of the metal balls 15' is greater than the melting point of the solder paste 15 s. The metal balls 15' will not be affected by the reflow operation or any subsequent high temperature operation.

Referring to fig. 5B, a portion of the encapsulation 14 and the metal balls 15' are removed to form the electrical contacts 15 and expose the backside 131 of the electronic component 13. In some embodiments, the encapsulation 14 and the metal balls 15' are removed by, for example, a grinding operation or any other suitable operation. In some embodiments, half of the metal balls 15' are removed. Removing portions of the encapsulation 14 and the solder balls 15' may promote uniformity in the thickness of the encapsulation 14. For example, the uniformity of the thickness of the encapsulation 14 may be improved from +/-30 μm to +/-10 μm. Furthermore, no residual resin will remain on the electronic component 13. The polished surfaces 151 of the electrical contacts 15 have interfaces with the exposed grains. In some embodiments, the electrical contacts 15 and solder paste 16 comprising different materials may exhibit different colors at the interface. The electrical contact 15 includes a high melting point portion. The melting point of the high melting point portion of the electric contact 15 is larger than the melting point of the solder paste 15 s.

Referring to fig. 5C, the distance between the lower surface 102 of the substrate 10 and the lapped surface 151 of the electrical contacts 15 can be equal to, less than, or greater than the radius of the entire metal sphere. Solder paste 16 is formed on the lapped surfaces 151 of the electrical contacts 15 to form the semiconductor device package 1 as shown in fig. 1A. In some embodiments, the solder paste 16 may be formed by printing. In some embodiments, the thickness of the semiconductor device package 1 may be reduced to 0.7 millimeters (mm) or less compared to conventional double-sided molding modules. In addition, the bottom side mold cap can be reduced (e.g., from 180 μm to 80 μm). The solder paste 15s spreads onto the electrical contacts 15 during the thermal operation. The solder paste 16 spreads onto the electrical contacts 15 during thermal operation.

Fig. 6A-6C illustrate some embodiments of methods of manufacturing a semiconductor device package 2, according to some embodiments of the present disclosure. The various figures have been simplified to more clearly present aspects of the disclosure.

A substrate 10 is provided with reference to fig. 6A. The solder paste 25s is disposed on the substrate 10.

Electronic components

11a and 11b are disposed on the upper surface 101 of the substrate 10. The electronic components 13 and the solder paste 25s are disposed on the lower surface 102 of the substrate 10. The solder paste 25s is placed on the conductive pad 10 p. The

encapsulants

12 and 14 are formed on the upper surface 101 and the lower surface 102 of the substrate 10 to sufficiently cover the

electronic components

11a, 11b, and 13 and the solder paste 25 s. In some embodiments, the

encapsulation bodies

12 and 14 are formed in a single molding operation. Alternatively, the

encapsulation bodies

12 and 14 may be formed in a separate molding operation. In some embodiments, a grinding operation may be further performed to expose the backside 131 of the electronic component 13.

Referring to fig. 6B, one or more grooves 14c are formed to penetrate into the encapsulation 14 to expose the solder paste 25 s. In some embodiments, the groove 14c may be formed by laser ablation or any other suitable operation. Since the electrical contacts 25 to be formed in the grooves 14c will not be affected by the reflow operation, the size of the grooves 14c can be as small as possible. Thus, the offset window for operation may be increased.

Referring to fig. 6C, electrical contacts 25 are formed within the recesses 14C to form the semiconductor device package 2 as shown in fig. 2A. A conductive layer 21 is disposed over the

encapsulation

12 and 14 and a portion of the substrate 10. In some embodiments, the electrical contacts 25 may be formed by ball dropping. The solder paste 25s may bond the electrical contacts 25 to the conductive pads 10 p. The electrical contacts 25 extend beyond the lower surface 142 of the encapsulated body 14. In some embodiments, solder paste may be optionally formed on the electrical contacts 25 to prevent oxidation. The solder paste 25s spreads onto the electrical contacts 25 during the thermal operation.

The electrical contacts 25 include high melting point portions. The melting point of the high melting point portion of the electric contact 25 is larger than that of the solder paste 25 s.

The operations of fig. 6A-6C may be applied to the package structure as illustrated and described with reference to fig. 2C-2E, within the spirit of the present disclosure.

Fig. 7A-7D illustrate some embodiments of methods of manufacturing a semiconductor device package 3, according to some embodiments of the present disclosure. The various figures have been simplified to more clearly present aspects of the disclosure.

Referring to fig. 7A, a method for manufacturing the semiconductor device package 3 includes providing a substrate 10. The solder paste 35s is disposed on the substrate 10.

Electronic components

11a and 11b are disposed on the upper surface 101 of the substrate 10. Electronic components 13 and electrical contacts 35 are disposed on lower surface 102 of substrate 10. The electrical contacts 35 are disposed on the solder paste 35 s. The encapsulation 14 is formed on the lower surface 102 of the substrate 10 to substantially cover the electronic components 13 and the electrical contacts 35. In some embodiments, the

encapsulation bodies

12 and 14 are formed in a single molding operation. Alternatively, the

encapsulation bodies

12 and 14 may be formed in a separate molding operation.

The electrical contacts 35 include a high melting point portion. The melting point of the high melting point portion of the electrical contact 35 is greater than the melting point of the solder paste 35 s.

Referring to fig. 7B, a portion of the encapsulation 14 is removed to expose the backside 131 of the electronic component 13. In some embodiments, the encapsulation 14 is removed by, for example, a grinding operation or any other suitable operation. The electrical contacts 35 are still covered and encapsulated by the encapsulation 14.

Referring to fig. 7C, one or more recesses 14C are formed to expose the electrical contacts 35. In some embodiments, the groove 14c may be formed by laser ablation or any other suitable operation.

Referring to fig. 7D, a solder paste 36 is formed by printing to cover the exposed portions of the electrical contacts 35. The solder paste 36 prevents oxidation of the electrical contacts 35 and provides a better electrical connection between the semiconductor device package 3 and any other device or component. The solder paste 35s spreads onto the electrical contacts 35 during thermal operation. The solder paste 36 spreads onto the electrical contacts 35 during thermal operation.

Fig. 8A-8B illustrate some embodiments of methods of manufacturing a semiconductor device package 4, according to some embodiments of the present disclosure. The various figures have been simplified to more clearly present aspects of the disclosure.

Referring to fig. 8A, a method for manufacturing the semiconductor device package 4 includes providing a substrate 10. The solder paste 45s is disposed on the substrate 10.

Electronic components

11a and 11b are disposed on the upper surface 101 of the substrate 10. Electronic components 13 and electrical contacts 45 are disposed on lower surface 102 of substrate 10. The electrical contacts 45 are placed on the solder paste 45 s. The solder balls 45 may be formed by ball dropping, screen printing, electroplating, or any other suitable operation. An encapsulation 44 is formed on the lower surface 102 of the substrate 10 to substantially cover the electronic components 13 and the electrical contacts 45. In some embodiments, the

encapsulation bodies

12 and 44 are formed in a single molding operation. Alternatively, the

encapsulation bodies

12 and 44 may be formed in a separate molding operation.

The electrical contacts 45 include a high melting point portion. The melting point of the high melting point portion of the electric contact 45 is greater than that of the solder paste 45 s.

Referring to fig. 8B, a portion of the encapsulation 44 is removed to partially expose the electrical contacts 45 to form the semiconductor device package 4 in fig. 4A. The encapsulation 44 includes a stepped profile. In some embodiments, the encapsulation 44 may be removed by a laser polishing or plasma etching operation. The thickness of the encapsulation body 44 can be flexibly defined. For example, the distance between

surfaces

441 and 442 of encapsulation 44 may be adjusted. The distance between

surfaces

441 and 443 of the encapsulation body 44 can be adjusted. In some embodiments, solder paste may be optionally formed on the electrical contacts 45 to prevent oxidation. The solder paste 45s spreads onto the electrical contacts 45 during thermal operation.

As used herein, and not otherwise defined, the terms "substantially," "about," and "about" are used to describe and explain minor variations. When used in conjunction with an event or circumstance, the terms can encompass the exact occurrence of the event or circumstance, as well as a close approximation of the occurrence of the event or circumstance. For example, when used in conjunction with numerical values, the terms can encompass a range of variation of less than or equal to ± 10% of the stated value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. The term "substantially coplanar" may refer to two surfaces that are within microns along the same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm along the same plane.

As used herein, the singular terms "a", "an" and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component disposed "on" or "over" another component may encompass a situation in which the preceding component is directly on the succeeding component (e.g., in physical contact with the succeeding component), as well as a situation in which one or more intervening components are located between the preceding and succeeding components.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not to be construed in a limiting sense. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. The description may not be drawn to scale. Due to manufacturing processes and tolerances, there may be a distinction between artistic renderings in the present disclosure and actual equipment. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation.

Claims

1. A semiconductor device package, comprising:

a substrate comprising a conductive pad;

a first solder paste disposed on the pad;

an electrical contact disposed on the first solder paste, the electrical contact having a surface facing away from the substrate, wherein a melting point of the electrical contact is greater than a melting point of the first solder paste; and

a first encapsulation encapsulating a portion of the electrical contacts and exposing the surfaces of the electrical contacts, the first encapsulation including a first surface facing the substrate and a second surface opposite the first surface, wherein the second surface of the first encapsulation is exposed to air.

2. The semiconductor device package of claim 1, wherein the surfaces of the electrical contacts are substantially coplanar with the second surface of the first encapsulation.

3. The semiconductor device package of claim 1, wherein the electrical contacts comprise copper (Cu) or a high melting solder material.

4. The semiconductor device package of claim 1, further comprising a second solder paste disposed on the surfaces of the electrical contacts.

5. The semiconductor device package of claim 4, wherein the second solder paste has a melting point lower than the melting point of the electrical contacts.

6. The semiconductor device package of claim 1, wherein the first encapsulation includes a recess to accommodate the electrical contacts.

7. The semiconductor device package of claim 6, further comprising a second solder paste disposed on the surfaces of the electrical contacts, wherein the first encapsulant is spaced apart from the second solder paste.

8. The semiconductor device package of claim 6, wherein a thickness of the electrical contacts exposed from the first encapsulation is less than a radius of the electrical contacts.

9. The semiconductor device package of claim 6, wherein the recess exposes at least a portion of the conductive pad of the substrate.

10. The semiconductor device package of claim 6, wherein the first solder paste overlays the conductive pads of the substrate.

11. The semiconductor device package of claim 10, further comprising an insulating layer covering a portion of the conductive pad.

12. The semiconductor device package of claim 1, further comprising a first electronic component disposed on a first surface of the substrate and adjacent to the electrical contacts.

13. The semiconductor device package of claim 12, further comprising:

a second electronic component disposed on a second surface of the substrate opposite the first surface; and

a second encapsulation encapsulating the second electronic component.

14. A semiconductor device package, comprising:

a substrate comprising a conductive pad;

a first solder paste disposed on the conductive pad;

an electrical contact disposed on the first solder paste, wherein the electrical contact includes a high melting point portion, and the high melting point portion of the electrical contact has a melting point greater than a melting point of the first solder paste; and

an encapsulation encapsulating the electrical contact, wherein the encapsulation is in contact with the high melting point portion of the electrical contact.

15. The semiconductor device package of claim 14, wherein the electrical contacts comprise copper (Cu) or a high melting solder material.

16. The semiconductor device package of claim 14, further comprising a second solder paste disposed on exposed portions of the surfaces of the electrical contacts.

17. The semiconductor device package of claim 14, wherein the encapsulation includes a first surface facing the substrate and a second surface opposite the first surface, the second surface of the encapsulation at least partially exposing surfaces of the electrical contacts, the surfaces of the electrical contacts being substantially coplanar with the second surface of the encapsulation.

18. The semiconductor device package of claim 17, wherein the encapsulation includes a recess to accommodate an exposed portion of the surface of the electrical contact.

19. The semiconductor device package of claim 18, wherein a thickness of the electrical contacts exposed from the encapsulation is less than a radius of the electrical contacts.

20. A method of manufacturing a semiconductor package device, comprising:

disposing a first solder paste on a substrate;

disposing an electrical contact on the first solder paste, wherein the electrical contact comprises a high melting point portion having a melting point greater than a melting point of the first solder paste;

forming an encapsulation to encapsulate the electrical contacts, the encapsulation in contact with the high melting point portions of the electrical contacts; and

a second solder paste is disposed on the electrical contacts.

21. The method of claim 20, further comprising heating the first solder paste to diffuse the first solder paste onto the electrical contacts.

22. The method of claim 21, further comprising heating the second solder paste to diffuse the second solder paste onto the electrical contacts.

23. The method of claim 20, further comprising removing a portion of the encapsulation.

24. The method of claim 23, further comprising removing a portion of the electrical contact.

25. A semiconductor package device, comprising:

a substrate comprising a first surface, a second surface opposite the first surface, a conductive pad disposed adjacent to the first surface, and an insulating layer disposed on the conductive pad, wherein the insulating layer exposes a portion of the conductive pad;

a first encapsulation encapsulating the insulating layer, wherein the encapsulation includes a recess exposing the portion of the conductive pad; and

an electrical contact disposed at least partially within the recess and disposed on the portion of the pad.

26. The semiconductor packaging device of claim 25, wherein the encapsulation contacts the portion of the conductive pad.

27. The semiconductor package device of claim 26, further comprising a first solder paste disposed between the conductive pads and the electrical contacts.

28. The semiconductor packaging device of claim 25, further comprising a second encapsulant encapsulating the second surface of the substrate.

29. The semiconductor packaging device of claim 28, further comprising a conductive layer disposed over the first encapsulant, the second encapsulant, and a portion of the substrate.