CN110634750A

CN110634750A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN110634750A
Application number: CN201910424852.6A
Authority: CN
Inventors: 王垂堂; 蔡仲豪; 余振华
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-06-22
Filing date: 2019-05-21
Publication date: 2019-12-31

Abstract

A semiconductor device includes: a rewiring structure; a semiconductor device located on the rewiring structure; a top package over the semiconductor device, the top package including a second semiconductor device; a molding compound interposed between the redistribution structure and the top package; a set of vias between the top package and the rewiring structure and electrically connecting the top package to the rewiring structure; and an interconnect structure disposed within the molding compound and electrically connecting the top package to the redistribution structure, the interconnect structure including a substrate and a passive device formed in the substrate, wherein the interconnect structure does not include an active device.

Description

Semiconductor device and method for manufacturing the same

Technical Field

Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same.

Background

The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this improvement in integration density stems from the ever-decreasing minimum feature sizes (e.g., semiconductor process nodes shrinking towards nodes below 20 nm), which allows more components to be integrated into a given area. Recently, as the demand for miniaturization, higher speed and greater bandwidth, and lower power consumption and latency increases, more subtle and innovative semiconductor die packaging techniques are needed.

As semiconductor technology has advanced further, stacked semiconductor devices and bonded semiconductor devices have emerged as an effective alternative to further reduce the physical size of semiconductor devices. In stacked semiconductor devices, active circuitry (e.g., logic, memory, processor circuitry, etc.) is fabricated at least partially on respective substrates and then physically and electrically bonded together to form a functional device. Such bonding processes utilize sophisticated techniques and improvements are desired.

Disclosure of Invention

An embodiment of the present invention provides a semiconductor device, including: a rewiring structure; a first semiconductor device located on the rewiring structure; a top package over the first semiconductor device, the top package including a second semiconductor device; a molding compound between the redistribution structure and the top package; a first set of vias between the top package and the rewiring structure and electrically connecting the top package to the rewiring structure; and a first interconnect structure disposed within the molding compound and electrically connecting the top package to the rewiring structure, the first interconnect structure including a substrate and a passive device formed in the substrate, wherein the first interconnect structure does not include an active device.

An embodiment of the present invention provides a semiconductor device, including: a rewiring structure; a package including a first semiconductor device and a second semiconductor device disposed on a package substrate, the package disposed over the redistribution structure; a third semiconductor device disposed between the rewiring structure and the package substrate and electrically connected to the rewiring structure; a via extending between the rerouting structure and the package substrate, the via electrically connecting the rerouting structure to the package substrate; a first passive device structure disposed between the package substrate and the rewiring structure, the first passive device structure comprising: a first substrate; a first passive device disposed on the first substrate; a first via extending through the first substrate and electrically connected to the first passive device; and a second via extending through the first substrate, wherein the first via and the second via are electrically connected to the rerouting structure and to the first semiconductor device; a second passive device structure disposed between the package substrate and the rerouting structure, the second passive device structure comprising: a second substrate; a second passive device disposed on the second substrate; a third via extending through the second substrate and electrically connected to the second passive device; and a fourth via extending through the second substrate, wherein the third via and the fourth via are electrically connected to the rerouting structure and to the second semiconductor device; and a molding compound surrounding each of the first passive device structure, the second passive device structure, the via, and the third semiconductor device.

An embodiment of the present invention provides a method of manufacturing a semiconductor device including: forming a set of vias in a carrier substrate; placing a first die on the carrier substrate, the first die being spaced apart from the set of vias; and placing a first interconnect structure on the carrier substrate, the first interconnect structure being spaced apart from the first die and the set of vias. The first interconnect structure includes: a substrate; a first conductive element and a second conductive element extending from a first side of the substrate to a second side of the substrate; a metallization layer disposed over and electrically connected to the first and second conductive elements; and an integrated passive device, wherein the integrated passive device is electrically connected to the first conductive element and the second conductive element through the metallization layer; encapsulating the set of vias, the first die, and the first interconnect structure in an encapsulant, wherein the encapsulant is in physical contact with the set of vias, the first die, and the first interconnect structure; and placing a top package over the set of vias, the first die, and over the first side of the first interconnect structure, wherein the top package includes a second die, and wherein placing the top package includes electrically connecting the second die to the integrated passive device.

Drawings

The aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 through 6 illustrate the formation of an interconnect structure according to some embodiments.

Fig. 7-14 illustrate formation of a package structure including an interconnect structure according to some embodiments.

Fig. 15 illustrates a package structure including an interconnect structure according to an embodiment.

Fig. 16A to 16B illustrate an interconnect structure and a package structure including the interconnect structure according to another embodiment.

Fig. 17 illustrates a package structure including an interconnect structure according to another embodiment.

Fig. 18A to 18B illustrate an interconnect structure and a package structure including the interconnect structure according to another embodiment.

Fig. 19A-19C illustrate an interconnect structure and a package structure including the interconnect structure according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Fig. 1-6 illustrate the formation of an example of an interconnect structure 650 according to some embodiments. Referring now to fig. 1, a first substrate 101 and an Integrated Passive Device (IPD) 103 are shown. The first substrate 101 may comprise doped or undoped silicon, another semiconductor material, a silicon-on-insulator (SOI) substrate, silicon dioxide (SiO), a silicon-on-insulator (SOI) substrate₂) Or other insulating material or another material. In some embodiments, the first substrate 101 has a thickness between about 50 μm and about 400 μm, such as about 150 μm. In the embodiments shown in fig. 1 to 6, the IPD103 is shown as a deep-trench capacitor (deep-trench capacitor), but in other embodiments, the IPD103 may comprise one or more other types of passive devices, such as resistors, inductors, other types of capacitors, and so forth.

The IPD103 may be formed within the first substrate 101 or on the first substrate 101 using any suitable method. For example, a deep trench capacitor can be formed by first forming one or more trenches in the first substrate 101. The trenches may be formed by any suitable photolithographic masking and etching process. For example, a photoresist can be formed over the first substrate 101 and patterned, and one or more etching processes (e.g., dry etching processes) can be utilized to remove those portions of the first substrate 101 where the presence of deep trench capacitors is desired. In some embodiments, the one or more trenches are formed to have a depth of between about 1 μm and about 15 μm. The first capacitor electrode may be formed, for example, by forming the first conductive electrode material 105 in the one or more trenches by a deposition process or another process. The excess portions of the first conductive electrode material 105 may be removed using, for example, a suitable photolithographic masking and etching process. For example, a photoresist may be formed over the first conductive electrode material 105 and patterned, and one or more etching processes (e.g., wet etching processes or dry etching processes) may be utilized to remove excess portions of the first conductive electrode material 105. In some embodiments, the remaining portion of the first conductive electrode material 105 may extend above the top surface of the substrate 101. The first conductive electrode material 105 may be one or more layers of conductive material, such as doped silicon, polysilicon, copper, tungsten, an aluminum alloy, or a copper alloy, the like, combinations thereof, or another conductive material. The first conductive electrode material 105 may be formed to have a thickness between about 0.05 μm and about 1 μm.

A dielectric layer 107 may be formed over the first conductive electrode material 105 within the one or more trenches. The dielectric layer 107 may comprise a high-K dielectric material, an oxide, a nitride, etc., or a combination or multiple layers thereof, and may be formed using any suitable deposition process, such as a Chemical Vapor Deposition (CVD) process. The excess portions of the dielectric layer 107 may be removed using, for example, a suitable photolithographic masking and etching process. For example, a photoresist may be formed over the dielectric layer 107 and patterned, and one or more etching processes (e.g., wet etching processes or dry etching processes) may be utilized to remove excess portions of the dielectric layer 107. In some embodiments, the remaining portion of the dielectric layer 107 may extend over the portion of the first conductive electrode material 105 disposed on the top surface of the substrate 101. The dielectric layer 107 may be formed to have a thickness between about 1nm and about 100 nm.

A second conductive electrode material 109 may be formed over the dielectric layer 107 in the one or more trenches, such as by a deposition process or another process, to form a second capacitor electrode. The excess portion of the second conductive electrode material 109 may be removed using, for example, a suitable photolithographic masking and etching process. For example, a photoresist may be formed over the second conductive electrode material 109 and patterned, and one or more etching processes (e.g., a wet etching process or a dry etching process) may be utilized to remove excess portions of the second conductive electrode material 109. In some embodiments, the remaining portion of the second conductive electrode material 109 may extend over the portion of the dielectric layer 107 disposed over the top surface of the substrate 101. The second conductive electrode material 109 may be one or more layers of conductive material, such as doped silicon, polysilicon, copper, tungsten, an aluminum alloy, or a copper alloy, the like, combinations thereof, or another conductive material. The second conductive electrode material 109 may be formed to have a thickness between about 0.05 μm and about 1 μm. The above-described process for forming a deep trench capacitor is but one method of forming a deep trench capacitor, and other methods are fully intended to be included within the scope of the embodiments.

The IPD103 may comprise one deep trench capacitor or may comprise a plurality of deep trench capacitors. In some embodiments, the deep trench capacitor can include one trench or a plurality of trenches. For example, when forming a deep trench capacitor, the first conductive electrode material 105, the dielectric layer 107, and the second conductive electrode material 109 can be formed over a single trench or can be formed to extend over multiple trenches.

Fig. 2 shows that through-substrate-via (TSV) 201 is formed in the first substrate 101. The TSV201 may be formed, for example, by: a dielectric layer 203 is formed over the first substrate 101 and the IPD103, then an opening is etched through the dielectric layer 203 and into the first substrate 101, and then a conductive material is deposited in the opening. The dielectric layer 203 may be one or more layers of, for example, oxide, nitride, polymer, composite, or another dielectric material. In an embodiment, the dielectric layer 203 covers the second conductive electrode material 109 after formation. The dielectric layer 203 is then thinned to expose the second conductive electrode material 109. The thinning may be performed, for example, using a mechanical grinding or Chemical Mechanical Polishing (CMP) process. Suitable photolithographic masking and etching processes may be used to form the openings in the first substrate 101. For example, a photoresist may be formed and patterned over the dielectric layer 203 and the first substrate 101, and one or more etching processes (e.g., wet etching processes or dry etching processes) may be utilized to remove those portions of the dielectric layer 203 and the first substrate 101 where the TSV201 is desired. After forming the opening for the TSV201, the opening for the TSV201 may be filled with, for example, a barrier layer (barrier layer) and a conductive material. The barrier layer may comprise a conductive material such as titanium nitride, although other materials may be utilized such as tantalum nitride, titanium, dielectric materials, and the like. The barrier layer may be formed using a CVD process, such as Plasma Enhanced CVD (PECVD). However, other alternative processes may be used, such as sputtering or Metal Organic Chemical Vapor Deposition (MOCVD). A barrier layer may be formed to define (contour) the underlying shape of the opening for the TSV 201.

The conductive material may include one or more conductive materials, such as copper, tungsten, other conductive metals, the like, or combinations thereof. The conductive material may be formed, for example, by: a seed layer (not separately shown) is deposited and an electrically conductive material is deposited onto the seed layer, filling and overfilling the openings for the TSVs 201, using electroplating, electroless plating, or the like. After the opening for the TSV201 has been filled, the excess barrier layer and the excess conductive material outside the opening for the TSV201 (e.g., over the dielectric layer 203) may be removed by a grinding process, such as Chemical Mechanical Polishing (CMP), although any suitable removal process may be used. In some embodiments, the grinding process exposes the conductive material of the TSV201 and/or the second conductive electrode material 109. In an embodiment, the TSV201 has a width between about 5 μm and about 50 μm, such as about 10 μm. The above-described process for forming the TSV201 is but one method of forming the TSV201, and other methods are fully intended to be included within the scope of the embodiments.

The example structure shown in fig. 1-6 includes four TSVs 201, but in other embodiments, the structure may include another number of TSVs 201. For example, the structure may include two TSVs 201, three TSVs 201, six TSVs 201, or another number of TSVs 201. Further, for purposes of illustration only, the TSVs 201 are shown as being arranged as adjacent pairs of TSVs 201. In other embodiments, the TSVs 201 may be formed without being adjacent to another TSV201, or may be formed adjacent to two or more TSVs 201. As described below, adjacent TSVs 201 (see fig. 6) may be electrically connected within the first interconnect layer 301 and/or through metal contacts 603. The use of the plurality of TSVs 201 electrically connected may reduce resistance and improve electrical performance. These and other configurations of TSVs 201 are fully intended to be included within the scope of the embodiments.

Turning to fig. 3, a first interconnect layer 301 is formed over the first substrate 101 and the first interconnect layer 301 is designed to become the respective IPDs 103 and TSVs 201 and provide electrical connections between the respective IPDs 103 and TSVs 201. In some embodiments, the first interconnect layer 301 may be formed to be electrically connected to the IPD103 and the TSV201 through, for example, a conductive line, trace or via. For example, in some embodiments, a first insulating layer 303 is formed over the first substrate 101. The first insulating layer 303 can be made of one or more suitable dielectric materials, such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), a polymer material, a low-k dielectric material, another dielectric material, combinations of these materials, and the like. The first insulating layer 303 can be formed by a process such as spin coating, lamination, CVD, or the like, or a combination thereof. The first insulating layer 303 may have a thickness between about 0.1 μm and about 15 μm, although any suitable thickness may be used.

Suitable photolithographic masking and etching processes may be used to form openings in the first insulating layer 303. For example, a photoresist may be formed over the first insulating layer 303 and patterned, and portions of the first insulating layer 303 may be removed using one or more etching processes (e.g., wet or dry etching processes) to expose regions of the second conductive electrode material 109 or TSVs 201. In some embodiments, portions of the dielectric layer 203 may also be removed to expose portions of the first conductive electrode material 105.

In an embodiment, the first interconnect layer 301 may be formed by first forming a seed layer (not shown) comprising one or more layers of titanium, copper, or a titanium copper alloy by a suitable formation process (e.g., PVD, CVD, sputtering, etc.). The seed layer is formed over the first insulating layer 303 and over an exposed region of the first conductive electrode material 105, an exposed region of the second conductive electrode material 109, or an exposed region of the TSV 201. A photoresist (also not shown) may then be formed to cover the seed layer and then patterned to expose those portions of the seed layer where the first interconnect layer 301 will be subsequently formed. After the photoresist has been formed and patterned, a conductive material may be formed on the seed layer. The conductive material may be a material such as copper, titanium, tungsten, aluminum, another metal, combinations, and the like. The conductive material may be formed by a deposition process such as electroplating or electroless plating. However, while the materials and methods discussed are suitable for forming the conductive material, these materials are merely exemplary. The first interconnection layer 301 may alternatively be formed using any other suitable material or any other suitable formation process (e.g., CVD or PVD). After the conductive material has been formed, the photoresist may be removed by a suitable removal process, such as ashing (ashing) or chemical stripping. In addition, after removing the photoresist, those portions of the seed layer that are covered by the photoresist may be removed by, for example, a suitable wet or dry etch process that may use the conductive material as an etch mask. The seed layer and the remaining portion of the conductive material form a first interconnect layer 301.

In some embodiments, the first interconnect layer 301 comprises multiple layers of dielectric and conductive materials, and may be formed by any suitable process, such as suitable photolithographic masking and etching processes, deposition, damascene (dalamascene), dual damascene, etc. In some embodiments, the material of the first insulating layer 303 is the same as the material of the dielectric layer 203, but may be different in other embodiments.

The first interconnect layer 301 may be configured to electrically connect adjacent TSVs 201 and may also be configured to connect the TSVs 201 to the IPD 103. In some embodiments where the IPD103 includes deep trench capacitors, the first interconnect layer 301 may connect one TSV201 (or a group of adjacent TSVs 201) to a first electrode (e.g., the first conductive electrode material 105) of one or more deep trench capacitors and another TSV201 (or another group of adjacent TSVs 201) to a second electrode (e.g., the second conductive electrode material 109) of the one or more deep trench capacitors. For example, as shown in fig. 3, the TSV labeled 201A is connected to the second conductive electrode material 109 of the IPD103 through the first interconnect layer 301, and the TSV labeled 201B is connected to the first conductive electrode material 105 of the IPD103 through the first interconnect layer 301. This is an illustrative example, and other configurations may exist. In some embodiments, the one or more TSVs 201 connected to a first electrode may be configured to conduct a first voltage or a first current, and the one or more TSVs 201 connected to a second electrode may be configured to conduct a second voltage or a second current. In some embodiments, the TSV201 may be configured to transmit a supply voltage, which may be, for example, a positive voltage, a negative voltage, or a ground voltage. In some embodiments, the TSV201 may be configured to conduct an electrical signal, such as a voltage signal or a current signal. As a non-limiting example, during operation of the package structure 1450 described below in fig. 14, one or more TSVs 201 may transmit electrical signals between the rerouting structure 1001 and the top package 1400, and/or one or more TSVs 201 may transmit supply voltages from the rerouting structure 1001 to the top package 1400.

Referring now to fig. 4, a second insulating layer 305, a first protective layer 401, a bonding pad 403, and a first external connector 405 are shown. In an embodiment, the second insulating layer 305 is formed in-process and over the first interconnect layer 301 and the first insulating layer 303 using a material similar to the first insulating layer 303. Alternatively, the second insulating layer 305 may be formed differently from the first insulating layer 303. The second insulating layer 305 may have a thickness between about 0.1 μm and about 15 μm, although any suitable thickness may be used. After forming the second insulating layer 305, an opening may be formed through the second insulating layer 305 to expose a portion of the first interconnect layer 301 to form further connections. The openings may be formed by suitable masking and removal processes, such as suitable photolithographic masking and etching processes.

Then, the bonding pads 403 may be formed over the first interconnect layer 301 and the bonding pads 403 are formed to be in electrical contact with the first interconnect layer 301. The bond pad 403 may comprise one or more conductive materials, such as copper, titanium, tungsten, aluminum, another metal, combinations, and the like. The conductive material of the bond pads 403 may be formed using a deposition process such as electroplating or electroless plating. However, while the materials and methods discussed are suitable for forming conductive materials, these materials are merely exemplary. The bond pads 403 may alternatively be formed using any other suitable material or any other suitable formation process (e.g., CVD or PVD). In some embodiments, the bonding pads 403 may be formed in a similar manner as the first interconnect layer 301 (see fig. 3) or using a similar material as the first interconnect layer 301. The bond pad 403 may have a thickness between about 0.5 μm and about 10 μm, such as about 3 μm, although any suitable thickness may be used.

A first passivation layer 401 may be formed over the first interconnect layer 301 and the bonding pads 403 to protect the first interconnect layer 301 and the bonding pads 403 from physical and environmental damage during subsequent processing and environmental conditions. The first protective layer 401 may be formed of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics (e.g., carbon-doped oxides), very low-k dielectrics (e.g., porous carbon-doped silicon dioxide), combinations of these materials, and the like. In some embodiments, the first protective layer 401 may be Polybenzoxazole (PBO), but any suitable material may be utilized, such as polyimide or a polyimide derivative. The first protective layer 401 may be formed by a process such as spin coating, lamination, CVD, or the like, or a combination thereof. The first protective layer 401 may have a thickness between about 0.5 μm and about 10 μm, such as about 3 μm, although any suitable thickness may be used.

After forming the first protective layer 401, an opening may be formed through the first protective layer 401 to expose a portion of the bonding pad 403 to form further connections. The openings may be formed by suitable masking and removal processes, such as suitable photolithographic masking and etching processes. However, the discussed patterning process disclosed is intended only as a representative process, and any other suitable patterning process may be utilized to expose a portion of the bond pad 403.

In an embodiment, the first external connector 405 may be a conductive post (e.g., a copper post or a copper rod). The first external connector 405 may be formed, for example, by deposition, electroplating, electroless plating, or the like. For example, a seed layer (not shown) may first be formed within the openings of both the first protection layer 401 and the photoresist, and then the material of the first external connectors 405 may be grown on the seed layer using a suitable technique. After the first external connectors 405 have been formed using photoresist, a suitable removal process, such as an ashing process or wet chemical clean, may be used to remove the photoresist and remove excess material of the seed layer. Removing the photoresist may expose the first external connector 405 such that the first external connector 405 protrudes beyond the surface of the first protective layer 401. Embodiments, however, are not limited to only these pillars, and may be solder bumps, copper bumps, or include one or more conductive materials, such as copper, tungsten, other conductive metals, and the like. Other suitable first external connectors 405 may be formed to provide electrical connections. All such external contacts are fully intended to be included within the scope of the embodiments.

Turning to fig. 5, a Die Attach Film (DAF) 501 is formed over the first protective layer 401 and the first external connector 405. The DAF501 may comprise materials such as epoxy, phenolic, acrylic rubber, silica fillers, adhesive layers, polymeric materials, or combinations thereof, and is applied using lamination techniques or another suitable technique. The DAF501 may be formed to have a thickness between about 1 μm and about 50 μm, such as about 20 μm, although any suitable thickness may be used.

Turning to fig. 6, a thinning process is performed on the backside of the first substrate 101 to expose the TSV201 for further processing and to form metal contacts 603. The structure shown in fig. 6 is in an inverted orientation relative to the orientation of fig. 1-5. Thinning (e.g., using a mechanical grinding or CMP process) may be performed on the first substrate 101 until the conductive material of the TSV201 has been exposed. As such, the TSV201 may be formed to have a first thickness between about 50 μm and about 200 μm, such as about 100 μm. In an embodiment, the TSV201 has a cross-sectional thickness to width aspect ratio of between about 3:1 and about 15:1 (e.g., about 5: 1). Optionally, the TSVs 201 may be recessed within the first substrate 101 after the first substrate 101 has been thinned. In some embodiments, an additional etch may be performed on the first substrate 101 such that the TSV201 protrudes from the first substrate 101. In an embodiment, the TSV201 may be recessed using, for example, an etching process that may utilize an etchant that is selective to the material of the TSV201 (e.g., selective to copper).

Referring now to fig. 6, a second protective layer 601 covered by a third protective layer 605 and a metal contact 603 are shown. Metal contacts 603 may be formed to interconnect the TSV201 with external semiconductor devices (described below). In an embodiment, a second protective layer 601 is formed over the back side of the first substrate 101. In some embodiments, the second protective layer 601 is a polymeric material. In some embodiments, the second protective layer 601 comprises one or more of the same materials described above with reference to the first insulating layer 303 or the first protective layer 401. The second protective layer 601 can be formed using a process similar to that described above with respect to the first insulating layer 303 or the first protective layer 401. In other embodiments, the second protective layer 601 can be formed in a different manner and material than described for the first insulating layer 303 or the first protective layer 401. The second protective layer 601 may be formed to have a thickness between about 5 μm and about 25 μm, such as about 7 μm, although any suitable thickness may be used.

Suitable photolithographic masking and etching processes may be used to form openings in the second protective layer 601. For example, a photoresist may be formed and patterned over the second protective layer 601, and portions of the second protective layer 601 are removed using one or more etching processes (e.g., wet etching processes or dry etching processes) to expose regions of the TSV 201.

In an embodiment, the metal contact 603 may be formed by first forming a seed layer (not shown) comprising one or more layers of titanium, copper, or a titanium-copper alloy by a suitable formation process, such as PVD, CVD, sputtering, or the like. The seed layer is formed over the second protective layer 601 and the exposed region of the TSV 201. A photoresist (also not shown) may then be formed to cover the seed layer and then patterned to expose those portions of the seed layer where the metal contacts 603 will be subsequently formed. After the photoresist has been formed and patterned, a conductive material may be formed on the seed layer. The conductive material may be a material such as copper, titanium, tungsten, aluminum, another metal, combinations, and the like. The conductive material may be formed by a deposition process such as electroplating or electroless plating. However, while the materials and methods discussed are suitable for forming conductive materials, these materials are merely exemplary. Any other suitable material or any other suitable formation process (e.g., CVD or PVD) may alternatively be used to form the metal contacts 603. After the conductive material has been formed, the photoresist may be removed by a suitable removal process, such as ashing or chemical stripping. In addition, after removing the photoresist, those portions of the seed layer that are covered by the photoresist may be removed by, for example, a suitable wet or dry etch process that may use the conductive material as an etch mask. The remaining portions of the seed layer and the conductive material form metal contacts 603.

In other embodiments, other techniques may be used to form metal contacts 603. For example, metal contact 603 may be formed by: a layer of conductive material is formed using a deposition process such as sputtering, and portions of the layer of material may then be removed by a suitable process (e.g., photolithographic masking and etching). As shown in fig. 6, the metal contact 603 may extend over and electrically connect two or more TSVs 201, but in some embodiments the metal contact 603 may not electrically connect some TSVs 201. Metal contact 603 may be formed to have a thickness between about 5 μm and about 25 μm, such as about 7 μm, although any suitable thickness may be used.

As shown in fig. 6, a third protective layer 605 is formed over the second protective layer 601 and the metal contact 603. In an embodiment, the third protective layer 605 may be a polymer such as Polybenzoxazole (PBO), but any suitable material may alternatively be used, such as polyimide or a polyimide derivative, Solder Resist (SR), Ajinomoto build-up film (ABF), or another material. The third protective layer 605 may be placed to a thickness of between about 5 μm and about 25 μm, such as about 7 μm, using, for example, a spin coating process, although any suitable method and thickness may alternatively be used. In some embodiments, DAF materials may be used for the third protective layer 605, such as the DAF materials described above with reference to DAF 501. In some embodiments, the third protective layer 605 is optional and may be omitted.

As such, an interconnect structure 650 including IPD103 and TSV201 is formed, as shown in fig. 6. In some embodiments, a single substrate may be used to form multiple interconnect structures 650 and then singulated to form individual interconnect structures 650. In some embodiments, the interconnect structure 650 includes passive devices and does not include active devices. The processes illustrated in fig. 1-6 are exemplary processes for forming the interconnect structure 650, and in other embodiments, other suitable techniques or processes may be used to form the interconnect structure 650, which are considered to be within the scope of the present invention.

In some embodiments, the interconnect structure (e.g., interconnect structure 650) may be included in an integrated fan out package-on-package (InFO-POP) as discussed below with reference to FIGS. 7-15. Referring now to fig. 7, a carrier substrate 701 is shown with a release layer 703, a fourth protective layer 705, and a first seed layer 707 over the carrier substrate 701. The carrier substrate 701 may comprise, for example, a silicon-based material (e.g., a glass material or silicon oxide) or other materials (e.g., aluminum oxide), combinations of these materials, and the like. The carrier substrate 701 may be planar to accommodate semiconductor devices (e.g., interconnect structures 850 and first semiconductor devices 801 described below).

The release layer 703 may be formed of a polymer-based material, and the release layer 703 may be removed along with the carrier substrate 701 from overlying structures formed in subsequent steps. In some embodiments, the release layer 703 is an epoxy-based Heat release material that loses its tackiness when heated, such as a Light-to-Heat-Conversion (LTHC) release coating. In other embodiments, the release layer 703 may be an Ultraviolet (UV) glue that loses its tackiness upon exposure to UV light. The release layer 703 may be dispensed as a liquid and cured, and the release layer 703 may be a laminate film or the like laminated onto the carrier substrate 701. The top surface of the release layer 703 may be planarized and may have a high co-planarity.

A fourth protection layer 705 is disposed over the release layer 703 and is used to provide protection for the interconnect structure 850 or the first semiconductor device 801, for example, as described below. In an embodiment, the fourth protective layer 705 may be a polymer material such as polybenzoxazole, but any suitable material may alternatively be used, such as polyimide or a polyimide derivative, a solder resist, an ajinomoto composition film, or another material. The fourth protective layer 705 may be placed using, for example, a spin-on process to a thickness of between about 2 μm and about 15 μm, such as about 5 μm, although any suitable method and thickness may alternatively be used.

The first seed layer 707 is formed over the fourth protective layer 705. In an embodiment, the first seed layer 707 is a thin layer of conductive material that assists in forming a thicker layer during subsequent processing steps. The first seed layer 707 may for example comprise a titanium layer as well as a copper layer, but other materials or combinations of materials may be used. The first seed layer 707 is generated using a process such as sputtering, evaporation or PECVD process depending on the desired material. The first seed layer 707 may be formed to have a thickness between about 0.3 μm and about 1 μm, such as about 0.5 μm.

Fig. 7 also shows placing a perforated mask 709 over the first seed layer 707 and patterning the perforated mask 709. In an embodiment, the perforation mask 709 may comprise photoresist, and the perforation mask 709 may be placed on the first seed layer 707 using, for example, a spin coating technique to a height of between about 50 μm and about 250 μm, for example, about 120 μm. After placing the aperture mask 709, the aperture mask 709 may be patterned using suitable photolithography techniques. In an embodiment, the pattern formed in the perforation mask 709 exposes portions of the first seed layer 707 to form the vias 711. In some embodiments, vias 711 are formed as vias or other conductive elements located on different sides or the same side of a subsequently attached device (e.g., first semiconductor device 801 or interconnect structure 650). However, any suitable arrangement of the pattern of vias 711 may alternatively be utilized. Fig. 7 shows two vias 711, but more or fewer vias 711 may be formed in other embodiments.

In an embodiment, the vias 711 comprise one or more conductive materials, such as copper, tungsten, other conductive materials, and the like. The via hole 711 may be formed, for example, by electroplating, electroless plating, or the like. After the vias 711 have been formed, the via mask 709 may be removed using a suitable removal process (e.g., a wet chemical etch or ashing process). Removing the perforation mask 709 may expose portions of the underlying first seed layer 707. The exposed portions of the first seed layer 707 may then be removed by, for example, a wet etch process or a dry etch process. After the exposed portions of the first seed layer 707 have been removed, some portions of the fourth protection layer 705 are exposed between the vias 711.

Fig. 8 illustrates the placement of a first semiconductor device 801 and a plurality of interconnect structures 850 onto a fourth protective layer 705. One or more of interconnect structures 850 shown in fig. 8 may be similar to interconnect structure 650 described above with reference to fig. 6, or may be similar to interconnect structure 852, interconnect structure 854, or interconnect structure 856 described with reference to fig. 16A-19C, although in some embodiments one or more of interconnect structures 850 may be different from interconnect structure 650, interconnect structure 852, interconnect structure 854, or interconnect structure 856. In some embodiments, different interconnect structures 850 placed on the fourth protection layer 705 may have different characteristics, such as different configurations of TSVs 201, different IPDs 103, or other different characteristics. In some embodiments, there may be more or fewer interconnect structures 850 than shown in fig. 8. In some embodiments, one or more interconnect structures 850 may be placed between two vias 711 or between a via 711 and a first semiconductor device 801. The interconnect structure 850 may be placed in an orientation such that the IPD (e.g., IPD 103) faces toward the fourth protective layer 705, but in other embodiments, the interconnect structure 850 may be oriented such that the IPD faces away from the fourth protective layer 705.

The first semiconductor device 801 shown in fig. 8 may be a semiconductor device designed for an intended purpose, such as a memory die (e.g., a Dynamic Random Access Memory (DRAM) die), a logic die, a Central Processing Unit (CPU) die, a combination of these dies, or the like. In an embodiment, integrated circuit devices such as transistors, capacitors, inductors, resistors, metallization layers, external connectors, and the like are included in the first semiconductor device 801 depending on the particular functionality desired.

In an embodiment, the interconnect structure 850 and the first semiconductor device 801 may be placed on the fourth protective layer 705 using, for example, a pick-and-place process. However, any other alternative method may be used to place the interconnect structure 850 or the first semiconductor device 801.

Fig. 9 illustrates the use of an encapsulant 901 to encapsulate via 711, first semiconductor device 801, and interconnect structure 850. Encapsulation may be performed in a molding apparatus, or another technique may be used to deposit the encapsulant 901. The encapsulant 901 may be a molding compound such as resin, polyimide, Polyphenylene sulfide (PPS), Polyetheretherketone (PEEK), Polyethersulfone (PES), another material, a combination of these materials, or the like. Fig. 9 also illustrates thinning of the encapsulant 901 to expose the vias 711, metal contacts of the first semiconductor device 801, and metal contacts of the interconnect structure 850 (e.g., metal contacts 603) for further processing. The thinning may be performed, for example, using mechanical grinding or Chemical Mechanical Polishing (CMP). Thus, via 711, first semiconductor device 801, and interconnect structure 850 may have planar surfaces that are also flush with encapsulant 901.

Fig. 10 illustrates the formation of a re-routing structure 1001 to interconnect the via 711, the first semiconductor device 801, and the interconnect structure 850 with the second external connector 1101 and the IPD device 1103 (described below). In an embodiment, the redistribution structure 1001 can be formed by forming a stack of the conductive layer 1012, the conductive layer 1014, and the conductive layer 1016, and the insulating layer 1002, the insulating layer 1004, the insulating layer 1006, and the insulating layer 1008.

In an embodiment, a third insulating layer 1002 is formed over the encapsulant 901, the via 711, the first semiconductor device 801, and the interconnect structure 850. The third insulating layer 1002 can be made of one or more suitable dielectric materials, such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), a polymer material, a low-k dielectric material, another dielectric material, combinations of these materials, and the like. The third insulating layer 1002 can be formed by a process such as spin coating, lamination, CVD, or the like, or a combination thereof. The third insulating layer 1002 may have a thickness between about 5 μm and about 25 μm, such as about 7 μm, although any suitable thickness may be used. In an embodiment, the third insulating layer 1002 is thinned using a grinding or CMP process.

Suitable photolithographic masking and etching processes may be used to form openings in the third insulating layer 1002. For example, a photoresist may be formed over the third insulating layer 1002 and patterned, and one or more etching processes (e.g., wet etching processes or dry etching processes) may be utilized to remove portions of the third insulating layer 1002 to expose regions of the vias 711, regions of the first semiconductor device 801, and regions of the interconnect structure 850.

In an embodiment, the first conductive layer 1012 may be formed by first forming a seed layer (not shown) having one or more layers of titanium, copper, or titanium copper alloy by a suitable formation process (e.g., PVD, CVD, sputtering, etc.). A seed layer is formed over the third insulating layer 1002 and over the via 711, the first semiconductor device 801, and the exposed region of the interconnect structure 850. A photoresist (also not shown) may then be formed to cover the seed layer, and then patterned to expose those portions of the seed layer where first conductive layer 1012 will be subsequently formed. After the photoresist has been formed and patterned, a conductive material may be formed on the seed layer. The conductive material may be a material such as copper, titanium, tungsten, aluminum, another metal, combinations, and the like. The conductive material may be formed by a deposition process such as electroplating or electroless plating. However, while the materials and methods discussed are suitable for forming conductive materials, these materials are merely exemplary. First conductive layer 1012 may alternatively be formed using any other suitable material or any other suitable formation process (e.g., CVD or PVD). After the conductive material has been formed, the photoresist may be removed by a suitable removal process, such as ashing or chemical stripping. In addition, after removing the photoresist, those portions of the seed layer that are covered by the photoresist may be removed by, for example, a suitable wet or dry etch process that may use the conductive material as an etch mask. The seed layer and the remaining portion of the conductive material form a first conductive layer 1012.

In an embodiment, the fourth insulating layer 1004 is formed over the first conductive layer 1012 in a process similar to the process of forming the third insulating layer 1002 and using a material similar to the third insulating layer 1002. Alternatively, the fourth insulating layer 1004 may be formed in a different manner from the third insulating layer 1002. In an embodiment, the fourth insulating layer 1004 is thinned, for example, using a grinding or CMP process. After the fourth insulating layer 1004 has been formed, an opening may be formed through the fourth insulating layer 1004 by removing portions of the fourth insulating layer 1004 to expose at least a portion of the underlying first conductive layer 1012. The openings allow contact between the first conductive layer 1012 and the second conductive layer 1014 (described further below). The openings may be formed using a suitable photolithographic masking and etching process, but any suitable process may alternatively be used to expose portions of the first conductive layer 1012.

Second conductive layer 1014 can be formed to provide additional routing along with electrical connections within rerouting structure 1001. In an embodiment, the second conductive layer 1014 can be formed using similar materials and processes as the first conductive layer 1012. For example, a seed layer may be formed, a photoresist may be placed on top of the seed layer and patterned in accordance with the desired pattern of the second conductive layer 1014, a conductive material is plated into the patterned openings of the photoresist, the photoresist is removed, and the seed layer is etched.

After the second conductive layer 1014 has been formed, a fifth insulating layer 1006 can be formed over the second conductive layer 1014. In an embodiment, the fifth insulating layer 1006 similar to the third insulating layer 1002 or the fourth insulating layer 1004 may be formed of a polymer such as PBO, or may be formed of a material similar to the third insulating layer 1002 or the fourth insulating layer 1004 (e.g., polyimide or a polyimide derivative). The fifth insulating layer 1006 may be formed to have a thickness between about 2 μm and about 15 μm, such as about 5 μm.

After forming the fifth insulating layer 1006, an opening may be formed through the fifth insulating layer 1006 by removing portions of the fifth insulating layer 1006 to expose at least a portion of the underlying second conductive layer 1014. The opening allows contact between second conductive layer 1014 and third conductive layer 1016 (described further below). The openings may be formed using a suitable photolithographic masking and etching process, although any suitable process may be used to expose portions of the second conductive layer 1014.

A third conductive layer 1016 can be formed to provide additional routing along with electrical connections within the rerouting structure 1001. In an embodiment, the third conductive layer 1016 may be formed using similar materials and processes as the first conductive layer 1012 or the second conductive layer 1014. For example, a seed layer may be formed, a photoresist may be placed on top of the seed layer and patterned according to the desired pattern of the third conductive layer 1016, a conductive material plated into the patterned openings of the photoresist, the photoresist removed, and the seed layer etched.

After the third conductive layer 1016 has been formed, a sixth insulating layer 1008 can be formed over the third conductive layer 1016. In an embodiment, the sixth insulating layer 1008 similar to the third insulating layer 1002, the fourth insulating layer 1004, or the fifth insulating layer 1006 may be formed of a polymer such as PBO, or may be formed of a material similar to the third insulating layer 1002, the fourth insulating layer 1004, or the fifth insulating layer 1006 (e.g., polyimide or a polyimide derivative). The sixth insulating layer 1008 may be formed to have a thickness between about 2 μm and about 15 μm, for example, about 5 μm.

As shown in fig. 10, an opening is then formed through the sixth insulating layer 1008 by removing portions of the sixth insulating layer 1008 to expose at least a portion of the underlying third conductive layer 1016. Under Bump Metal (UBM) 1003 and connector 1005 are then formed within the opening to form an electrical connection with overlying structures and with rerouting structure 1001 through third conductive layer 1016. The openings may be formed using a suitable photolithographic masking and etching process, or any suitable process may be used.

UBM 1003 and connector 1005 may, for example, comprise three layers of conductive material, such as a layer of titanium, a layer of copper, and a layer of nickel. However, other materials and arrangements of layers suitable for forming UBM 1003 may be used, such as a chromium/chromium copper alloy/copper/gold arrangement, a titanium/titanium tungsten/copper arrangement, or a copper/nickel/gold arrangement. Any suitable material or layers of materials that may be used to form UBM 1003 and connector 100 are fully intended to be included within the scope of the present application. UBM 1003 and connector 1005 may be generated by forming each layer over rerouting structure 1001 and forming an opening in each layer. The formation of each layer may be performed using a plating process (e.g., electroplating or electroless plating), but other formation processes (e.g., sputtering, evaporation, or PECVD processes) may alternatively be used depending on the desired material. After the desired layers have been formed, portions of the layers may then be removed by suitable photolithographic masking and etching processes in the desired shape (e.g., circular, octagonal, square, or rectangular shape) to remove unwanted material and leave the UBM 1003 and connectors 1005. Any desired shape may alternatively be formed.

The connector 1005 may be formed simultaneously with the UBM 1003 or in a separate step. Other types of suitable UBMs 1003 and connectors 1005 may be formed to provide electrical connections. For example, a seed layer may be formed over the openings in the sixth insulating layer 1008 and the sixth insulating layer 1008, a photoresist placed on top of the seed layer and patterned with the desired pattern of the third conductive layer 1016, a conductive material plated into the patterned openings of the photoresist, the photoresist removed, and the seed layer etched. In an embodiment, UBM 1003 and connector 1005 may be, for example, copper posts or copper rods. All such external contacts are fully intended to be included within the scope of the embodiments.

Turning to fig. 11, a second external connector 1101 and an IPD device 1103 are formed over the UBM 1003 and the connector 1005, respectively. The second external connector 1101 may be used to provide an external connection point to electrically connect to the rewiring structure 1001 and may be, for example, a contact bump or solder ball, although any suitable connection may be utilized. In embodiments where the second external connector 1101 is a contact bump, the second external connector 1101 may comprise a material such as tin, or other suitable material such as silver, lead-free tin or copper. In embodiments where the second external connector 1101 is a solder bump, the second external connector 1101 may be formed by first forming a layer of tin to a thickness of, for example, about 100 μm by such methods as evaporation, plating, printing, solder transfer, ball placement, and the like. After the tin layer has been formed on the structure, reflow may be performed to shape the material into the desired bump shape.

As shown in fig. 11, the IPD device 1103 is mounted to the connector 1005 and thus electrically connected to the rewiring structure 1001. The IPD device 1103 can be mounted to the connector 1005 before or after the second external connector 1101 is formed. The IPD device 1103 may be connected to the connector 1005, for example, by: connectors, such as conductive bumps or pads (e.g., solder balls (not shown)) of the IPD device 1103 are sequentially dipped into flux (flux), and then a pick-and-place tool (pick-and-place tool) is used to physically align the connectors of the IPD device 1103 with the individual connectors in the connector 1005. In some cases, reflow may be performed to join the connector of the IPD device 1103 to the connector 1005. The IPD device 1103 may be a semiconductor device, or other device including one or more passive devices (e.g., capacitors, resistors, inductors, etc.). Metallization layers and the like electrically coupled to the passive devices may also be included in the IPD device 1103, depending on the particular functionality desired. In some embodiments, the IPD device 1103 may be configured to stabilize the voltage or current of the first semiconductor device 801. In some embodiments, more than one IPD device 1103 can be connected to the rerouting structure 1001.

Fig. 12 illustrates peeling the carrier substrate 701 and attaching the resulting structure to a carrier structure 1201. The carrier structure 1201 may be, for example, a metal ring intended to provide support and stabilize the structure during and after the lift-off process. In an embodiment, the structure is attached to the carrier structure 1201 using, for example, an ultraviolet tape (ultraviet tape), but any other suitable adhesive or attachment method may alternatively be used. After the structure is attached to the carrier structure 1201, the carrier substrate 701 and release layer 703 may be peeled away from the structure. According to some embodiments, peeling comprises projecting light (e.g., laser or ultraviolet light) onto the release layer 703 such that the release layer 703 decomposes under the heat of the light, and the carrier substrate 701 may be removed. In some embodiments, the fourth protective layer 705 remains on the structure after lift-off, and in other embodiments, the fourth protective layer 705 is removed from the structure after lift-off using, for example, a suitable wet or dry etch process.

Fig. 13 illustrates patterning the fourth passivation layer 705 to form an opening 1301 that exposes the via 711 and the bonding pad (e.g., bonding pad 403) of the interconnect structure 850. In some embodiments, the bonding pads of the interconnect structure 850 are covered by a DAF (e.g., the DAF501 shown in fig. 6), which is patterned in the same step as the fourth passivation layer 705 to expose the bonding pads. In an embodiment, the fourth protective layer 705 (and DAF, if present) may be patterned using, for example, a laser drilling method. In some embodiments using a laser drilling method, an optional protective layer (e.g., a photothermal conversion layer or a water-soluble protective film (hogomax) layer (not additionally shown in fig. 13)) is first deposited over the fourth protective layer 705. After protection, the laser is directed to those portions of the fourth protective layer 705 that are desired to be removed to form openings 1301. In some embodiments, the laser drilling process may use a drilling angle of about 0 ° (perpendicular to the polymer layer (fourth protective layer 705)) to about 85 ° relative to the normal to the fourth protective layer 705. In other embodiments, photolithography techniques may be used to pattern the fourth protective layer 705 (and DAF, if present). In an embodiment, the patterning can be formed to form an opening 1301 having a width between about 50 μm and about 300 μm (e.g., about 200 μm).

Fig. 14 illustrates forming a third external connector 1403 and attaching the top package 1400 to form a package structure 1450. In an embodiment, the top package 1400 may include a second substrate 1411, a second semiconductor device 1413, a third semiconductor device 1415, and an encapsulant 1417. In an embodiment, the second substrate 1411 may be, for example, a package substrate including internal interconnects (e.g., metallization layers, through-substrate vias, etc.) connecting the second and

third semiconductor devices

1413, 1415 to the interconnect structure 850 and the first semiconductor device 801 via the third external connector 1403.

In some embodiments, the second substrate 1411 may be an interposer that serves as an intermediate substrate that connects the second and

third semiconductor devices

1413, 1415 to the third external connector 1403. In this embodiment, the second substrate 1411 may be an active layer such as a doped or undoped silicon substrate, or a silicon-on-insulator (SOI) substrate. However, the second substrate 1411 may alternatively be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that may provide suitable protection and/or interconnect functionality. These and any other suitable materials may alternatively be used for the second substrate 1411.

The second semiconductor device 1413 or the third semiconductor device 1415 may each be a semiconductor device designed for the intended purpose, such as a memory die (e.g., a DRAM die), a logic die, a central processing unit die, a combination of these dies, or the like. In an embodiment, integrated circuit devices, such as transistors, capacitors, inductors, resistors, first metallization layers (not shown), and the like, are included in the second semiconductor device 1413 or the third semiconductor device 1415, depending on the particular functionality desired to be achieved. In an embodiment, the second 1413 or third 1415 semiconductor devices are designed and fabricated to operate with each other or in conjunction with or simultaneously with the first 801 semiconductor device. Although fig. 14 shows two

semiconductor devices

1413 and 1415, in other embodiments, more or fewer semiconductor devices may be connected to the second substrate 1411. In some embodiments, a third semiconductor device 1415 is mounted to the second semiconductor device 1413. In some embodiments, the second semiconductor device 1413 or the third semiconductor device 1415 may be electrically connected to the second substrate 1411 using, for example, wire bonds (not shown in fig. 14), although any suitable electrical bond may alternatively be utilized. In some embodiments, the second semiconductor device 1413 or the third semiconductor device 1415 may include external connectors (not shown in fig. 14) connected to internal interconnects of the second substrate 1411.

An encapsulant 1417 may be used to encapsulate and protect the second semiconductor device 1413, the third semiconductor device 1415, and the second substrate 1411. The encapsulant 1417 may be a molding compound, a resin such as polyimide, PPS, PEEK, PES, a heat resistant crystalline resin, another material, a combination of these, and the like.

In some embodiments, a third external connector 1403 may be formed over the opening 1301 to provide external connection to the second substrate 1411. The third external connectors 1403 may be contact bumps (e.g., micro bump or controlled collapse chip connection (C4) bumps) and may comprise a material such as tin or comprise other suitable materials such as silver or copper. In embodiments where the third external connectors 1403 are solder bumps, the third external connectors 1403 may be formed by first forming a layer of tin by any suitable method (e.g., evaporation, plating, printing, solder transfer, ball-planting, etc.) to a thickness of, for example, about 100 μm. After the tin layer has been formed on the structure, reflow is performed to shape the material into the desired bump shape. In some embodiments, a conductive pad is formed within the opening 1301 and over the interconnect feature 850 and the bond pad of the via 711. After the third external connector 1403 is formed, the third external connector 1403 is aligned with the opening 1301, and a bonding process is performed. In embodiments where the third external connectors 1403 are solder bumps, the bonding process may include a reflow process, such as a thermal process.

Fig. 14 also illustrates the formation of an underfill (underfill)1405 between the second substrate 1411 and the fourth protective layer 705 and around the third external connector 1403. In an embodiment, the underfill 1405 may be a material such as a molding compound, an epoxy, an underfill, a Molding Underfill (MUF), a resin, and the like. After underfill 1405 is formed, package structure 1450 may be peeled from carrier structure 1201. In some embodiments, package structure 1450 is also singulated from the other package structures. As such, individual package structures 1450 may be formed, although other techniques or processes may be used and are considered to be within the scope of the present invention. In some embodiments, package structure 1450 may be an integrated fan-out package-on-package structure.

In some embodiments, the use of one or more interconnect structures 850 may improve the electrical performance of the package structure 1450. For example, power may be supplied to the second semiconductor device 1413 or the third semiconductor device 1415 through TSVs (e.g., the TSV 201) of the interconnect structure 850. For example, a first group of TSVs of the interconnect structure 850 may supply a first voltage or a first current, and a second group of TSVs of the interconnect structure may supply a second voltage or a second current. In some cases, the supply voltage may be a ground voltage or a common voltage. In some embodiments where the IPD (e.g., IPD 103) of the interconnect structure 850 comprises a capacitor (e.g., a deep trench capacitor), the capacitor may be connected between the first group of TSVs and the second group of TSVs. Connected in this manner, the capacitors of the interconnect structure 850 are able to decouple the first voltage or first current from the second voltage or second current. As such, the interconnect structure 850 may reduce noise, fluctuation, or transients and stabilize the power supplied to the appropriate semiconductor device (e.g., 1413 or 1415) of the top package 1400. In some embodiments, the interconnect structure 850 may be configured to stabilize the power of the semiconductor device of the top package 1400, and the IPD device 1103 may be configured to stabilize the power of the first semiconductor device 801. In some cases, orienting interconnect structure 850 such that the IPD is closer to semiconductor device 1413 and semiconductor device 1415 may improve the electrical performance of package structure 1450 more than orienting the IPD farther from semiconductor device 1413 and semiconductor device 1415. In some embodiments, each semiconductor device of the top package 1400 may have an associated interconnect structure 850 configured for that device.

Fig. 15 to 19C illustrate an embodiment of a package structure including an interconnect structure having an IPD. Package structure 1450, package structure 1452, package structure 1454, package structure 1456, package structure 1458, package structure 1460, and package structure 1462 shown in fig. 14 through 19C are illustrative examples and are not intended to be limiting. For example, the different features of the embodiments shown in fig. 14-19C may be combined in a single interconnect structure within a single package structure, or may be present in different interconnect structures in different combinations.

Fig. 15 illustrates a package structure 1452 including an interconnect structure 850 according to an embodiment. The package structure 1452 is similar to the package structure 1450 described above with reference to fig. 14, but the fourth protective layer 705 (see fig. 12) is removed in the package structure 1452 before attaching the top package 1400. For example, in the processes shown in fig. 7-14, the fourth protective layer 705 may be removed when peeling the carrier substrate 701, as described in fig. 12. In some embodiments, the fourth protection layer 705 may be removed after the carrier substrate 701 has been stripped, for example, using a wet etch process or a dry etch process. In some embodiments, after removing the fourth passivation layer 705, the bonding pads (e.g., the bonding pads 403) and the vias 711 of the interconnect structure 850 may be exposed. In some embodiments, the bond pads of the interconnect structure 850 are covered by a DAF (e.g., DAF 501), and openings may be formed in the DAF to expose the bond pads, which may be formed in a manner similar to that described above with respect to opening 1301 shown in fig. 13. The removal of the fourth protective layer 705 may be combined with the other embodiments shown in fig. 16 to 19C or with other embodiments not shown. In some cases, removing the fourth protective layer 705 may reduce the overall thickness of the resulting package structure.

Fig. 16A-16B illustrate an interconnect structure 852 and a package structure 1454 including the interconnect structure 852, according to an embodiment. The package structure 1454 is similar to the package structure 1452 described above with reference to fig. 15. For example, the fourth protection layer 705 (see fig. 12) is removed before the top package 1400 is attached. The interconnect structure 852 is similar to the interconnect structure 650 described with reference to fig. 6, except that the interconnect structure 852 does not include the third protective layer 605 (see fig. 6). A re-wiring structure 1001 (see fig. 10) is formed over the second protective layer 601 and the metal contact 603, and is electrically connected to the metal contact 603. In some cases, omitting the third protective layer 605 may reduce the cost or time to form the interconnect structure 852 or the package structure 1454.

Fig. 17 illustrates a package structure 1456 including an interconnect structure 850 according to an embodiment. The package structure 1456 is similar to the package structure 1452 described above with reference to fig. 15, but in the package structure 1456, the rewiring structure 1700 is provided between the third external connector 1403 and the interconnect structure 850, the via 711 and the first semiconductor device 801. In some embodiments, the re-routing structure 1700 is formed over the fourth protection layer 705 before forming the via mask 709 and the via 711 described above with reference to fig. 7. The rewiring structure 1700 may be formed in a similar manner as the formation of the rewiring structure 1001 (e.g., including multiple insulating layers and multiple conductive layers, as described with reference to fig. 10), or in a different manner. The rerouting structure 1700 may also include more rerouting layers than shown in fig. 17. In some embodiments, an opening is formed through the rewiring structure 1700, and the third external connector 1403 is connected to the interconnect structure 850 or the via 711 through the opening. For example, fig. 17 shows a third external connector 1403 connected to an interconnect structure 850 by a rewiring structure 1700. The openings in the redistribution structure 1700 may be formed by, for example, laser drilling or photolithography. In some embodiments, laser drilling may expose a portion of the redistribution layer in the opening such that an electrical connection is formed between a third external connector 1403 formed within the opening and the redistribution layer.

In some embodiments, the third external connector 1403 connects to a conductive feature (e.g., a rerouting layer) within the rerouting structure 1700. For example, fig. 17 shows a via 711 and a third external connector 1403 connected to a conductive feature within the rerouting structure 1700. The formation of the re-wiring structure 1700 may be combined with other embodiments shown in fig. 14 to 16B or fig. 18A to 19C or with other embodiments not shown.

Fig. 18A-18B illustrate an interconnect structure 854 and a package structure 1458 including the interconnect structure 854, in accordance with an embodiment. The package structure 1458 is similar to the package structure 1450 described above with reference to fig. 14. Interconnect structure 854 is similar to interconnect structure 850 described with reference to fig. 14, but interconnect structure 854 is configured to be oriented such that the IPD (e.g., IPD 103) faces rerouting structure 1001. As such, the third external connector 1403 may be connected to the metal contact 603 of the interconnect structure 854. In some embodiments, the interconnect structure 854 includes a top protective layer 1805 disposed over the metal contact 603 and a bottom protective layer 1801 disposed over the bond pad 403. The top protective layer 1805 or the bottom protective layer 1801 may be similar to the DAF501 previously described with reference to fig. 5 or similar to the third protective layer 605 previously described with reference to fig. 6. In some embodiments, the bottom protective layer 1801 may be omitted, similar to the interconnect structure 852 described with reference to fig. 16A. In some embodiments, the fourth protective layer 705 may be omitted, similar to the package structure 1452 described above with reference to fig. 15. The different orientations of the interconnect structure 852 may be combined with other embodiments shown in fig. 14-17 or 19A-19C or with other embodiments not shown.

According to some embodiments, fig. 19A illustrates interconnect structure 856, fig. 19B illustrates package structure 1460 including interconnect structure 856 and interconnect structure 850, and fig. 19C illustrates package structure 1462 including a plurality of interconnect structures 856. The package structure 1460 shown in fig. 19B is similar to the package structure 1450 described above with reference to fig. 14, but the package structure 1460 includes more than one type of interconnect structure. The package structure 1462 shown in fig. 19C is similar to the package structure 1460 of fig. 19B, but all interconnect structures within the package structure 1462 are interconnect structures 856. Interconnect structure 856 is similar to interconnect structure 650 described with reference to fig. 6, except that interconnect structure 856 does not include TSV201 and associated features (e.g., metal contacts 603, etc.). As such, the semiconductor device of the top package may be connected to the IPD103 of the interconnect structure 856 through the third external connector 1403. In some embodiments, the fourth protective layer 705 may be omitted, similar to the package structure 1452 described above with reference to fig. 15. The interconnect structure without the TSV or the package structure with a different type of interconnect structure may be combined with other embodiments shown in fig. 14 to 18B or with other embodiments not shown.

The interconnect structures described herein may achieve a number of advantages. For example, the interconnect structure may include TSVs that conduct externally provided power to other semiconductor devices (e.g., memory devices) within the package. By including an IPD (e.g., capacitor or other device) connected to TSVs within the interconnect structure, the IPD may stabilize or reduce noise of voltages or currents conducted by the TSVs to the semiconductor device. Additionally, the interconnect structures described herein may reduce the equivalent series resistance or equivalent series inductance between the IPD and the associated semiconductor device. Device performance may be improved or more reliable, for example, in lower supply voltage applications, higher bandwidth applications, or other applications, since power is more stable. In some cases, positioning the IPD closer to the associated semiconductor device may improve the stabilization achieved by the IPD. Thus, disposing the interconnect structure within the molding compound (e.g., encapsulant 901) or near the via (e.g., via 711) may further improve device performance. Additionally, including the IPD within a package as described above may reduce the size of the package. In this way, the distribution network of the package can be improved.

According to an embodiment, a semiconductor device includes: a rewiring structure; a first semiconductor device located on the rewiring structure; a top package over the first semiconductor device, the top package including a second semiconductor device; a molding compound between the redistribution structure and the top package; a first set of vias between the top package and the rewiring structure and electrically connecting the top package to the rewiring structure; and a first interconnect structure disposed within the molding compound and electrically connecting the top package to the rewiring structure, the first interconnect structure including a substrate and a passive device formed in the substrate, wherein the first interconnect structure does not include an active device. In an embodiment, the passive device comprises a trench capacitor. In an embodiment, the first interconnect structure further comprises: a first via extending through the substrate, the first via electrically connected to the second semiconductor device; and a second via extending through the substrate, the second via electrically connected to the second semiconductor device, wherein a first electrode of the passive device is electrically connected to the first via and a second electrode of the passive device is electrically connected to the second via. In an embodiment, the first interconnect structure further includes a conductive trace, and the conductive trace electrically connects the passive device with a third via extending through the substrate. In an embodiment, the device further includes a polymer layer extending over the first interconnect structure, the first set of vias, and the first semiconductor device. In an embodiment, the first interconnect structure further includes a polymer layer disposed over the passive devices, the first vias, and the second vias. In an embodiment, the device further includes a second interconnect structure between the top package and the redistribution structure, the second interconnect structure separated from the first semiconductor device, from the first interconnect structure, and from the first set of vias by the molding compound. In an embodiment, at least one via of the first set of vias is laterally disposed between the first interconnect structure and the first semiconductor device.

According to an embodiment, a semiconductor device includes: a rewiring structure; a package including a first semiconductor device and a second semiconductor device disposed on a package substrate, the package disposed over the redistribution structure; a third semiconductor device disposed between the rewiring structure and the package substrate and electrically connected to the rewiring structure; a via extending between the rerouting structure and the package substrate, the via electrically connecting the rerouting structure to the package substrate; a first passive device structure disposed between the package substrate and the rewiring structure, the first passive device structure comprising: a first substrate; a first passive device disposed on the first substrate; a first via extending through the first substrate and electrically connected to the first passive device; and a second via extending through the first substrate, wherein the first via and the second via are electrically connected to the rerouting structure and to the first semiconductor device. The device further comprises: a second passive device structure disposed between the package substrate and the rerouting structure, the second passive device structure comprising: a second substrate; a second passive device disposed on the second substrate; a third via extending through the second substrate and electrically connected to the second passive device; and a fourth via extending through the second substrate, wherein the third via and the fourth via are electrically connected to the rerouting structure and to the second semiconductor device; and a molding compound surrounding each of the first passive device structure, the second passive device structure, the via, and the third semiconductor device. In an embodiment, the first via and the second via are connected to a same terminal of the first passive device. In an embodiment, the first via is configured to transmit a supply voltage to the first semiconductor device, and the second via is configured to transmit an electrical signal to the first semiconductor device. In an embodiment, the first passive device of the first passive device structure is a capacitor. In an embodiment, the device further includes an integrated passive device coupled to the rewiring structure opposite the package substrate. In an embodiment, the apparatus further comprises at least one redistribution layer disposed between the via and the package substrate.

According to an embodiment, a method of manufacturing a semiconductor device includes: forming a set of vias in a carrier substrate; placing a first die on the carrier substrate, the first die being spaced apart from the set of vias; and placing a first interconnect structure on the carrier substrate, the first interconnect structure being spaced apart from the first die and the set of vias. The first interconnect structure includes: a substrate; a first conductive element and a second conductive element extending from a first side of the substrate to a second side of the substrate; a metallization layer disposed over and electrically connected to the first and second conductive elements; and an integrated passive device, wherein the integrated passive device is electrically connected to the first conductive element and the second conductive element through the metallization layer. The method further comprises the following steps: encapsulating the set of vias, the first die, and the first interconnect structure in an encapsulant, wherein the encapsulant is in physical contact with the set of vias, the first die, and the first interconnect structure; and placing a top package over the set of vias, the first die, and over the first side of the first interconnect structure, wherein the top package includes a second die, and wherein placing the top package includes electrically connecting the second die to the integrated passive device. In an embodiment, the method further comprises: forming a redistribution structure over the set of vias, the first die, and over a second side of the first interconnect structure, the second side of the first interconnect structure being opposite the first side of the first interconnect structure. In an embodiment, the method further comprises: forming a dielectric layer over the set of vias, the first die, and over the first side of the first interconnect structure; forming an opening in the dielectric layer; and forming a conductive material within the opening, the conductive material contacting the set of vias and the metallization layer of the first interconnect structure. In an embodiment, forming the opening in the dielectric layer comprises using a laser drilling process. In an embodiment, the method further comprises placing a second interconnect structure on the carrier substrate. In an embodiment, the integrated passive device is a trench capacitor.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

a rewiring structure;

a first semiconductor device located on the rewiring structure;

a top package over the first semiconductor device, the top package including a second semiconductor device;

a molding compound between the redistribution structure and the top package;

a first set of vias between the top package and the rewiring structure and electrically connecting the top package to the rewiring structure; and

a first interconnect structure disposed within the molding compound and electrically connecting the top package to the rewiring structure, the first interconnect structure including a substrate and a passive device formed in the substrate, wherein the first interconnect structure does not include an active device.