CN110620569B

CN110620569B - Trigger circuit

Info

Publication number: CN110620569B
Application number: CN201810630956.8A
Authority: CN
Inventors: 徐薪承; 曹太和; 林柏青
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2018-06-19
Filing date: 2018-06-19
Publication date: 2023-09-08
Anticipated expiration: 2038-06-19
Also published as: CN110620569A

Abstract

A flip-flop circuit includes an input terminal, an output terminal, a control circuit and a logic circuit. The control circuit is coupled to the input terminal and the output terminal. The control circuit receives an input voltage from the input end and receives an output voltage from the output end, and the control circuit generates a plurality of reference voltages according to at least the input voltage and the output voltage. The logic circuit is coupled to the control circuit and the output terminal. When the input voltage is converted from a first voltage value to a second voltage value, the control circuit controls the logic circuit through the plurality of reference voltages to convert the output voltage from the second voltage value to the first voltage value.

Description

Trigger circuit

Technical Field

The present invention relates to electronic circuits, and more particularly to a flip-flop circuit with protection.

Background

With the rapid development of Complementary Metal Oxide Semiconductor (CMOS) technology, the size of transistors is continually reduced to reduce the chip area, thereby increasing the operating speed and saving power consumption. However, as transistor dimensions continue to shrink, so does the gate oxide and transistor channel, so does the maximum allowable cross-voltage across any of the transistor electrodes (gate, drain, source and base). If the voltage difference between any two ends of a transistor is greater than the rated voltage (nominal voltage), the transistor will be damaged. At present, the rated voltage of an advanced CMOS process is lower and lower, so that a conventional CMOS Schmitt trigger (Schmitt trigger) circuit faces the problem that a transistor is damaged due to the fact that the power supply voltage is higher than the rated voltage.

Disclosure of Invention

It is therefore an object of the present invention to provide a flip-flop circuit that solves the above-mentioned problems.

According to one embodiment of the present invention, a flip-flop circuit is disclosed, comprising an input terminal, an output terminal, a control circuit and a logic circuit. The control circuit is coupled to the input terminal and the output terminal. The control circuit receives an input voltage from the input end and receives an output voltage from the output end, and the control circuit generates a plurality of reference voltages according to at least the input voltage and the output voltage. The logic circuit is coupled to the control circuit and the output terminal. When the input voltage is converted from a first voltage value to a second voltage value, the control circuit controls the logic circuit through the plurality of reference voltages to convert the output voltage from the second voltage value to the first voltage value.

Drawings

FIG. 1 is a schematic diagram of a flip-flop circuit according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a logic circuit according to an embodiment of the invention.

Fig. 3 is a schematic diagram illustrating the operation of a logic circuit according to a first embodiment of the present invention.

Fig. 4 is a schematic diagram illustrating the operation of a logic circuit according to a second embodiment of the present invention.

Fig. 5 is a schematic diagram of a control circuit according to an embodiment of the invention.

Fig. 6 is a schematic diagram of a comparison circuit in a control circuit according to an embodiment of the invention.

Detailed Description

Certain terms are used throughout the description and following claims to refer to particular components. It will be appreciated by those of ordinary skill in the art that a hardware manufacturer may refer to a component by different names. The present specification and the following claims do not take the form of an element differentiated by a name, but rather by a functional difference. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Furthermore, the term "coupled" as used herein includes any direct or indirect electrical connection, and thus, if a first device couples to a second device, that connection may be made directly to the second device, or indirectly to the second device via other devices or connections.

FIG. 1 is a schematic diagram of a flip-flop circuit 10 according to an embodiment of the present invention, wherein the flip-flop circuit 10 includes an input terminal IN, an output terminal OUT, a control circuit 110 and a logic circuit 120, as shown IN FIG. 1, wherein the control circuit 110 receives an input voltage V from the input terminal IN _in And from the output endOUT receives output voltage V _out And according to the input voltage V _in And output voltage V _out Reference voltage VSS, VDD, VDD x 2 … VDD x n is generated, wherein reference voltage VSS may be a ground voltage, in other words, reference voltage VSS may be the lowest voltage point in flip-flop circuit 10, and reference voltage VDD is the highest voltage that can be used in the semiconductor process used to manufacture flip-flop circuit 10, which is also referred to as a nominal voltage. n may be a positive integer greater than 2, and the value of n may actually depend on the application, i.e., the invention is not limited to the value of n, and the reference voltage vdd×n represents a reference voltage n times the reference voltage VDD, and the reference voltage vdd×n may be a reference voltage output to the logic circuit 120 through the control circuit 110 via an external input.

IN the present invention, when the input voltage V at the input terminal IN _in When the reference voltage VSS is converted to the reference voltage VDD, the flip-flop circuit 10 makes the output voltage V at the output terminal OUT through the control circuit 110 and the logic circuit 120 _out Converting from the reference voltage VDD to the reference voltage VSS; similarly, when the input voltage V at the input IN _in When converting from the reference voltage VDD to the reference voltage VSS, the flip-flop circuit 10 makes the output voltage V on the output terminal OUT through the control circuit 110 and the logic circuit 120 _out The reference voltage VSS is converted into the reference voltage vdd×n, and the detailed conversion process will be described in the following paragraphs.

Fig. 2 is a schematic diagram of a logic circuit 120 according to an embodiment of the present invention, as shown in fig. 2, the logic circuit 120 is formed by stacking P-type metal oxide semiconductor field effect transistors (abbreviated as transistors in the following paragraphs) MP1, MP2 … MPn and MP (n+1) and N-type transistors MN1, MN2 … MNn and MN (n+1), where N is the same as the reference voltage VDD x N in fig. 1 and represents a positive integer, such as 3, 4, 5, etc. The P-type transistor and the N-type transistor in the logic circuit 120 respectively receive the reference voltage from the control circuit 110 through the gate terminal to control the switching state of the transistors, and a source terminal of the transistor MP (n+1) is coupled to the reference voltage VDD x N and a source terminal of the transistor MN (n+1) is coupled to the reference voltage VSS, wherein the reference voltage VDD xThe n and the reference voltage VSS may be generated directly from external inputs or through the control circuit 110. In addition, the control circuit 110 transmits the reference voltage to a source terminal of the transistor MPn and a source terminal of the transistor MNN according to the output voltage V _out The voltage value of (a) determines the reference voltage value received by the source terminal of the transistor MPn and the source terminal of the transistor MNN, thereby controlling the switching states of the transistor MPn and the transistor MNN and thus completing the output voltage V _out Is a transition of (2).

Fig. 3 is a schematic diagram illustrating an operation of the logic circuit 120 according to a first embodiment of the present invention, in which N is 2, in other words, the logic circuit 120 includes P-type transistors MP1, MP2 and MP3 and N-type transistors MN1, MN2 and MN3, and are stacked with each other as shown in fig. 3. Description of the embodiment when the input voltage V _in The logic circuit 120 operates when the reference voltage VSS is converted to vdd×2. In an initial state (1 st step marked by the numeral 1 in FIG. 3), when the voltage V is inputted _in When the reference voltage is VSS, the output voltage V _out The reference voltages VDD 2 of the previous transition state are received from the control circuit 110 at the gate terminals of the P-type transistors MP1-MP3, and the reference voltages VDD 2, VDD and VSS are received from the control circuit 110 at the gate terminals of the N-type transistors MN1-MN3, respectively; then, input voltage V _in Starting from the reference voltage VSS, the control circuit 110 transmits the reference voltage VDD to the gate terminals of the N-type transistors MN1-MN3 (step 2 is labeled with numeral 2 in FIG. 3), and those skilled in the art will readily understand that when the input voltage of the flip-flop circuit increases from a low voltage to a high voltage, the output voltage must be shifted after the threshold voltage is raised too high, and thus the input voltage V _in When the reference voltage VSS starts to increase but the threshold voltage is not reached, the control circuit 110 additionally transmits the reference voltage VDD to the source terminal of the N-type transistor MN2 (labeled as step 3 in fig. 3), so that both the gate terminal and the source terminal of the N-type transistor MN2 receive the reference voltage VDD and turn off. Then, when the voltage V is input _in After exceeding the high threshold voltage, the control circuit 110 stops transmitting the reference voltage VDD to the source terminal of the N-type transistor MN2, and the N-type transistor MN2 is turned on, and at this time, the N-type transistor MN1-MN3 is turned on and transmits the reference voltage VSS to the output terminal OUT, so that the output voltage V _out From reference voltage VDD x 2 to reference voltage VSS (labeled step 4 in fig. 3 by numeral 4). Next, the control circuit 110 starts with the reference voltage VSS and respectively transmits the reference voltages to the P-type transistors MP1-MP3 at intervals of the reference voltage VDD, in detail, the gate of the P-type transistor MP1 receives the reference voltage VSS, the gate of the P-type transistor MP2 receives the reference voltage VDD, and the gate of the P-type transistor MP3 receives the reference voltage vdd×2, such that the gate voltage presents an arithmetic sequence { VSS, VDD, VDD ×2}, and the P-type transistor MP3 presents a turned-off state because the gate voltage thereof is vdd×2, and the rest of the P-type transistors generate a step-down function because the gate voltage is a step-down voltage at intervals of VDD. Thus, the output voltage V _out The voltage at any terminal of any transistor in logic circuit 120 will not exceed the nominal voltage, thereby greatly reducing the possibility of transistor damage.

Fig. 4 is a schematic diagram illustrating the operation of the logic circuit 120 according to a second embodiment of the present invention, and in this embodiment, N is 2, in other words, the logic circuit 120 includes P-type transistors MP1, MP2 and MP3 and N-type transistors MN1, MN2 and MN3, and are stacked on each other as shown in fig. 4. Description of the embodiment when the input voltage V _in The logic circuit 120 operates when switching from the reference voltage VDD x 2 to VSS. In an initial state (1 st step marked by the numeral 1 in FIG. 4), when the voltage V is inputted _in When the reference voltage is VDD 2, the output voltage V _out The reference voltage VSS of the previous transition state is supposed, at this time, the gate terminals of the N-type transistors MN1-MN3 all receive the reference voltage VDD from the control circuit 110, and the gate terminals of the P-type transistors MP1-MP3 respectively receive the reference voltages VSS, VDD and VDD x 2 from the control circuit 110; then, input voltage V _in From the reference voltage VDD by 2, the control circuit 110 transmits the reference voltage VDD to the gate terminals (labeled 2 nd step in fig. 4) of the P-type transistors MP1-MP3, and the input voltage of the flip-flop circuit is changed from high to low as described in the embodiment of fig. 3, and the output voltage is changed after the threshold voltage is lowered, so that the input voltage V _in When the reference voltage VDD starts to decrease but the threshold voltage is not reached, the control circuit 110 additionally transmits the reference voltage VDD to the source terminal of the P-type transistor MP2 (labeled 3 rd step in fig. 4), such that both the gate terminal and the source terminal of the P-type transistor MP2 receive the reference voltage VDD and turn off. Then, when the voltage V is input _in After the threshold voltage is low, the control circuit 110 stops transmitting the reference voltage VDD to the source terminal of the P-type transistor MP2, and the P-type transistor MP2 is turned on, and at this time, the P-type transistors MP1-MP3 are turned on and transmit the reference voltage vdd×2 to the output terminal OUT, so that the output voltage V _out From reference voltage VSS to reference voltage VDD x 2 (labeled step 4 in fig. 4 by numeral 4). Next, the control circuit 110 starts with the reference voltage vdd×2 and respectively transmits the reference voltages to the N-type transistors MN1-MN3 at intervals of the reference voltage VDD, specifically, the gate of the N-type transistor MN1 receives the reference voltage vdd×2, the gate of the N-type transistor MN2 receives the reference voltage VDD, and the gate of the N-type transistor MN3 receives the reference voltage VSS, so that the gate voltage presents an arithmetic sequence { VSS, VDD, VDD ×2}, and the N-type transistor MN3 presents a turned-off state because the gate voltage is VSS, and the rest of the N-type transistors generate a step-down function because the gate voltage is a step-down voltage at intervals of VDD. Thus, the output voltage V _out The voltage at any terminal of any transistor in the logic circuit 120 will not exceed the rated voltage, which greatly reduces the possibility of transistor damage.

It should be noted that in the embodiments of fig. 3 and fig. 4, n=2 is taken as an example, but this is not a limitation of the present invention, when the reference voltage vdd×n is greater due to the higher value of n (e.g. n=3, 4, 5 …), the number of transistors stacked in the logic circuit 120 is also increased, so that the voltage at any terminal of any transistor in the logic circuit 120 will not exceed the rated voltage, thereby protecting the circuit. In addition, the present invention is not limited to the implementation of the control circuit 110, in some embodiments, the control circuit 110 may be implemented in hardware, for example, the control circuit 110 may be a processor, however, in other embodiments, the control circuit 110 may be implemented in software, firmware, etc., so long as the control circuit 110 can generate the reference voltages VSS, VDD … VDD (n-1), VDD n to the logic circuit 120, which fall within the scope of the present invention.

Fig. 5 is a schematic diagram of the control circuit 110 according to an embodiment of the invention, as shown in fig. 5, the control circuit 110 includes comparison circuits 510, 520, 530 and 540 and switch circuits 550 and 560, in fig. 5, the switch circuits 550 and 560 and the comparison circuits 510, 520, 530 and 540 are separated for simplicity and convenience of reading and understanding, but in this embodiment, the switch circuits 550 and 560 and the comparison circuits 510, 520, 530 and 540 are all implemented in the same circuit. In the present embodiment, the switch circuits 550 and 560 are implemented by a P-type transistor SW1 and an N-type transistor SW2, respectively. However, in other embodiments, the comparing circuits 510, 520, 530, and 540 and the switching circuits 550 and 560 may be implemented independently, and are not limited to be implemented in the same circuit. In detail, the comparison circuit 510 is used for comparing the input voltage V _in And a reference voltage VDD, and outputs the higher of the two to the gate terminal of the P-type transistor MP 3; the comparison circuit 520 is used for comparing the output voltage V _out And a reference voltage VDD, and outputs the lower of the two to the gate terminal of the P-type transistor MP 1; the comparator 530 is used for comparing the output voltage V _out And a reference voltage VDD, and outputs the higher of the two to the gate terminal of the N-type transistor MN 1; the comparison circuit 540 is used for comparing the input voltage V _in And a reference voltage VDD, and outputs the lower of the two to the gate terminal of the N-type transistor MN 3; the control circuit 110 couples the reference voltage VDD to the gate terminals of the P-type transistor MP2 and the N-type transistor MN 2. In addition, the switching circuits 550 and 560 are based on the output voltage V _out To determine whether to turn on the transistors SW1 and SW2, and if so, to transmit the reference voltage VDD to the source terminals of the P-type transistor MP2 and the N-type transistor MN2, respectively.

Referring to both fig. 3 and fig. 5, the input voltage V is at the initial state _in For reference voltage VSS, output voltage V _out VDD x 2, the gates of P-type transistors MP1-MP3 each receive the reference voltage VDD from the control circuit 110, according to the characteristics of the comparison circuits 510-520, and according to the characteristics of the comparison circuits 530-540,the gate terminals of the N-type transistors MN1-MN3 respectively receive the reference voltages VDD 2, VDD and VSS from the control circuit 110. In addition, the switching circuit 560 outputs the voltage V _out Turned on for vdd×2 to transmit the reference voltage VDD to the source terminal of the N-type transistor MN2, and turned off because the gate terminal and the source terminal of the N-type transistor MN2 are both the reference voltage VDD. With input voltage V _in After the reference voltage VSS rises to the reference voltage vdd×2, the gate terminals of the P-type transistors MP2-MP3 respectively receive the reference voltages VDD and vdd×2 from the control circuit 110, and the N-type transistor MN3 receives the reference voltage VDD from the control circuit 110. And at this time output voltage V _out Gradually decreasing, eventually causing the switch circuit 560 to turn off, and the N-type transistors MN1-MN3 are all turned on, thereby outputting the voltage V _out The conversion is performed to the reference voltage VSS, and the gate terminals of the N-type transistors MN1 and MN2 receive the reference voltage VDD and the gate terminal of the P-type transistor MP1 receives the reference voltage VSS, thereby realizing the embodiment of fig. 3.

Referring to both fig. 4 and fig. 5, the input voltage V is at the initial state _in For reference voltage VDD 2, output voltage V _out The gate terminals of the P-type transistors MP1-MP3 respectively receive the reference voltages VSS, VDD and VDD 2 from the control circuit 110 according to the characteristics of the comparison circuits 510-520, and the gate terminals of the N-type transistors MN1-MN3 respectively receive the reference voltage VDD from the control circuit 110 according to the characteristics of the comparison circuits 530-540. In addition, the switching circuit 550 outputs the voltage V _out Turned on for VSS to transmit the reference voltage VDD to the source terminal of the P-type transistor MP2, since both the gate terminal and the source terminal of the P-type transistor MP2 are turned off for the reference voltage VDD. With input voltage V _in After the reference voltage vdd×2 drops to the reference voltage VSS, the gate terminals of the P-type transistors MP2-MP3 all receive the reference voltage VDD from the control circuit 110 and the N-type transistor MN3 receives the reference voltage VSS from the control circuit 110. And at this time output voltage V _out Gradually rising, eventually causing the switch circuit 550 to turn off, and the P-type transistors MP1-MP3 are all turned on, thereby outputting the voltage V _out Is converted to the reference voltage VDD 2 to complete the conversion, and the gate terminals of the N-type transistors MN1 and MN2 receive the reference voltages VDD 2 and VDD respectively and the gate terminal of the P-type transistor MP1The reference voltage VDD is received, thereby implementing the embodiment of fig. 4.

FIG. 6 is a schematic diagram of the comparison circuits 510-540 in the control circuit 110 according to an embodiment of the invention, as shown in FIG. 6, the comparison circuits 510-540 are each implemented by two transistors, in detail, the comparison circuit 510 includes P-type transistors MPX and MPY, wherein the gate of the P-type transistor MPX is coupled to the reference voltage VDD, and the gate of the P-type transistor MPY is coupled to the input voltage V _in The source terminals of the P-type transistors MPX and MPY are coupled to the gate terminal of the P-type transistor MP3, thereby outputting the input voltage V _in The higher voltage of the reference voltage VDD is connected to the gate terminal of the P-type transistor MP 3; the comparison circuit 520 includes N-type transistors MNX and MNY, wherein the gate of the N-type transistor MNX is coupled to the reference voltage VDD, and the gate of the N-type transistor MNY is coupled to the output voltage V _out The source terminals of the N-type transistors MPX and MPY are coupled to the gate terminal of the P-type transistor MP1 to output an output voltage V _out The lower voltage of the reference voltage VDD is connected to the gate terminal of the P-type transistor MP 1; the comparison circuit 530 includes P-type transistors MPI and MPJ, wherein the gate of the P-type transistor MPI is coupled to the reference voltage VDD, and the gate of the P-type transistor MPJ is coupled to the output voltage V _out The source terminals of the P-type transistors MPI and MPJ are coupled to the gate terminal of the N-type transistor MN1, thereby outputting an output voltage V _out The higher voltage of the reference voltage VDD is applied to the gate terminal of the N-type transistor MN 1; the comparison circuit 540 includes N-type transistors MNI and MNJ, wherein the gate of the N-type transistor MNI is coupled to the reference voltage VDD, and the gate of the N-type transistor MNJ is coupled to the input voltage V _in The source terminals of the N-type transistors MNI and MNJ are coupled to the gate terminal of the N-type transistor MN3 to output and input the voltage V _in The lower voltage of the reference voltage VDD is applied to the gate terminal of the N-type transistor MN 3.

In summary, the control circuit 110 transmits different reference voltages to the transistors stacked in the logic circuit 120, so that the two ends of any transistor in the logic circuit 120 will not exceed the rated voltage after the conversion is completed, and the risk of transistor damage can be greatly reduced.

The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Symbol description

10. Trigger circuit

110. Control circuit

120. Logic circuit

IN input terminal

OUT output terminal

V _in Input voltage

V _out Output voltage

VSS, VDD, VDD x 2 … VDD x n reference voltage

MP1-MP3, MPn, MP (n+1), MPX, MPY, MPI, MPJ, SW 1P type transistor

MN1-MN3, MNN, MN (n+1), MNX, MNY, MNI, MNJ, SW 2N type transistor

510-540 comparison circuit

550-560 switching circuit

Claims

1. A flip-flop circuit, comprising:

an input end and an output end;

the control circuit is coupled to the input end and the output end, receives an input voltage from the input end and receives an output voltage from the output end, and generates a plurality of reference voltages according to at least the input voltage and the output voltage;

a logic circuit coupled to the control circuit and the output terminal, wherein when the input voltage is converted from a first voltage value to a second voltage value, the control circuit controls the logic circuit through the plurality of reference voltages to convert the output voltage from the second voltage value to the first voltage value,

wherein the voltage values of the plurality of reference voltages are in an equal-difference series, the first voltage value is one of a maximum voltage and a minimum voltage of the plurality of reference voltages, the second voltage value is the other of the maximum voltage and the minimum voltage of the plurality of reference voltages,

the logic circuit is formed by overlapping n+1P-type metal oxide semiconductor field effect transistors and n+1N-type metal oxide semiconductor field effect transistors, wherein the number of n+1 is equal to the number of the plurality of reference voltages and N is a positive integer.

2. The flip-flop circuit of claim 1, wherein when a change in said input voltage is less than a predetermined threshold, said control circuit transmits a specific reference voltage to a gate terminal and a source terminal of an N-th pmos fet of said n+1th pmos fet or to a gate terminal and a source terminal of an N-th nmos fet of said n+1th nmos fet, wherein said N-th pmos fet is adjacent to and connected to said n+1th pmos fet, wherein a source terminal of said n+1th pmos fet is connected to a highest voltage, and wherein said specific reference voltage is received by said source terminal of said n+1th pmos fet.

3. The flip-flop circuit of claim 2, wherein said control circuit stops transmitting said specific reference voltage to said source terminal of said N-th pmos or N-th nmos when said change in said input voltage is greater than or equal to said predetermined threshold.

4. The flip-flop circuit of claim 1, wherein the control circuit comprises:

and a comparator for comparing the input voltage with a specific reference voltage and outputting the higher of the input voltage and the specific reference voltage as one of the plurality of reference voltages, wherein the specific reference voltage is the rated voltage of the trigger circuit.

5. The flip-flop circuit of claim 1, wherein the control circuit comprises:

and a comparator for comparing the output voltage with a specific reference voltage, and outputting the higher of the output voltage and the specific reference voltage as one of the plurality of reference voltages, wherein the specific reference voltage is the rated voltage of the trigger circuit.

6. The flip-flop circuit of claim 1, wherein the control circuit comprises:

and a comparator for comparing the input voltage with a specific reference voltage and outputting the lower of the input voltage and the specific reference voltage as one of the plurality of reference voltages, wherein the specific reference voltage is the rated voltage of the trigger circuit.

7. The flip-flop circuit of claim 1, wherein the control circuit comprises:

and a comparator for comparing the output voltage with a specific reference voltage, and outputting the lower of the output voltage and the specific reference voltage as one of the plurality of reference voltages, wherein the specific reference voltage is the rated voltage of the trigger circuit.

8. The flip-flop circuit of claim 1, wherein the control circuit comprises:

the switching circuit is used for judging whether a specific reference voltage is output to a source terminal of an N-th P-type metal oxide semiconductor field effect transistor in the n+1th P-type metal oxide semiconductor field effect transistor or an N-th N-type metal oxide semiconductor field effect transistor in the n+1th N-type metal oxide semiconductor field effect transistor according to the output voltage, wherein the N-th P-type metal oxide semiconductor field effect transistor is adjacent to and connected with the n+1th P-type metal oxide semiconductor field effect transistor, the source terminal of the n+1th P-type metal oxide semiconductor field effect transistor receives the highest voltage, the N-th N-type metal oxide semiconductor field effect transistor is adjacent to and connected with the n+1th N-type metal oxide semiconductor field effect transistor, and the source terminal of the n+1th N-type metal oxide semiconductor field effect transistor receives the lowest voltage, and the specific reference voltage is the rated voltage of the trigger circuit.