CN110620521B

CN110620521B - Multi-level inverter and capacitor voltage balancing method thereof

Info

Publication number: CN110620521B
Application number: CN201910916136.XA
Authority: CN
Inventors: 张永
Original assignee: Fonrich Shanghai New Energy Technology Co ltd
Current assignee: Fonrich Shanghai New Energy Technology Co ltd
Priority date: 2019-09-26
Filing date: 2019-09-26
Publication date: 2021-06-08
Anticipated expiration: 2039-09-26
Also published as: CN110620521A

Abstract

The invention mainly relates to a multi-level inverter and a capacitor voltage balancing method thereof. The inverter includes a single arm for generating a multi-level output voltage having an upper arm and a lower arm connected in series between first and second input terminals, the upper and lower arms being interconnected at a first intermediate node. Includes first and second reference voltage sources coupled to the first and second input terminals, respectively, with an upper capacitor and a lower capacitor connected in series between the first and second reference voltage sources and coupled at a second intermediate node. The voltage level of the second intermediate node is used as a voltage reference to generate a series of multi-level output voltages at the first intermediate node, a direct current voltage equivalent to the difference between the first reference voltage source and the second reference voltage source is input between the first input end and the second input end, and a waveform which changes according to a sine wave rule and is equivalent to an alternating current is synthesized between the first intermediate node and the second intermediate node by the series of multi-level output voltages.

Description

Multi-level inverter and capacitor voltage balancing method thereof

Technical Field

The invention mainly relates to the technical field of photovoltaic power generation, in particular to a multi-level inverter capable of supplying power to a local alternating current load or being connected to a power grid in a grid-connected mode and a method for balancing capacitor voltage in the inverter.

Background

One of the core power devices of photovoltaic power generation technology is an inverter, and ac power generated by solar energy can be supplied to a local ac load or used for grid-connecting abundant power to a public power grid. The multi-level inverter technology gradually becomes a new research field of converting high voltage and high power into a research object in the power electronic technology, and particularly, the flying capacitor type multi-level inverter has low harmonic distortion and extremely small electromagnetic interference and shows better inversion performance. The multilevel inverter as a high-voltage high-power converter has the following characteristics: each power device such as a switch and a capacitor only bears small voltage drop, and high-voltage high-power output can be realized by using a device with low voltage resistance; the increase of the number of levels means that the output voltage waveform is improved and the output waveform distortion is reduced; the low switching frequency obtains the same output voltage waveform as the high switching frequency, but can obtain the advantages of small switching loss and high efficiency; an isolated output transformer is not needed, so that the volume and the loss of the system are reduced; the harmonic wave of the input current is greatly reduced, and the pollution to a grid-connected network is reduced; when the three-phase electric induction motor is used for driving, neutral point level fluctuation can be reduced or eliminated to a higher degree; the safety is higher, and the danger of the short circuit of the bus is greatly reduced. On the main topological structure of an inverter circuit, a multi-level inverter has three common basic topological structures, namely diode clamping, flying capacitor and H-bridge cascade, and the flying capacitor type topological structure has higher multi-voltage configuration freedom.

According to the technical advantages of the flying capacitor type multi-level inverter, the flying capacitor type multi-level inverter is applied to photovoltaic power generation occasions, the multi-level requirement of output alternating current is fully considered, an inversion control scheme is established, and particularly, the level error is caused by unbalanced capacitor voltage of the flying capacitor. The application claims that the equalization measure of the capacitor voltage is applied to the flying capacitor type inversion structure, the feasibility of reducing common-mode current and parasitic electromagnetic interference and eliminating harmonic distortion is reduced to the utmost extent, and the mechanism for generating alternating current is clarified through the disclosed novel inversion topological model and the equalization scheme of the capacitor voltage.

Disclosure of Invention

In an optional but non-limiting embodiment of the present application, a multilevel inverter is disclosed and is primarily characterized by comprising the following parts: a single arm for generating a multilevel output voltage having an upper arm and a lower arm connected in series between first and second input terminals, the upper and lower arms being interconnected at a first intermediate node; first and second reference voltage sources coupled to the first and second input terminals, respectively, with an upper capacitor and a lower capacitor connected in series between the first and second reference voltage sources and coupled at a second intermediate node; generating a series of said multi-level output voltages at the first intermediate node with the voltage level at the second intermediate node as a voltage reference; a DC voltage equivalent to the difference between the first and second reference voltage sources is input between the first and second input terminals and a waveform which changes according to a sine wave law and is equivalent to an AC current is synthesized between the first and second intermediate nodes by a series of multi-level output voltages.

The above multilevel inverter, wherein: said single arm comprising a first set of switches, identified as the upper arm, and a second set of switches, identified as the lower arm, connected in series between first and second input terminals; and one or more flying capacitors are arranged between the interconnection node between any adjacent pair of switches in the first group of switches and the interconnection node between the corresponding adjacent pair of switches in the second group of switches.

The above multilevel inverter, wherein: monitoring the actual voltage value of at least a part of the flying capacitors, simultaneously comparing the actual voltage value of the monitored flying capacitors with an expected preset value, and selecting a specified level in the process of driving the single arm to generate the multilevel output voltage: when the actual voltage value is lower than the preset value, the first group of switches and the second group of switches are driven to generate the designated level, and simultaneously the flying capacitor to be monitored is synchronously charged; alternatively, when the actual voltage value is higher than the predetermined value, the first and second groups of switches are driven to generate the specified level while simultaneously discharging the monitored flying capacitor.

The above multilevel inverter, wherein: generating an SPWM modulation signal by an inner loop PI controller established based on the alternating current output by the multi-level inverter and an outer loop PI controller established based on the direct current voltage; the outer loop PI controller is used for setting a bus reference voltage as a given instruction value and synchronously adjusting the deviation of the actual input voltage of the multi-level inverter to the bus reference voltage; the inner loop PI controller is used for setting a result obtained by multiplying a current reference value given by the outer loop PI controller by the phase of the alternating voltage as a given instruction value and synchronously adjusting the deviation of the alternating current output by the multi-level inverter to the result; the SPWM modulated signal is used to drive first and second sets of switches to produce alternating current.

The above multilevel inverter, wherein: at least a portion of the monitored flying capacitor is charged or discharged at a time when the actual voltage value is adjusted to the predetermined value, including a zero-crossing point time of the alternating voltage.

The above multilevel inverter, wherein: the first set of switches is ordered from a first switch coupled to the first input to a last switch coupled to the first intermediate node; furthermore, the second set of switches is ordered from a first switch coupled to the second input to a last switch coupled to the first intermediate node; in addition, each of the switches in the first and second sets, which are in the same order, is set to a complementary switch, one of which is turned on and the other of which is turned off.

The above multilevel inverter, wherein: the capacitance value of the upper capacitor is equal to the capacitance value of the lower capacitor.

In an alternative embodiment of the present application, a method of achieving capacitor voltage balancing based on the aforementioned multi-level inverter is disclosed: a first group of switches which are regarded as upper arms and a second group of switches which are regarded as lower arms are connected in series between the first input end and the second input end; the first and second sets of switches are each ordered with the first switch furthest from the first intermediate node to the trailing switch closest to the first intermediate node; one or more flying capacitors are connected between the interconnection node between any adjacent pair of switches in the first group of switches and the interconnection node between the corresponding adjacent pair of switches in the second group of switches; the method comprises the following steps: monitoring an actual voltage value of at least a portion of the flying capacitor, comparing the actual voltage value of the monitored flying capacitor to an expected predetermined value; driving the single arm to generate multi-level output voltages and selecting a designated level from the multi-level output voltages; when the actual voltage value is sensed to be lower than the preset value, the first group of switches and the second group of switches are driven to generate the specified level and simultaneously charge the monitored flying capacitor; or when sensing that the actual voltage value is higher than the preset value, driving the first and second groups of switches to synchronously discharge the monitored flying capacitor while generating the specified level; thereby adjusting the actual voltage value of the monitored flying capacitor at the time when the specified level is generated, until the actual voltage value of the monitored flying capacitor tends to be equal to a desired predetermined value.

The method described above, wherein: the timing at which at least a portion of the monitored flying capacitor performs charging or discharging to achieve capacitor voltage balancing by adjusting the actual voltage value to a predetermined value includes the zero-crossing point timing of the alternating voltage.

The method described above, wherein: a plurality of direct current power supplies are directly connected in series between the first and second input terminals; or a plurality of voltage converters are connected in series between the first input end and the second input end, and each voltage converter is used for receiving the electric energy provided by one direct current power supply.

One of the biggest advantages of the multi-level inverter is that the output voltage has low harmonic content, the cost of the inverter system is greatly increased and the control is complex due to the excessive number of output levels, especially, the voltage of a flying capacitor is easy to deviate from a desired value, the alternating current output voltage is distorted due to the unbalanced voltage of the capacitor, and even harmonics and inconsistent voltage resistance of a switching tube are generated. The cumulative effect of even harmonics will further aggravate the midpoint voltage imbalance, and eventually the system will enter positive feedback and collapse. The general idea of measures for balancing the capacitor voltage of a three-phase 3L-NPC inverter, such as hysteresis loop, virtual space vector method, zero sequence voltage injection method and the like, which are used in some occasions in the industry is to realize the voltage balancing of the capacitor voltage by reasonably distributing redundant small vectors under the modulation of SVPWM signals. For example, the balance of a method of replacing an input capacitor with a plurality of direct current sources or adding a hardware circuit is adopted, so that the cost of the whole inverter system is greatly increased; the forced voltage division method of connecting large resistors in parallel on two sides of the capacitor increases circuit loss, and the methods do not solve the problem fundamentally and destroy the balance characteristic of the inverter circuit. The multi-level inverter can also adopt additional balancing circuits such as auxiliary components like RLC and the like to carry out capacitor voltage balancing control, but the cost is high. The scheme for realizing the capacitor voltage balance is simple and low in cost, and the control method does not influence the normal level output of the inverter.

Drawings

The features and advantages of the present application will become apparent upon reading the following detailed description and upon reference to the following drawings.

Fig. 1 is a main topology circuit architecture adopted by the flying capacitor type multilevel inverter of the present application.

Fig. 2 is a circuit topology of an upper arm first set of six switches and a lower arm second set of six switches.

Fig. 3 is an inverter system based on different reference voltage sources and generating multiple levels by single-arm switches.

Fig. 4 shows the input voltages as first and second reference voltage sources coupled to the first and second input terminals.

Fig. 5 is a graph of the use of an outer voltage loop and an inner voltage loop to generate modulation signals that control the various switches of the inverter.

Fig. 6 is an example of a negative-going to positive-going curve of a synthesized sine wave from a multi-level output voltage.

Fig. 7 is an example of a positive-going to negative-going curve of a synthesized sine wave from a multi-level output voltage.

FIG. 8 is a method flow of taking steps to perform voltage equalization on flying capacitors in a multilevel inverter.

Detailed Description

The technical solutions of the present invention will be clearly and completely explained below with reference to various embodiments, and the described embodiments are only used as illustrative embodiments of the present invention and not all embodiments, and the solutions obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

Referring to fig. 1, with the rapid development of control theory, power electronics technology and semiconductor devices, a lower-cost and higher-efficiency inverter is sought to realize that single-phase or multi-phase alternating current becomes a hot spot of power electronics, and a Flying capacitor type Flying-capacitor clamping type multi-level inversion scheme proposed by MEYNARD and FOCH in a multi-level inverter circuit in the alternating current field is very featured, thereby bringing great attention to the field of speed regulation of medium and high power alternating current motors, and having small harmonic distortion, low stress of semiconductor devices and low electromagnetic interference of an inversion system. In the figure, a direct current voltage source is provided between the transmission line LNA and the transmission line LNB, and if the transmission line LNA has a potential VD and the transmission line LNB has a potential VR, the direct current input to the multi-level inverter is VD minus VR.

Referring to fig. 1, a plurality of dc power supplies may be directly connected in series between the transmission line LNA and the transmission line LNB, i.e., between the first and second input terminals, and the dc power supplies typically include: photovoltaic modules, fuel cells, chemical cells and other types of energy storage battery packs, and the like. In the first case: the dc power supplies are allowed to be directly connected in series to obtain a cascade voltage having a high voltage level by superposition, and then the cascade voltage is used as a dc voltage to be input to the inverter between the first and second input terminals. As an alternative second case: the direct current power supply is not directly connected in series between the transmission line LNA and the transmission line LNB, but a plurality of voltage converters are connected in series between the first input end and the second input end, the voltage converters belong to a switch mode power supply SMPS, and the switch mode power supply is also called as an exchange power supply and a switch converter, and is a high-frequency electric energy conversion device for DC/DC conversion; at this time, the direct current power supply is not directly connected in series between the transmission line LNA and the transmission line LNB, the plurality of voltage converters are directly connected in series between the transmission line LNA and the transmission line LNB, the voltage converters are direct current to direct current voltage converters, each voltage converter is used for receiving electric energy provided by a corresponding direct current power supply and performing power conversion on the electric energy, and the voltages output by the plurality of voltage converters are superposed to be transmitted to the position between the transmission line LNA and the transmission line LNB as serial-level voltages. The advantages of the second case are: a certain voltage converter may adopt a scheme of maximum power point tracking in performing power conversion on electric energy provided by a corresponding direct current power supply. The output power of the photovoltaic module is affected by factors such as the irradiation intensity of peripheral sunlight and temperature in most occasions, and the voltage converter can track the maximum output power point of the photovoltaic module, namely the output voltage and the output current of the photovoltaic module are set at the maximum power point in the power conversion process. Because photovoltaic modules or chemical batteries and the like are influenced by various external factors such as irradiance, temperature and the like, the instability of the output power of the direct-current power supply further causes the cascade voltage between the transmission lines LNA and LNB not to be very stable, and the definition of the transmission lines LNA-LNB as the direct-current bus proves that the voltage U of the direct-current bus, namely the input voltage of the inverter, is allowed to float up and down.

Referring to fig. 1, the topology is widely representative using a single arm with a variable number of switches and K +1 switches for both the upper arm and the lower arm. The upper arms SA _1 to SA _ K +1 and the lower arms SB _1 to SB _ K +1 respectively constitute a first group of switches and a second group of switches of the flying capacitor type multilevel inverter. Flying capacitor C _ K is connected between interconnection node NA _ K between any adjacent pair of switches SA _ K and SA _ K +1 in the first group of switches and interconnection node NB _ K between corresponding adjacent pair of switches SB _ K and SB _ K +1 in the second group of switches, and it is noted that K, which is described as a natural number, is greater than or equal to 2. The condition is satisfied in the single arm: among the pair of switches SA _ K and SA _ K +1 and the corresponding pair of switches SB _ K and SB _ K +1, a switch SA _ K in the first set of switches is complementary to a switch SB _ K in the second set of switches, and a switch SA _ K +1 in the first set is complementary to a switch SB _ K +1 in the second set. The single arm has an upper arm and a lower arm connected in series between a first input, transmission line LNA, and a second input, transmission line LNB, and is used to generate a multilevel output voltage: the upper arms SA _1 to SA _ K +1 and the lower arms SB _1 to SB _ K +1 are connected to the first intermediate node NX, i.e., an arm point, and a number of switches K +1 are respectively applied to the upper and lower arms. In this topology the first set of switches is ordered sequentially from the first switch SA _1 connected to the transmission line LNA to the switch SA _ K +1 connected to the end of the intermediate node NX, and the second set of switches is ordered sequentially from SB _1 connected to the transmission line LNB, denoted as the first switch, to the switch SB _ K +1 connected to the end of the intermediate node NX, any one of the switches of the first set and the one of the switches of the second set having the same ordering being set as a pair of complementary switches. The direct current voltage source is input from between the transmission line LNA and the transmission line LNB, the multi-level voltage is output from the intermediate node NX, and the filter inductor LX may be further connected to the intermediate node NX. The first and second sets of switches are generally considered to constitute a single leg of a multilevel inverter, and the combination of the single legs may constitute a multi-phase inverter.

Referring to fig. 2, taking as an example a first set of six switches and a second set of six switches, the first and second sets of switches are each controlled by a high frequency pulse width modulated signal/control signal PWM coupled to a control terminal of the switch to switch between off and on. In fact, the number of the switches of the first group and the second group is not limited to six, more or fewer switches can be selected adaptively as shown in fig. 1, and in the field of power electronics, power switches such as IGBTs and MOSFETs or power switches similar to thyristors can be adopted as the switches. The first set of switches SA1-SA6 and the second set of switches SB1-SB6 constitute a single arm of the multilevel inverter, the number of switches in each set may not be limited to six but a greater or lesser number, the individual switches SA1-SA6 in the first set of switches are connected in series between the transmission line LNA and the intermediate node NX, and the individual switches SB1-SB6 in the second set of switches are connected in series between the transmission line LNB and the intermediate node NX. The switch tube is provided with a first end, a second end and a control end for receiving a control signal, and the control signal is conducted between the first end and the second end if the switch tube is controlled to be conducted or is disconnected between the first end and the second end if the switch tube is controlled to be disconnected. The position relations of the switches in the first group of switches SA1-SA6 are, for example: the first terminal of the first switch SA1 is connected to the transmission line LNA, the first terminal of the following switch SA2 is connected to the second terminal of the adjacent previous switch SA1, the first terminal of the following switch SA3 is connected to the second terminal of the adjacent previous switch SA2, and so on, according to the rule, the first terminal of the following switch SA5 is connected to the second terminal of the adjacent previous switch SA4, the first terminal of the last switch SA6 is connected to the second terminal of the adjacent switch SA5 and the second terminal of the switch SA6 is connected to the intermediate node NX. The first terminal of the first switch SA1 in the first set of switches is connected to the transmission line LNA and the second terminal of the last switch SA6 is connected to the intermediate node NX and the first terminal of any subsequent switch is connected to the second terminal of the adjacent previous switch. The position relations of the switches in the second group of switches SB1-SB6 are as follows: the second end of the first switch SB1 is connected to the transmission line LNB, the second end of the next switch SB2 is connected to the first end of its adjacent previous switch SB1, the second end of the next switch SB3 is connected to the first end of its adjacent previous switch SB2, and so on, the second end of the next switch SB5 is connected to the first end of its adjacent previous switch SB4, and the second end of the last switch SB6 is connected to the switch SB5, i.e. the first ends of the adjacent switches and the first end of the last switch SB6 is connected to the intermediate node NX. The second terminal of the first switch SB1 in the second set of switches is connected to the transmission line LNB and the first terminal of the last switch SB6 is connected to the intermediate node NX with the second terminal of any subsequent switch being connected to the first terminal of the adjacent previous switch.

Referring to fig. 2, the first set of switches SA1-SA6 is ordered sequentially from the first switch SA1 connected to the transmission line LNA to the switch SA6 connected to the end of the intermediate node NX, and the second set of switches SB1-SB6 is ordered sequentially from the first switch SB1 connected to the transmission line LNB to the switch SB6 connected to the end of the intermediate node NX. The first switch SA1 of the first group and the first switch SB1 of the second group are complementary switches to each other, the second switch SA2 of the first group and the second switch SB2 of the second group are complementary switches, the third switch SA3 of the first group and the third switch SB3 of the second group are complementary switches, the fourth switch SA4 of the first group and the fourth switch SB4 of the second group are complementary, and the fifth switch SA5 of the first group and the fifth switch SB5 of the second group are complementary to each other, and so on until the sixth switch SA6 of the first group and the sixth switch SB6 of the second group are defined as complementary switches. Complementary switches mean that one of the complementary switches is on and the other is off. As a flying capacitor type multilevel inverter scheme, one or more capacitors are connected between one interconnection node between any adjacent pair of switches in the first group of switches and one interconnection node between a corresponding pair of adjacent switches in the second group of switches, thereby constituting a single arm of the flying capacitor type multilevel inverter.

Referring to fig. 2, one or more capacitors C1 are connected between an interconnection node NA1 between an adjacent pair of switches SA1-SA2 in the first set of switches and an interconnection node NB1 between a corresponding adjacent pair of switches SB1-SB2 in the second set of switches, wherein: the second terminal of switch SA1 and the first terminal of switch SA2 are connected to interconnection node NA1 and also the first terminal of switch SB1 and the second terminal of switch SB2 are connected to interconnection node NB 1.

Referring to fig. 2, one or more capacitors C2 are connected between an interconnection node NA2 between an adjacent pair of switches SA2-SA3 in the first set of switches and an interconnection node NB2 between a corresponding adjacent pair of switches SB2-SB3 in the second set of switches, wherein: the second terminal of switch SA2 and the first terminal of switch SA3 are connected to interconnection node NA2 and also the first terminal of switch SB2 and the second terminal of switch SB3 are connected to interconnection node NB 2.

Referring to fig. 2, one or more capacitors C3 are connected between an interconnection node NA3 between an adjacent pair of switches SA3-SA4 in the first set of switches and an interconnection node NB3 between a corresponding adjacent pair of switches SB3-SB4 in the second set of switches, wherein: the second terminal of switch SA3 and the first terminal of switch SA4 are connected to interconnection node NA3 and also the first terminal of switch SB3 and the second terminal of switch SB4 are connected to interconnection node NB 3.

Referring to fig. 2, one or more capacitors C4 are connected between an interconnection node NA4 between an adjacent pair of switches SA4-SA5 in the first set of switches and an interconnection node NB4 between a corresponding adjacent pair of switches SB4-SB5 in the second set of switches, wherein: the second terminal of switch SA4 and the first terminal of switch SA5 are connected to interconnection node NA4 and also the first terminal of switch SB4 and the second terminal of switch SB5 are connected to interconnection node NB 4.

Referring to fig. 2, one or more capacitors C5 are connected between an interconnection node NA5 between an adjacent pair of switches SA5-SA6 in the first set of switches and an interconnection node NB5 between a corresponding adjacent pair of switches SB5-SB6 in the second set of switches, wherein: the second terminal of switch SA5 and the first terminal of switch SA6 are connected to interconnection node NA5 and also the first terminal of switch SB5 and the second terminal of switch SB6 are connected to interconnection node NB 5.

Referring to fig. 3, an output stage is additionally provided in this embodiment compared to the single arm of fig. 1. The aforementioned series of multi-level output voltages is generated at a first intermediate node with a reference voltage source present at a second intermediate node as a voltage reference. Such as first and second reference voltage sources coupled to the first and second input terminals, respectively, with an upper capacitor (e.g., one or more capacitors CU) and a lower capacitor (e.g., one or more capacitors CD) coupled in series between the first and second reference voltage sources, and the upper and lower capacitors coupled at a second intermediate node NZ, with the second intermediate node having a voltage level, e.g., denoted as V3, as a voltage reference to produce a series of the multi-level output voltages at the first intermediate node. Take three reference voltage sources as an example: the highest voltage level reference voltage source V1 is coupled to transmission line LNA and the second voltage level reference voltage source V3 is coupled to transmission line LNE1/LNE2 through capacitive devices CU/CD respectively and the lowest voltage level reference voltage source V2 is coupled to transmission line LNB. In an alternative embodiment, the single-arm first intermediate node NX generates a series of multi-level output voltages referenced to a voltage reference from a reference voltage source V3, the load LD is connected between the first intermediate node NX and a second intermediate node NZ, the load is applied between the output terminals OUT1-OUT2, the output terminal OUT1 is coupled to the first intermediate node NX and the output terminal OUT2 is coupled to the second intermediate node NZ. Direct current is input between the first input end and the second input end, namely between the LNA-LNB, and a series of multi-level output voltages are generated to synthesize a waveform which changes according to a sine wave rule and is equivalent to alternating current between the first intermediate node NX-NZ and the second intermediate node NX-NZ. The third voltage, i.e., reference voltage source V3, may be an independent voltage source, the second voltage, i.e., reference voltage source V2, may be an independent voltage, and the first voltage, i.e., reference voltage source V1, may also be an independent voltage, without any relation therebetween being allowed.

Referring to fig. 3, if transmission line LNE1 is directly connected to the transmission line with reference voltage source V1, correspondingly if transmission line LNE2 is directly connected to the transmission line with reference voltage source V2, two or more voltage dividing capacitors such as serial voltage dividing capacitors CU-CD are connected in series between transmission lines LNE1 and LNE 2. The voltage dividing capacitors CU and CD are interconnected at a voltage dividing node, which is also substantially a second intermediate node NZ: the capacitance values of the voltage dividing capacitors can be the same or different, which is equivalent to that a voltage dividing capacitor CU is connected between the transmission line LNE1 and the voltage dividing node NZ and a voltage dividing capacitor CD is connected between the transmission line LNE2 and the voltage dividing node NZ. A desired reasonable divided voltage value or a reasonable clamping voltage value can be obtained at the dividing node/the second intermediate node NZ. It can also be understood in essence that: the reference voltage source V3, which connects two or more voltage dividing capacitors in series between the first voltage V1 and the second voltage V2 to obtain the third voltage at the second intermediate node NZ, is equivalent to connecting two or more voltage dividing capacitors in series between the reference voltage sources V1 and V2 to obtain the third voltage at the voltage dividing node NZ. If the above-mentioned capacitors CU and CD are equal, the voltage drop of the first voltage, i.e., V1, with respect to the third voltage, i.e., V3, is equal to the voltage drop of the third voltage, i.e., V3, with respect to the second voltage, i.e., V2, in other words, the third voltage is allowed, and V1-V3= V3-V2 is a preferred embodiment. In an alternative embodiment the transmission line LNE1 with voltage V1 is coupled to the LNA and the transmission line LNE2 with voltage V2 is correspondingly coupled to the LNB, which is an alternative embodiment illustrated in fig. 3.

Referring to fig. 3, in an alternative embodiment, the second voltage, i.e. reference voltage source V2, is no longer an independent voltage and the aforementioned first voltage, i.e. reference voltage source V1, is no longer an independent voltage, but rather the potential of reference voltage source V1 is set equal to the potential VD present on transmission line LNA, while at the same time the potential of reference voltage source V2 is set equal to the potential VR present on transmission line LNB. As shown, the transmission line LNE1 with the reference voltage source V1 is directly coupled to the transmission line LNA with the potential VD, while the transmission line LNE2 with the reference voltage source V2 is directly coupled to the transmission line LNB with the potential VR. The capacitor CU-CD is interconnected at the voltage dividing node: a voltage dividing capacitor CU is connected between the transmission line LNE1 and the voltage dividing node NZ and a voltage dividing capacitor CD is also connected between the transmission line LNE2 and the voltage dividing node NZ, and the capacitance values of the voltage dividing capacitors CU-CD may be the same or different. A desired reasonable value of the divided voltage can be achieved at the divided voltage node NZ. If the capacitors CU and CD are equal, the voltage drop of the first voltage, i.e. V1, with respect to the third voltage, i.e. V3, is equal to the voltage drop of the third voltage, i.e. V3, with respect to the second voltage, i.e. V2, in other words, the third voltage is the midpoint potential of the first voltage and the second voltage, and VD-V3= V3-VR is a preferred embodiment, where the potential of the first voltage is equal to the potential VD of the first input terminal and the potential of the second voltage is equal to the potential VR of the second input terminal.

Referring to fig. 4, in an alternative embodiment, a multilevel inverter system for generating ac power controlled by high frequency switching single-leg switches is disclosed, where the multilevel inverter may comprise the single-leg of fig. 1-3, where the single-leg may output a plurality of level levels of output voltage, where the output level includes a plurality of reference voltage sources having different voltage levels. The function of the output stage comprises switching the output voltages of the plurality of level levels to suitable voltage references, since the output voltages of the plurality of level levels only exhibit a voltage level or a level magnitude with a relatively well-defined voltage reference.

Referring to fig. 4, in this embodiment the multilevel inverter includes a first set of switches SA1-SA3 connected between the transmission line LNA and the intermediate node NX, and a second set of switches SB1-SB3 connected between the transmission line LNB and the intermediate node NX, the upper arms SA1-SA3 of the multilevel inverter being connected in series between the transmission line LNA and the intermediate node NX and the lower arms SB1-SB3 of the multilevel inverter being connected in series between the transmission line LNB and the intermediate node NX, also directly expressed as the first set of switches and the second set of switches being connected in series between the transmission line LNA and the transmission line LNB. In a multilevel inverter: one or more capacitors C1 are connected between an interconnection node NA1 between any adjacent pair of switches SA1-SA2 in the first set of switches and an interconnection node NB1 between a corresponding adjacent pair of switches SB1-SB2 in the second set of switches, and one or more capacitors C2 are provided between an interconnection node NA2 between any adjacent pair of switches SA2-SA3 in the first set of switches and an interconnection node NB2 between a corresponding adjacent pair of switches SB2-SB3 in the second set of switches. As described above, the complementary switches SA1-SB1, SA2-SB2 and SA3-SB3 are satisfied to thereby constitute a single arm based on the flying capacitor type clamped inversion scheme. The power supply V1 in the output stage is connected at the second intermediate node NZ through some capacitors CU, the power supply V2 is connected at the second intermediate node NZ through some capacitors CD, and the reference power supply V3 in the output stage is equivalent to at the second intermediate node NZ. More than two voltage dividing capacitors such as voltage dividing capacitors CU-CD connected in series are connected between the transmission lines LNE1-LNE2, that is, the voltage dividing capacitor CU is connected between the transmission line LNE1 and the voltage dividing node and the voltage dividing capacitor CD is connected between the transmission line LNE2 and the voltage dividing node NZ, and the voltage dividing node obtains a desired reasonable voltage dividing value and serves as a voltage source V3. The transmission line LNE1 with the reference voltage source V1 is coupled to the input transmission line LNA with the potential VD, while the transmission line LNE2 with the reference voltage source V2 is directly coupled to the input transmission line LNB with the potential VR. To avoid confusion, the intermediate node NX of the single arm of the inverting part may be set as a first defined intermediate node, and the intermediate node NZ of the output stage may be set as a second defined intermediate node. The control switches, i.e. the first and second group of switches mentioned above, are power semiconductor switches having first and second terminals and a control terminal for receiving a control signal/modulation signal, which if controlling the switches to be on corresponds to the first and second terminals of the switch being on or the switches to be off corresponds to the first and second terminals of the switch being off, for example the first and second terminals may be drain and source terminals or vice versa of a field effect transistor, for example the collector and emitter of an insulated gate bipolar transistor or vice versa, of course the anode and cathode of a thyristor or vice versa, the control terminal of the switch is a gate or gate terminal or the like and the switch may also be a thyristor switching device or the like. Alternating current is generated between a first output terminal OUT1 and a second output terminal OUT2 as output terminals of the output stage, the first output terminal OUT1 is coupled to the intermediate node NX of the single arm and the corresponding second output terminal OUT2 is coupled to the intermediate node NZ, and an alternating current load LD portion is connected between the first and second output terminals OUT-OUT 2. A filter inductance LX may be connected between the first output terminal OUT1 and the intermediate node NX and a filter capacitance CX may also be connected between the first and second output terminals OUT-OUT 2. Direct current is input between the first and second input terminals, i.e. between the transmission lines LNA-LNB, whereby a waveform varying according to a sine wave law and equivalent to alternating current is synthesized between said first and second intermediate nodes NX-NZ by the series of multilevel output voltages, the alternating current load LD being coupled between the first and second intermediate nodes NX-NZ.

Referring to fig. 4, in an alternative embodiment, an alternative, but not necessary, way of generating alternating current is illustrated in conjunction with the topology of fig. 4. Assuming that the transmission line LNA has a potential VD and the transmission line LNB has a potential VR, the dc voltage input to the multilevel inverter is VD minus VR, and the difference is equal to U. Assuming that capacitors CS1-CS2 and the like are connected in series between the reference ground potential G and the transmission line LNA, and capacitors CS3-CS4 and the like are connected in series between the reference ground potential G and the transmission line LNB, it is equivalent to divide the dc input voltage U of the multilevel inverter into two equal parts, such as a positive U/2 potential of the transmission line LNA with respect to the reference ground potential G, and the potential of the transmission line LNB with respect to the reference ground potential G is a negative U/2 potential, and VD-VR = U is satisfied. In an alternative embodiment, capacitors C11-C12 are connected in series between node NA1 and another node NB1, a capacitor C2 is connected between node NA2 and node NB2, and capacitors C11-C12 are charged to U/2 and capacitor C2 is charged to U/4 in total during the initial charging setup voltage phase. The bus voltage U or notation U is explained hereinbefore_BUSThe voltage of the battery can float up and down, the U is not required to be a continuously fixed value, particularly, the voltage of the battery on the site of photovoltaic power generation is considered to be changed along with day and night alternation in a large fluctuation mode, and the inverter control scheme can be operated more conveniently if the voltage of the U is continuously fixed.

Referring to fig. 4, the on/off combination of the single-arm switch is: the first set of switches SA1-SA3 of the upper arm are all off and the complementary relationship is such that the second set of switches SB1-SB3 of the lower arm are all on. In this mode the output level at the intermediate node NX of the multilevel inverter is then approximately negative U/2 with respect to the intermediate node NZ. The flying capacitor C11-C12 is set to a non-charging and non-discharging state in this mode and the flying capacitor C2 is neither charging nor discharging.

Referring to fig. 4, the on/off combination of the single-arm switch is: the first set of upper arm switches SA1/SA2 is off but SA3 is on and the complementary relationship has the second set of lower arm switches SB1/SB2 on but SB3 is off. In this mode the output level at the intermediate node NX is then approximately negative U/4 with respect to NZ. The flying capacitor C11-C12 is set to a non-charging and discharging state in this mode and the flying capacitor C2 discharges.

Referring to fig. 4, the on/off combination of the single-arm switch is: the first set of upper arm switches SA1/SA3 is off but SA2 is on and the complementary relationship has the second set of lower arm switches SB1/SB3 on but SB2 is off. In this mode the output level at the intermediate node NX is then approximately negative U/4 with respect to NZ. The flying capacitor C11-C12 is set to the discharged state in this mode and the flying capacitor C2 charges.

Referring to fig. 4, the on/off combination of the single-arm switch is: the first set of upper arm switches SA2/SA3 is on but SA1 is off and the complementary relationship has the second set of lower arm switches SB2/SB3 is off but SB1 is on. In this mode then the output level at the intermediate node NX is about zero with respect to NZ. The flying capacitor C11-C12 is placed in a discharged state in this mode and flying capacitor C2 is neither charged nor discharged.

Referring to fig. 4, the on/off combination of the single-arm switch is: the first set of upper arm switches SA2/SA3 is off but SA1 is on and the complementary relationship has the second set of lower arm switches SB2/SB3 on but SB1 is off. In this mode then the output level at the intermediate node NX is about zero with respect to NZ. The flying capacitor C11-C12 is placed in a charged state in this mode and the flying capacitor C2 is neither charged nor discharged.

Referring to fig. 4, the on/off combination of the single-arm switch is: the first set of upper arm switches SA1/SA3 is on but SA2 is off and the complementary relationship has the second set of lower arm switches SB1/SB3 is off but SB2 is on. In this mode the output level at the intermediate node NX is then approximately positive U/4 with respect to NZ. The flying capacitor C11-C12 is placed in a charged state in this mode and the flying capacitor C2 discharges.

Referring to fig. 4, the on/off combination of the single-arm switch is: the first set of upper arm switches SA1/SA2 is on but SA3 is off and the complementary relationship has the second set of lower arm switches SB1/SB2 is off but SB3 is on. In this mode the output level at the intermediate node NX is then approximately positive U/4 with respect to NZ. The flying capacitor C11-C12 is placed in neither a charging nor a discharging state in this mode and the flying capacitor C2 is charged.

Referring to fig. 4, the on/off combination of the single-arm switch is: the first set of switches SA1-SA3 of the upper arm are all ON and the complementary relationship is such that the second set of switches SB1-SB3 of the lower arm are all OFF. In this mode, the output level at the intermediate node NX of the single arm of the multilevel inverter is then positive U/2 with respect to the intermediate node NZ. The flying capacitor C11-C12 is placed in neither charging nor discharging states in this mode and the flying capacitor C2 is neither charging nor discharging.

Referring to fig. 6, looking at curve U1, curve U1 is essentially a partial segment of a full alternating current sine wave. Attempting to synthesize curve U1 at the multi-level output voltage output at the single-arm intermediate node NX relative to the intermediate node NZ may take into account the negative U/2 and negative U/4 timing control schemes previously described if the topology of FIG. 4 is intended to be the subject of control. At time points T0 to T1 on the time axis T, in conjunction with the timing control of fig. 4, a sinusoidal half-wave or a partial segment of a sinusoidal half-wave is replaced by a series of narrow pulses of equal amplitude but unequal width, i.e., the SPWM waveform of the industry, in which the pulse width varies sinusoidally and is modulated like a PWM waveform equivalent to a sine wave. The output waveform U1 between the first and second output terminals OUT1-OUT2 is a multi-level output based on the potential of the intermediate node NX relative to the potential V3 of the intermediate node NZ as a reference, and in an alternative embodiment, the curve U1 in fig. 6 illustrates a multi-level output mechanism by generating negative-going ripples with the value of V3 or with its absolute value as a reference, and the peak-to-peak values of the sine waves are set as positive and negative VM.

Referring to fig. 6, looking at curve U2, curve U2 is essentially a partial segment of a full alternating current sine wave. If one were to attempt to synthesize the curve U2 at the multi-level output voltage output at the single-arm intermediate node NX relative to the intermediate node NZ with the topology of fig. 4 as the subject of control, one could consider the negative U/4 and 0 timing control scheme previously described. Here again, the waveform U2 output between the first output terminal OUT1 and the second output terminal OUT2 arranged between the single arm and the output stage, with a series of narrow pulses of equal amplitude but unequal width instead of a sinusoidal half-wave or a partial segment of a sinusoidal half-wave: is a multi-level output realized based on the potential of the intermediate node NX as a voltage reference with respect to the potential V3 at the aforementioned voltage dividing node NZ, the curve U2 in fig. 6 illustrates a multi-level output mechanism with negative-going ripples generated with the value of V3 or with its absolute value as a reference value at time points T1 to T2 of the time axis T.

Referring to fig. 6, looking at curve U3, curve U3 is essentially a partial segment of a full alternating current sine wave. If one were to attempt to synthesize the curve U3 at the multi-level output voltage output at the single-arm intermediate node NX relative to the intermediate node NZ with the topology of fig. 4 as the subject of control, one could consider the aforementioned 0 and positive U/4 timing control scheme. Here too, a series of narrow pulses of equal amplitude but unequal width are used instead of a sinusoidal half-wave or a partial segment of a sinusoidal half-wave. Waveform U3 output between the first output terminal OUT1 and the second output terminal OUT2 arranged between the single arm and the output stage: is a multilevel output realized based on the potential of the intermediate node NX as a voltage reference with respect to the potential V3 at the aforementioned voltage dividing node NZ, the curve U3 in fig. 6 illustrates a multilevel output mechanism by generating a forward ripple with the value of V3 or with its absolute value as a reference value at time points T2 to T3 of the time axis T.

Referring to fig. 6, looking at curve U4, curve U4 is essentially a partial segment of a full alternating current sine wave. If it is intended to take the topology of fig. 4 as a controlled object, it is attempted to synthesize the curve U4 at the multilevel output voltage outputted at the intermediate node NX of the single arm with respect to the intermediate node NZ, a timing control scheme with positive U/4 and positive U/2 may be considered. Here a series of narrow pulses of equal amplitude but unequal width are used instead of a sinusoidal half-wave or a partial segment of a sinusoidal half-wave. Waveform U4 output between the first output terminal OUT1 and the second output terminal OUT2 arranged between the single arm and the output stage: is a multi-level output realized based on the intermediate node NX potential as a voltage reference with respect to the potential V3 at the aforementioned voltage dividing node NZ, it is noted that at time points T3 to T4 of the time axis T, the curve U4 in fig. 6 illustrates a multi-level output mechanism by generating a forward ripple with the value of V3 or with its absolute value as a reference value. Curves U1-U4 are four consecutive partial segments of a waveform that varies regularly in a sine wave so that they combine to form a half cycle of a complete sine wave Curve1 over time periods t0 to t 4. In an alternative embodiment, consider that during a cycle of the AC waveform Curve1, such as t0-t 8: multi-level output voltages such as negative U/2 and negative U/4 generated by the corresponding reference voltage source V3 as voltage reference during the divided determined period, i.e., t0 to t1, to synthesize a partial segment U1 of the alternating current Curve1 varying in accordance with the sine wave law during the period, i.e., time t0 to t 1; the multi-level output voltages such as 0 and negative U/4 and positive U/4 and 0 generated by the corresponding reference voltage source V3 as voltage reference in the divided determined period, i.e., t1 to t3, are combined into a partial segment U2-U3 of the alternating current Curve1 in the period t1-t3, which varies according to the sine wave rule; the multilevel output voltages, e.g. positive U/4 and positive U/2, generated by the respective voltage source V3 as voltage reference during the divided determined time periods, i.e. t3 to t4, synthesize a partial segment U4 of the alternating current waveform Curve1 which varies according to a sine wave law during this time period, i.e. time t3 to t 4. Thereby achieving a half cycle of the full sine wave Curve 1.

Referring to figure 6, in an alternative embodiment, it is desirable to monitor the actual voltage value of at least a portion of the flying capacitor, such as capacitor C2, and compare the actual voltage value of the flying capacitor C2 being monitored with a desired predetermined value, and select a specified level, such as negative U/4, in driving the single arm to produce a multilevel output voltage, where the predetermined value of the flying capacitor C2 being monitored should be approximately equal to U/4, for example. For example, the partial segment curves U1-U2 that generate a complete sine wave according to the foregoing description use a specified level of negative U/4. The actual voltage value of the monitored flying capacitor C2 is compared to a desired predetermined value U/4: when the actual voltage value sensed by flying capacitor C2 is below a predetermined value, then it is necessary to drive the first and second sets of switches to produce the specified level, for example negative U/4, while simultaneously charging the flying capacitor being monitored, for example with the first set of switches of the upper arm SA1/SA3 off but SA2 on and the complementary relationship having the second set of switches of the lower arm SB1/SB3 on but SB2 off, in which mode the output level at intermediate node NX is about a negative U/4 level relative to intermediate node NZ and flying capacitor C2 charges to compensate for the charge. Or the actual voltage value of the monitored flying capacitor C2 is compared to a desired predetermined value U/4: the flying capacitor C2 discharges to compensate for the charge when the actual sensed voltage value of flying capacitor C2 is above a predetermined value, while driving the first and second sets of switches to produce the specified level, e.g., the first set of upper arm switches SA1/SA2 are off but SA3 is on and the complementary relationship causes the second set of lower arm switches SB1/SB2 to be on but SB3 to be off, in which mode the output level at intermediate node NX is about a negative U/4 level relative to intermediate node NZ.

Referring to fig. 6, in other embodiments, the actual voltage value of at least a portion of the flying capacitor, such as capacitors C11-C12, may be monitored, the actual voltage value of the monitored flying capacitors C11-C12 may be compared to a desired predetermined value, and a specified level, such as a zero level, may be selected in driving the single arm to produce a multilevel output voltage, under which condition the total predetermined value of the monitored flying capacitors C11-C12, such as U/2, should be approximately equal. For example, the partial segment curves U2-U3 that generate a complete sine wave according to the foregoing description use the designated level of zero level. The actual voltage values of these monitored flying capacitors C11-C12 are claimed to be compared to a desired predetermined value U/2: when the actual voltage value of the monitored object, flying capacitors C11-C12, is sensed to be below a predetermined value, then the first and second sets of switches are driven to produce the specified level, e.g., zero level, while the monitored flying capacitors C11-C12 are simultaneously charged, e.g., as described above, with the upper arm first set of switches SA2/SA3 off but SA1 on and the complementary relationship with the lower arm second set of switches SB2/SB3 on but SB1 off, the output level at the intermediate node NX is made to be about zero level with respect to NZ in this mode and the flying capacitors C11-C12 are placed in a charged state to compensate for the charge. Or the actual voltage value of the flying capacitor C11-C12 is compared with the expected preset value U/2: the flying capacitor being monitored is simultaneously discharged while driving the first and second sets of switches to produce the specified zero level when the sensed actual voltage value of the flying capacitor is above the predetermined value, e.g., as described above, the first set of switches of the upper arm SA2/SA3 is on but switch SA1 is off and the complementary relationship causes the second set of switches of the lower arm SB2/SB3 to be off but SB1 to be on, in which mode the output level at the intermediate node NX is about zero level with respect to NZ, and flying capacitors C11-C12 are placed in a discharged state to compensate for the charge. In this embodiment, the timing of the monitored flying capacitors C11-C12 to perform charging or discharging with the actual voltage adjusted to a predetermined value includes the zero crossing point of the ac voltage, the zero crossing points of the partial segment curves U2-U3 representing the complete sine wave of the ac voltage are t2 and t6 of fig. 7, the essence of generating the sine wave is to replace the waveform with a series of narrow pulses of equal amplitude but unequal width, and in the alternative, implementing the charge compensation of the capacitors at the zero crossing point of the ac voltage can avoid distortion of the sine wave to some extent.

Referring to fig. 7, in other embodiments, the topology of fig. 4 may also form the waveform of fig. 7, and the above description mainly describes the waveform of fig. 6 formed by using the topology of fig. 4. The following of the present application will continue to present different timing control schemes to distinguish from the timing used in the waveforms of fig. 6.

Referring to fig. 4, the on/off combination of the single-arm switch is: the first set of switches SA1-SA3 of the upper arm are all off and the complementary relationship is such that the second set of switches SB1-SB3 of the lower arm are all on. In this mode, the output level at the intermediate node NX of the single arm of the multilevel inverter is then positive U/2 with respect to the intermediate node NZ. The flying capacitor C11-C12 is placed in neither charging nor discharging states in this mode and the flying capacitor C2 is neither charging nor discharging.

Referring to fig. 4, the on/off combination of the single-arm switch is: the first set of upper arm switches SA1/SA2 is off but SA3 is on and the complementary relationship has the second set of lower arm switches SB1/SB2 on but SB3 is off. In this mode the output level at the intermediate node NX is then approximately positive U/4 with respect to NZ. The flying capacitor C11-C12 is placed in neither a charging nor a discharging state in this mode and the flying capacitor C2 is charged.

Referring to fig. 4, the on/off combination of the single-arm switch is: the first set of upper arm switches SA1/SA3 is off but SA2 is on and the complementary relationship has the second set of lower arm switches SB1/SB3 on but SB2 is off. In this mode the output level at the intermediate node NX is then approximately positive U/4 with respect to NZ. The flying capacitor C11-C12 is placed in a charged state in this mode and the flying capacitor C2 discharges.

Referring to fig. 4, the on/off combination of the single-arm switch is: the first set of upper arm switches SA2/SA3 is on but SA1 is off and the complementary relationship has the second set of lower arm switches SB2/SB3 is off but SB1 is on. In this mode then the output level at the intermediate node NX is about zero with respect to NZ. The flying capacitor C11-C12 is placed in a charged state in this mode and the flying capacitor C2 is neither charged nor discharged.

Referring to fig. 4, the on/off combination of the single-arm switch is: the first set of upper arm switches SA2/SA3 is off but SA1 is on and the complementary relationship has the second set of lower arm switches SB2/SB3 on but SB1 is off. In this mode then the output level at the intermediate node NX is about zero with respect to NZ. The flying capacitor C11-C12 is placed in a discharged state in this mode and flying capacitor C2 is neither charged nor discharged.

Referring to fig. 4, the on/off combination of the single-arm switch is: the first set of upper arm switches SA1/SA3 is on but SA2 is off and the complementary relationship has the second set of lower arm switches SB1/SB3 is off but SB2 is on. In this mode the output level at the intermediate node NX is then approximately negative U/4 with respect to NZ. The flying capacitor C11-C12 is set to the discharged state in this mode and the flying capacitor C2 charges.

Referring to fig. 4, the on/off combination of the single-arm switch is: the first set of upper arm switches SA1/SA2 is on but SA3 is off and the complementary relationship has the second set of lower arm switches SB1/SB2 is off but SB3 is on. In this mode the output level at the intermediate node NX is then approximately negative U/4 with respect to NZ. The flying capacitor C11-C12 is set to a non-charging and discharging state in this mode and the flying capacitor C2 discharges.

Referring to fig. 4, the on/off combination of the single-arm switch is: the first set of switches SA1-SA3 of the upper arm are all ON and the complementary relationship is such that the second set of switches SB1-SB3 of the lower arm are all OFF. In this mode the output level at the intermediate node NX of the multilevel inverter is then approximately negative U/2 with respect to the intermediate node NZ. The flying capacitor C11-C12 is set to a non-charging and non-discharging state in this mode and the flying capacitor C2 is neither charging nor discharging.

Referring to fig. 7, looking at curve U5, curve U5 is essentially a partial segment of a full alternating current sine wave. If it is intended to take the topology of fig. 4 as the subject of control, an attempt is made to synthesize the curve U5 at the multilevel output voltage output at the single-arm intermediate node NZ with respect to the intermediate node NX, the aforementioned positive U/2 and U/4 timing control schemes may be considered. At time points T4 to T5 on the time axis T, in conjunction with the timing control of fig. 4, the sinusoidal half-wave or partial segment of the sinusoidal half-wave is replaced by a series of narrow pulses of equal amplitude but unequal width, modulated as in the industry SPWM waveform-pulse width varies sinusoidally and is equivalent to a sine wave PWM waveform. The output waveform U5 between the first and second output terminals OUT1-OUT2 is a multi-level output based on the potential of the intermediate node NX relative to the potential V3 of the intermediate node NX as a reference, and in an alternative embodiment, the curve U5 in fig. 7 may illustrate a multi-level output mechanism by generating a forward ripple by using the value of V3 or by using the absolute value thereof as a reference.

Referring to fig. 7, looking at curve U6, curve U6 is essentially a partial segment of a full alternating current sine wave. If it is intended to take the topology of fig. 4 as the controlled object, an attempt is made to synthesize the curve U6 at the multilevel output voltage outputted at the intermediate node NX of the single arm with respect to the intermediate node NZ, the aforementioned timing control schemes of positive U/4 and 0 may be considered. Here too, a series of narrow pulses of equal amplitude but unequal width are used instead of a sinusoidal half-wave or a partial segment of a sinusoidal half-wave. The waveform U6 output between the first output terminal OUT1 and the second output terminal OUT2 of the one-arm and output stage arrangement of the inverter is a multilevel output realized based on the potential of the intermediate node NX relative to the potential V3 at the aforementioned voltage dividing node NZ as a voltage reference, and at time points T5 to T6 of the time axis T, the curve U6 in fig. 7 may explain a multilevel output mechanism by generating a forward ripple at the value of V3 or at the absolute value thereof as a reference value.

Referring to fig. 7, looking at curve U7, curve U7 is essentially a partial segment of a full alternating current sine wave. If one were to attempt to synthesize the curve U7 at the multilevel output voltage output at the single-arm intermediate node NX relative to the intermediate node NZ with the topology of fig. 4 as the subject of control, one could consider the aforementioned 0 and negative U/4 timing control scheme. Here too, a series of narrow pulses of equal amplitude but unequal width are used instead of a sinusoidal half-wave or a partial segment of a sinusoidal half-wave. The waveform U7 output between the first output terminal OUT1 and the second output terminal OUT2 of the one-arm and output stage arrangement of the inverter is a multilevel output realized based on the potential of the intermediate node NX relative to the potential V3 at the aforementioned voltage dividing node NZ as a voltage reference, and at time points T6 to T7 of the time axis T, the curve U7 in fig. 7 may explain a multilevel output mechanism by generating a negative ripple at the value of V3 or at its absolute value as a reference value.

Referring to fig. 7, looking at curve U8, curve U8 is essentially a partial segment of a full alternating current sine wave. If the topology of FIG. 4 is intended to be the subject of control, an attempt is made to synthesize curve U8 at the multi-level output voltage output at the single-arm intermediate node NX relative to the intermediate node NZ, taking into account the negative U/4 and negative U/2 timing control schemes previously described. Here too, a series of narrow pulses of equal amplitude but unequal width are used instead of a sinusoidal half-wave or a partial segment of a sinusoidal half-wave. The waveform U8 output between the first output terminal OUT1 and the second output terminal OUT2 is a multilevel output realized based on the potential of the intermediate node NX relative to the potential V3 at the aforementioned voltage dividing node NZ as a voltage reference, and it is noted that the curve U8 in fig. 7 illustrates a multilevel output mechanism by generating a negative ripple with the value of V3 or with the absolute value thereof as a reference value at time points T7 to T8 of the time axis T. The curves U5-U8 are four consecutive partial segments of a waveform that varies regularly according to a sine wave so that they combine to form a half cycle of the sine wave Curve2 itself over the time period t4 to t 8. In certain embodiments it is considered that during a cycle of the alternating current waveform Curve2, such as t0 to t 8: multi-level output voltages such as positive U/2 and positive U/4 generated by the corresponding reference voltage source V3 as voltage reference in a defined time period, i.e., t4-t5, to synthesize a partial segment U5 of the alternating current Curve2 varying in accordance with a sine wave law in the time period, i.e., time t4-t 5; the multi-level output voltages such as 0 and positive U/4 and negative U/4 and 0 generated by the reference voltage source V3 as the voltage reference in the defined period, i.e., t5 to t7, are synthesized into partial segments U6-U7 of the sine wave alternating current Curve2 varying in accordance with the sine wave law in time t5 to t 7; the multilevel output voltages generated by the respective voltage source V3 as voltage reference during a defined time period, i.e. t7 to t8, such as the negative U/2 and negative U/4 mentioned above, synthesize a partial segment U8 of the alternating current waveform Curve2 which varies in accordance with a sine wave law during this time period, i.e. time t7 to t 8. Thereby achieving a half cycle of the full sine wave Curve 2.

Referring to figure 7, in an alternative embodiment, it is desirable to monitor the actual voltage value of at least a portion of the flying capacitor, such as capacitor C2, and compare the actual voltage value of the flying capacitor C2 being monitored with a desired predetermined value, and select a specified level, such as negative U/4, in driving the single arm to produce a multilevel output voltage, where the predetermined value of the flying capacitor C2 being monitored should be approximately equal to U/4, for example. For example, the partial segment curves U7-U8 that generate a complete sine wave according to the foregoing description use a specified level of negative U/4. The actual voltage value of the monitored flying capacitor C2 is compared to a desired predetermined value U/4: when the actual voltage value sensed by flying capacitor C2 is below a predetermined value, then it is necessary to drive the first and second sets of switches to produce the specified level, for example negative U/4, while simultaneously charging the flying capacitor being monitored, for example with the upper arm first set of switches SA1/SA3 on but SA2 off and the complementary relationship with the lower arm second set of switches SB1/SB3 off but SB2 on, in which mode the output level at intermediate node NX is about a negative U/4 level relative to intermediate node NZ and flying capacitor C2 charges to compensate for the charge. Or the actual voltage value of the monitored flying capacitor C2 is compared to a desired predetermined value U/4: the flying capacitor C2 discharges to compensate for the charge when the actual sensed voltage value of flying capacitor C2 is above a predetermined value, while driving the first and second sets of switches to produce the specified level, e.g., the upper arm first set of switches SA1/SA2 on but SA3 off and the complementary relationship causes the lower arm second set of switches SB1/SB2 off but SB3 on, in which mode the output level at intermediate node NX is about a negative U/4 level relative to intermediate node NZ.

Referring to fig. 7, in other embodiments, the actual voltage value of at least a portion of the flying capacitor, such as capacitors C11-C12, may be monitored, the actual voltage value of the monitored flying capacitors C11-C12 may be compared to a desired predetermined value, and a specified level, such as a zero level, may be selected in driving the single arm to produce a multilevel output voltage, under which condition the total predetermined value of the monitored flying capacitors C11-C12, such as U/2, should be approximately equal. For example, the partial segment curves U2-U3 that generate a complete sine wave according to the foregoing description use the designated level of zero level. The actual voltage values of these monitored flying capacitors C11-C12 are claimed to be compared to a desired predetermined value U/2: when the actual voltage value of the monitored object, i.e., flying capacitors C11-C12, is sensed to be below a predetermined value, then the first and second sets of switches are driven to produce the specified level, e.g., zero level, while the flying capacitors C11-C12 being monitored are simultaneously charged, e.g., as described above, the first set of switches of the upper arm SA2/SA3 is on but SA1 is off and the complementary relationship causes the second set of switches of the lower arm SB2/SB3 to be off but SB1 to be on, in which mode the output level at the intermediate node NX is at about zero level relative to NZ and the flying capacitors C11-C12 are placed in a charged state to compensate for the charge. Or the actual voltage value of the flying capacitor C11-C12 is compared with the expected preset value U/2: the flying capacitor being monitored is simultaneously discharged while driving the first and second sets of switches to produce the specified zero level when the sensed actual voltage value of the flying capacitor is above the predetermined value, e.g., as described above, the first set of switches of the upper arm SA2/SA3 is off but switch SA1 is on and the complementary relationship turns SB2/SB3 of the second set of switches of the lower arm SB1 off, in which mode the output level at the intermediate node NX is about zero level with respect to NZ, and flying capacitors C11-C12 are placed in the discharged state to compensate for the charge. In this embodiment, the timing of the monitored flying capacitors C11-C12 to perform charging or discharging with the actual voltage adjusted to a predetermined value includes the zero crossing point of the ac voltage, the zero crossing points of the partial segment curves U6-U7 representing the complete sine wave of the ac voltage are t6 and t2 of fig. 6, the essence of generating the sine wave is to replace the waveform with a series of narrow pulses of equal amplitude but unequal width, and in the alternative, implementing the charge compensation of the capacitors at the zero crossing point of the ac voltage can avoid distortion of the sine wave to some extent.

Referring to fig. 5, the turning on and off of the first and second sets of switches of the single arm is substantially controlled by a control signal or a modulation signal output from the microprocessor 100, which is not unique in type, such as: logic devices, complex processors or control devices, state machines, controllers, chips, software-driven controls, gate arrays, and/or other equivalent controllers, with pulse width modulated signals PWM generated as desired by the DSP/FPGA being particularly typical. The flying capacitor type multilevel inverter in the application needs to control the size and the phase of grid-connected alternating current besides taking charge of stabilizing the voltage U of a direct current bus, namely balancing input power and output power. The core idea of the application is that an input bus voltage outer ring is multiplied by the phase of an output voltage after being regulated by a PI controller, and the result is used as a set reference value of an inverter output current inner ring, and finally: the inverter inductance current is regulated by a so-called PI controller and is subjected to feedforward control of the grid voltage to form an SPWM (Sinussoidal-PWM) driving signal to drive the operation of the inverter. The PI controller in this application is a linear controller, which forms a control deviation from a given value and an actual value, and linearly combines the proportion and the integral of the deviation to form a control quantity, so as to control an object or a reference quantity to be controlled. The inverter is discussed to be responsible for stabilizing the dc bus voltage, and after the processor collects the above-mentioned various types of data, the specific way in which the inverter clamps the bus voltage U = VD-VR to approach the bus reference voltage VRE can be roughly described as follows: an inner loop PI2 controller based on a grid-connected alternating current IL output by the inverter and an outer loop PI1 controller based on a bus voltage U related to the alternating current grid-connected to the utility power and the bus voltage U related to the actual input voltage VIN of the multilevel inverter are required to generate SPWM modulation signals, which are used to drive switches SA1-SA3 and SB1-SB3 of the inverter circuit to generate alternating current. Closed-loop control of the voltage outer loop and the current inner loop is embodied in that the outer loop PI1 controller sets the bus reference voltage VRE to a given command value (i.e., reference value) and a deviation of the actual input voltage for synchronously adjusting the bus voltage U from the bus reference voltage VRE, and the objective is to automatically reduce such a deviation. According to the design idea that the PLL IS used for detecting the phase information of the grid-connected ac voltage of the inverter and further needs to multiply the current reference value IS given by the outer loop PI1 controller by the phase of the ac voltage output by the inverter to obtain a calculation result, the inner loop PI2 controller sets the calculation result containing the current reference value and the phase information as a given command value (i.e., a reference value) and a deviation of the ac current IL output by the inverter for synchronous regulation to the calculation result, and automatically reduces the deviation. The ac voltage output by the inverter can be negatively fed back to the output of the inner loop PI2 controller because the output current of the inverter is related to the ac grid voltage, which is the same as the ac grid voltage, and the ac voltage is negatively fed back to the inner loop PI2 controller so that the feed forward can be introduced into the current inner loop to cancel the effect of the ac grid voltage. Referring to fig. 5, the SPWM signal generation module is generally referred to as a pulse width signal generator, which may also be referred to as a digital pulse width signal generator, and receives the output of the inner loop PI controller, i.e., the adjustment result, to obtain an SPWM pulse signal, and finally the SPWM signal is used to control the high-frequency switching of the power switch of the inverter, i.e., to drive the single arm of the inverter to generate ac power.

Referring to FIG. 5, the modulation signals C-SA1 through C-SA3 generated by the output of microprocessor 100 are used to drive the first set of switches SA1 through SA3 in the single arm, respectively, and the modulation signals C-SB1 through C-SB3 generated by microprocessor 100 are used to drive the second set of switches SB1 through SB3 in the single arm, respectively. The foregoing has illustrated monitoring the actual voltage value of at least a portion of the flying capacitor, such as by using voltage acquisition circuit SAM in fig. 5 to acquire the voltage of flying capacitors C11-C12 while supplying the actual voltage value of the monitored flying capacitor to microprocessor 100 for analog-to-digital conversion, which also compares the acquired voltage to a desired predetermined value, such as labeled VREF. Comparator a1 is assumed to be an analog comparator or a digitized comparator. A comparison of the actual voltage value of the monitored flying capacitor with a desired predetermined value will always result in a positive comparison, for example the actual voltage value being below the predetermined value or the actual voltage value being above the predetermined value. Selecting a specific level, such as zero level, in the process of driving the single-arm to generate the multi-level output voltage, assuming that the SPWM signal requires HLL as the driving signal coupled to the gates of the switches SA1 to SA3 and LHH as the driving signal coupled to the gates of the switches SB1 to SB3, where H is high and L is low, detecting that the actual voltage value of the capacitors is too low and charging the flying capacitor C11-C12 is required, informing the logic device LOGI of the comparison result that HLL of the driving signal applied to the gates of the switches SA1-SA3 is strongly converted to LHH, and informing the logic device that LHH of the driving signal applied to the gates of the switches SB1-SB3 is strongly converted to HLL, and the logic device commonly has functions of and gate, or gate, not gate, nand gate, nor gate, and nor gate, so that the switches SA 96 1-SA3 are driven by the converted modulation signals C-SA1 to C-SA3 (H) and the switches SB3 are converted to SB 582 (HLL) (HLL-SB 583-C) ) Causes the flying capacitors C11-C12 to charge and meet the purpose of producing a specified level, such as a zero level. It is needless to say that the original modulation signals C-SA1 to C-SA3 (HLL) and C-SB1 to C-SB3 (LHH) would have opposite negative effects if no change was performed, causing the capacitor C11-C12 with too low voltage to continue to discharge, which goes against the spirit of the present invention. Another relative result of the actual voltage values is: assuming that the SPWM signal requires LHH as the driving signal coupled to the respective gates of switches SA1 to SA3 and HLL as the driving signal coupled to the respective gates of switches SB1 to SB3, detecting that the actual voltage value of the capacitors is too high and requires discharge of flying capacitors C11-C12, the comparison result informs logic devices LOGI to forcibly convert the driving signal given to the respective gates of switches SA1-SA3 into HLL, the comparison result informs logic devices to forcibly convert the driving signal given to the respective gates of switches SB1-SB3 into LHH, switches SA1-SA3 are under the driving of the converted modulation signals C-SA1 to C-SA3 (HLL), and a second set of switches SB1-SB3 are under the driving of the converted modulation signals C-SB1 to C-SB3 (LHH) so that flying capacitors C11-C12 are discharged and meet the purpose of generating a specified level of zero, the effect of this voltage equalization is therefore apparent. The microprocessor detects that the sensed voltage is close to a desired predetermined value, such as the labeled VREF, i.e., the actual voltage value of the monitored flying capacitor is approximately equal to the desired predetermined value, the SPWM signal can be used to drive the first and second sets of switches and this comparison informs the logic device LOGI not to interfere with the original high and low logic state levels of the SPWM signal, without any forced switching of the drive signals to the respective gates of the single-arm switches SA1-SA3/SB1-SB 3.

Referring to fig. 8, a method for realizing capacitor voltage balance based on the aforementioned multi-level inverter is also disclosed. Monitoring the actual voltage value of at least a part of the flying capacitors during the balancing of the flying capacitors, namely step S101; and comparing the actual voltage value of the monitored flying capacitor with a desired predetermined value, namely step S102; it is also necessary to drive the single arm to generate the multi-level output voltage and select a specific level from the multi-level output voltage, i.e., step S103. At least two results result from monitoring the actual voltage value of at least a portion of the flying capacitor: the first result is that when the actual voltage value is sensed to be lower than the predetermined value, the first and second sets of switches need to be driven to generate the specified level, and simultaneously the flying capacitor to be monitored needs to be charged, step S104 a; or a second result is that sensing the actual voltage value above the predetermined value requires driving the first and second sets of switches to produce the specified level and simultaneously discharging the monitored flying capacitor, step S104 b. Through the various implementation steps in fig. 8, the actual voltage value of the monitored flying capacitor is adjusted at the time when the specified level is generated until the actual voltage value of the monitored flying capacitor tends to be equal to the desired predetermined value, so as to avoid the voltage of the flying capacitor from generating errors during the charging and discharging processes.

While the above description and drawings represent a typical example of the particular arrangements of the embodiments, the present disclosure is intended to be illustrative of the presently preferred embodiments and is not to be taken in a limiting sense. Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above disclosure. It is therefore intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims of the present application should be considered to be within the intent and scope of the present invention.

Claims

1. A multilevel inverter, comprising:

a single arm for generating a multilevel output voltage having an upper arm and a lower arm connected in series between first and second input terminals, the upper and lower arms being interconnected at a first intermediate node;

first and second reference voltage sources coupled to the first and second input terminals, respectively, with an upper capacitor and a lower capacitor connected in series between the first and second reference voltage sources and coupled at a second intermediate node;

generating a series of said multi-level output voltages at the first intermediate node with the voltage level at the second intermediate node as a voltage reference;

inputting a DC voltage equivalent to the difference between the first and second reference voltage sources between the first and second input terminals and synthesizing a waveform which varies according to a sine wave law and is equivalent to an AC current between the first and second intermediate nodes by a series of the multilevel output voltages;

said single arm comprising a first set of switches, identified as the upper arm, and a second set of switches, identified as the lower arm, connected in series between first and second input terminals; and

one or more flying capacitors are arranged between the interconnection node between any adjacent pair of switches in the first group of switches and the interconnection node between the corresponding adjacent pair of switches in the second group of switches;

monitoring the actual voltage value of at least a part of the flying capacitors, simultaneously comparing the actual voltage value of the monitored flying capacitors with an expected preset value, and selecting a specified level in the process of driving the single arm to generate the multilevel output voltage:

when the actual voltage value is lower than the preset value, the first group of switches and the second group of switches are driven to generate the designated level, and simultaneously the flying capacitor to be monitored is synchronously charged; or

When the actual voltage value is higher than the preset value, the first group of switches and the second group of switches are driven to generate the specified level, and simultaneously, the flying capacitor to be monitored is synchronously discharged;

at least a portion of the monitored flying capacitor is charged or discharged at a time when the actual voltage value is adjusted to the predetermined value, including a zero-crossing point time of the alternating voltage.

2. The multilevel inverter of claim 1, wherein:

generating an SPWM modulation signal by an inner loop PI controller established based on the alternating current output by the multi-level inverter and an outer loop PI controller established based on the direct current voltage;

the outer loop PI controller is used for setting a bus reference voltage as a given instruction value and synchronously adjusting the deviation of the actual input voltage of the multi-level inverter to the bus reference voltage;

the inner loop PI controller is used for setting a result obtained by multiplying a current reference value given by the outer loop PI controller by the phase of the alternating voltage as a given instruction value and synchronously adjusting the deviation of the alternating current output by the multi-level inverter to the result;

the SPWM modulated signal is used to drive first and second sets of switches to produce alternating current.

3. The multilevel inverter of claim 1, wherein:

the first set of switches is ordered from a first switch coupled to the first input to a last switch coupled to the first intermediate node;

the second set of switches is ordered from a first switch coupled to the second input to a last switch coupled to the first intermediate node;

the switches in the first and second sets, each having the same rank, are set to complementary switches with one switched on and the other switched off.

4. The multilevel inverter of claim 1, wherein:

the capacitance value of the upper capacitor is equal to the capacitance value of the lower capacitor.

5. A method for realizing capacitor voltage balance based on a multi-level inverter is characterized by comprising the following steps:

a first group of switches which are regarded as upper arms and a second group of switches which are regarded as lower arms are connected in series between the first input end and the second input end;

the first and second sets of switches are each ordered with the first switch furthest from the first intermediate node to the trailing switch closest to the first intermediate node; and

one or more flying capacitors are connected between the interconnection node between any adjacent pair of switches in the first group of switches and the interconnection node between the corresponding adjacent pair of switches in the second group of switches;

the method comprises the following steps:

monitoring an actual voltage value of at least a portion of the flying capacitor and comparing the actual voltage value of the monitored flying capacitor to a desired predetermined value;

driving the single arm to generate multi-level output voltages and selecting a designated level from the multi-level output voltages;

when the actual voltage value is sensed to be lower than the preset value, the first group of switches and the second group of switches are driven to generate the specified level and simultaneously charge the monitored flying capacitor; or

When the actual voltage value is sensed to be higher than the preset value, the first group of switches and the second group of switches are driven to generate the specified level and simultaneously discharge the monitored flying capacitor;

thereby adjusting the actual voltage value of the monitored flying capacitor at the time when the specified level is generated until the actual voltage value of the monitored flying capacitor tends to be equal to a desired predetermined value;

the timing at which at least a portion of the monitored flying capacitor performs charging or discharging to achieve capacitor voltage balancing by adjusting the actual voltage value to a predetermined value includes the zero-crossing point timing of the alternating voltage.

6. The method of claim 5, wherein:

a plurality of direct current power supplies are directly connected in series between the first and second input terminals; or

A plurality of voltage converters are connected in series between the first input end and the second input end, each voltage converter is used for performing power conversion on electric energy provided by a corresponding direct current power supply, and output voltages of the voltage converters are superposed and then are transmitted to the first input end and the second input end.