CN110620082A - Method for cutting chip and chip - Google Patents
Method for cutting chip and chip Download PDFInfo
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- CN110620082A CN110620082A CN201910908500.8A CN201910908500A CN110620082A CN 110620082 A CN110620082 A CN 110620082A CN 201910908500 A CN201910908500 A CN 201910908500A CN 110620082 A CN110620082 A CN 110620082A
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- chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Abstract
The application provides a chip cutting method and a chip, which can avoid the chip from generating edge burrs in the cutting process. The method comprises the following steps: manufacturing metal coatings on a plurality of chips to be cut; manufacturing a plurality of buffer grooves in the area between two adjacent rows of chips in the plurality of chips with the metal coatings; manufacturing a cutting path between the two rows of chips based on the areas where the plurality of buffer grooves are located; and cutting the chip along the cutting path by using a cutting tool.
Description
Technical Field
The embodiment of the application relates to the technical field of chips, and more particularly relates to a chip cutting method and a chip.
Background
In order to solve the problem of heat dissipation at the top of the chip, a metal plating (BSM) is usually formed on the back surface of the chip, so that heat dissipation is achieved through the metal plating. However, the metal plating may cause the chip to generate edge burrs during the cutting process, thereby causing short circuits between chip pins (pins), and may even cause the chip to burn out.
Disclosure of Invention
The embodiment of the application provides a chip cutting method and a chip, which can avoid the chip from generating edge burrs in the cutting process.
In a first aspect, a method for cutting a chip is provided, which includes: manufacturing metal coatings on a plurality of chips to be cut; manufacturing a plurality of buffer grooves in the area between two adjacent rows of chips in the plurality of chips with the metal coatings; manufacturing a cutting path between the two rows of chips based on the areas where the plurality of buffer grooves are located; and cutting the chip along the cutting path by using a cutting tool.
In a possible implementation manner, the cutting path is located in a region where the plurality of buffer slots are located.
In one possible implementation, the buffer slots are parallel to the chip arrangement direction in each row of chips.
In a possible implementation, the width of the buffer slot is smaller than the width of the cutting track.
In one possible implementation manner, the manufacturing a plurality of buffer slots in a region between two adjacent rows of the plurality of chips with metal coatings includes: and manufacturing the plurality of buffer grooves in the area between the two adjacent rows of chips by using laser.
In a possible implementation manner, the making a scribe line between the two rows of chips based on the area where the plurality of buffer slots are located includes: and manufacturing the cutting channel between the two rows of chips by utilizing laser based on the areas where the plurality of buffer grooves are located.
In one possible implementation, the plurality of buffer slots are equally spaced.
In one possible implementation, the spacing is between 15 and 25 microns.
In one possible implementation, the plurality of buffer slots are distributed at unequal intervals.
In one possible implementation, among the plurality of buffer slots, the closer to the edge of the chip, the smaller the interval between the adjacent buffer slots.
In one possible implementation, the width of the buffer trench is between 60 microns and 100 microns.
In one possible implementation, the depth of the buffer trench is between 80 microns and 120 microns.
In one possible implementation, the number of the plurality of buffer slots is 7.
In a possible implementation manner, the chip is a power calculating chip, and a plurality of power calculating chips having the same structure are disposed on the same circuit board.
In a second aspect, a chip is provided, which is formed on the basis of the first aspect or the method in any possible implementation manner of the first aspect.
In a third aspect, a chip is provided, which includes: the metal coating is positioned on the upper surface of the chip; and a plurality of buffer grooves located at an edge region of the chip.
In one possible implementation, the buffer slot is parallel to the edge of the chip.
In one possible implementation, the plurality of buffer slots are equally spaced.
In one possible implementation, the spacing is between 15 and 25 microns.
In one possible implementation, the plurality of buffer slots are distributed at unequal intervals.
In one possible implementation, among the plurality of buffer slots, the closer to the edge of the chip, the smaller the interval between the adjacent buffer slots.
Based on above-mentioned technical scheme, through preparation a plurality of dashpots on the metal coating of waiting to cut the chip, and based on the regional preparation cutting street at a plurality of dashpots place, thereby utilizing cutting means to follow when carrying out the chip cutting on the cutting street, the dashpot can cushion the stress that produces when cutting, thereby avoids the chip to produce marginal burr in cutting process.
Drawings
FIG. 1 is a schematic view of a chip to be cut.
Fig. 2 is a schematic diagram of the chip cut at a in fig. 1.
Fig. 3 is a schematic view of edge burrs generated during the dicing of a chip.
Fig. 4 is a schematic flow chart of a method of chip dicing of an embodiment of the present application.
Fig. 5 is a schematic view of a buffer tank of one embodiment at B in fig. 1.
Fig. 6 is a schematic view of a buffer tank at B in fig. 1 according to still another embodiment.
Fig. 7 is a schematic view of a buffer tank at B in fig. 1 according to still another embodiment.
Fig. 8 is a schematic view of a buffer tank at B in fig. 1 according to still another embodiment.
Fig. 9 is a schematic flow chart of a possible chip manufacturing method according to an embodiment of the present application.
Detailed Description
The technical solution in the present application will be described below with reference to the accompanying drawings.
Generally, for a chip with high power consumption, in order to solve the heat dissipation problem of the chip, a Back Side Metallization (BSM) process may be used to fabricate a metal plating layer with high thermal conductivity on the surface of the chip. Fig. 1 shows the chips to be cut with the metal plating, only 8 chips being shown in fig. 1, wherein each chip 110 is shown in fig. 2 after cutting. Fig. 2 shows each chip 110 after dicing. As shown in fig. 2, a metal plating layer 120 is formed on a surface of the chip 110 to dissipate heat. However, when dicing a chip, since the metal plating layer 120 has high ductility, burrs are likely to be generated at the edge of the chip due to dicing stress. As shown in fig. 3, due to the existence of the metal plating layer, metal burrs are generated at the edge of the chip when the chip is cut, so that during the subsequent Surface Mount Technology (SMT), short circuits between pins are easily caused by soldering, and the chip is seriously even burned.
Therefore, the scheme for cutting the chip is provided, and edge burrs of the chip can be avoided in the cutting process.
Fig. 4 is a schematic flow chart diagram of a method 400 of die sawing in an embodiment of the present application. As shown in fig. 4, the method 400 includes some or all of the following steps.
At 410, a metal plating is fabricated on the plurality of chips to be cut.
In 420, a plurality of buffer slots are formed in a region between two adjacent rows of the plurality of chips having the metal plating layer.
At 430, dicing streets are made between the two rows of chips based on the areas where the plurality of buffer bins are located.
At 440, a dicing tool is used to cut the chip along the dicing street.
When the chips are cut, a cutting path is usually formed between two adjacent rows of chips. The cutting tool needs to perform chip cutting along the cutting path. However, when the chip is diced, dicing stress is generated at the dicing streets. When the metal plating layer on the surface of the chip is cut, metal burrs are easily generated at the edge of the metal plating layer due to cutting stress. In this embodiment, a plurality of buffer slots are first fabricated in adjacent areas between two rows of chips, wherein the buffer slots are located on the metal plating. Secondly, based on the areas where the plurality of buffer slots are located, a cutting channel is manufactured between two adjacent rows of chips, so that the buffer slots are distributed on two sides of the cutting channel. Like this, when cutting means carries out the chip cutting along the cutting street, the buffer slot of cutting street both sides can absorb the stress that produces when cutting, avoids metal coating to produce metal burr when the cutting, has reduced the roughness at chip edge.
Wherein the cutting tool described in 440 may be a knife, for example.
Optionally, at 420, the plurality of buffer slots may be fabricated in an adjacent area between the two rows of chips using a laser.
The laser cutting step originally existing in the chip cutting process can be utilized, the buffer groove is cut in advance in the adjacent area between two adjacent rows of chips, so that the cutting stress generated when the chips are mechanically cut can be buffered, extra equipment and a new process cannot be introduced, and the cost is reduced.
Optionally, at 430, the scribe line can be made between the two rows of chips using a laser.
Wherein the cutting street may be located in a region where the plurality of buffer slots are located.
The embodiment of the application does not limit the relative position between the cutting channel and the buffer slots, and the buffer slots are distributed on two sides of the cutting channel. For example, when the cutting street is manufactured, the cutting street may cover a part of the plurality of buffer slots; alternatively, when the plurality of buffer slots are manufactured, the positions of the cutting lanes may be reserved so that the cutting lanes do not cover the plurality of buffer slots.
Optionally, the buffer slot is parallel to the chip arrangement direction in each row of chips.
That is, the buffer grooves are parallel to the cut edges of the chips.
Optionally, the width of the buffer slot is smaller than the width of the cutting track.
Wherein, the width of the buffer groove can be between 60 microns and 100 microns. Preferably, the width of the buffer groove is 80 micrometers.
The depth of the buffer reservoir may be, for example, between 80 and 120 microns. Preferably, the depth of the buffer groove is 100 micrometers.
Since the buffer groove is formed on the metal coating, the depth of the buffer groove should be smaller than the thickness of the metal coating, that is, the buffer groove does not penetrate through the metal coating when the buffer groove is formed by laser.
The number of the buffer slots is not limited in the embodiment of the application. For example, the number of the buffer grooves is 6 to 10. Preferably, the number of the buffer slots is 7.
Next, the buffer tank according to the embodiment of the present application will be described by taking fig. 5 to 7 as an example. Fig. 5 to 7 illustrate adjacent regions between any adjacent two chips 110 in fig. 1. As shown in fig. 5 to 7, after metal plating is formed on a plurality of chips to be cut, a plurality of buffer grooves 121 are formed in adjacent regions between two adjacent rows of chips by using a laser. Fig. 5 shows 7 buffer tanks, and fig. 6 and 7 show 8 buffer tanks. Based on the areas where the buffer grooves 121 are located, dicing streets 122 are formed between the adjacent two rows of chips by using a laser.
When the buffer groove 121 and the scribe line 122 are manufactured, they are both in the adjacent area between two rows of chips, and they do not affect each other during the manufacturing. However, the scribe line 122 may overlap the buffer groove 121. In fig. 5 and 6, the scribe line 122 covers the buffer groove 121 in the adjacent region of the two chips 110. In fig. 7, when the buffer grooves 121 are formed in adjacent regions of two chips 110, the positions of the scribe lines are reserved, and thus the scribe lines 122 do not cover the buffer grooves 121. When the buffer groove 121 and the scribe line 122 are formed, the width of the laser used is different. The width of the scribe line 122 shown in fig. 5 to 7 is greater than the width of the buffer groove 121.
As can be seen from fig. 5 to 7, when a cutting tool is used to cut two adjacent rows of chips along the cutting street 122, the cutting stress generated is absorbed by the buffer grooves 121 on both sides of the cutting street 122, so as to avoid burrs on the edges of the cut chips. And because there are buffer slots 121 on both sides of the cutting street 122, the stress produced by cutting can be blocked by the buffer slots 121, and will not further diffuse to the middle area of the chip, prevent the metal plating layer on the surface of the chip from cracking. Meanwhile, in the process of manufacturing the buffer groove 121 at the adjacent area of the two adjacent rows of chips by using laser, the thickness of the metal plating layer at the adjacent area between the two rows of chips can be reduced.
The plurality of buffer grooves shown in fig. 5 to 7 may be equally spaced apart from each other, but the present application is not limited thereto. The plurality of buffer grooves may be distributed at unequal intervals. For example, among the plurality of buffer grooves, the closer to the edge of the chip, the smaller the interval between the adjacent buffer grooves; alternatively, the closer to the chip edge, the greater the spacing between adjacent buffer slots.
For example, as shown in fig. 8, the closer to the cutting street, the more affected the cutting stress. Therefore, the closer to the edge of the chip, the smaller the spacing between adjacent buffer slots becomes for each chip, thereby increasing the density of the buffer slots to absorb more of the cutting stress. And when the distance from the cutting path is farther and farther, the influence of cutting stress is gradually reduced, so that the interval between the adjacent buffer grooves is gradually increased, and the number of the buffer grooves is reduced.
The embodiment of the application does not limit the interval between the adjacent buffer grooves. For example, when the plurality of buffer grooves are distributed at equal intervals, the intervals are between 15 microns and 25 microns. Preferably, the spacing is 20 microns.
The embodiment of the present application does not limit the types of chips. For example, the chip may be a force computing chip.
It should be understood that for a conventional computer, only one computing processor chip, such as a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU), is disposed on a Printed Circuit Board (PCB). For products using computational power chips, a plurality of structurally identical computational processor chips (called computational power chips) are often densely disposed on a single PCB (called computational power board). And, in these power chips, at least two power chips will be connected together through the mode of connecting in series.
Fig. 9 is a schematic flow chart of a possible chip manufacturing method according to an embodiment of the present application. Which comprises the following steps:
at 910, a die is overmolded.
Through the steps, a packaging shell of the chip is formed so as to realize the functions of placing, fixing, sealing, protecting the chip, enhancing the electric heating performance and the like. And it is also a bridge to communicate the chip interior with external circuitry. Wherein the contacts on the chip are connected by wires to pins on the package housing, which in turn may establish connections with other devices via wires on the PCB board.
At 920, each chip is coded with a laser.
For example, each chip is marked with a respective code and other indicia, etc.
At 930, a chip clean and bake is performed.
At 940, the chip is filmed.
And after the film is pasted, a protective film is formed on the surface of the chip so as to protect the chip.
At 950, a metal plating is fabricated.
For example, a metal plating layer is formed on the surface of the chip by sputtering or the like. The metal plating layer can realize the functions of heat dissipation and the like.
At 960, a plurality of buffer tanks are fabricated.
Wherein the plurality of buffer grooves may be formed on the metal plating layer using a laser. The buffer grooves are positioned in the area between two adjacent rows of chips.
At 970, a scribe line is made.
Wherein the cutting lanes may be made using a laser. The cutting path is located in the area where the plurality of buffer grooves are located.
In 980, a die cut is performed.
For example, a cutter is used to cut the chip along the dicing streets.
Because a plurality of dashpots have been made, when utilizing the cutter to carry out the chip cutting along the cutting street, these dashpots can cushion the stress that produces when cutting to avoid the chip to produce marginal burr in cutting process.
It should be noted that, without conflict, the embodiments and/or technical features in the embodiments described in the present application may be arbitrarily combined with each other, and the technical solutions obtained after the combination also fall within the protection scope of the present application.
It should be understood that the specific examples in the embodiments of the present application are for the purpose of promoting a better understanding of the embodiments of the present application, and are not intended to limit the scope of the embodiments of the present application, and that various modifications and variations can be made by those skilled in the art based on the above embodiments and fall within the scope of the present application.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (21)
1. A method of die sawing, the method comprising:
manufacturing metal coatings on a plurality of chips to be cut;
manufacturing a plurality of buffer grooves in the area between two adjacent rows of chips in the plurality of chips with the metal coatings;
manufacturing a cutting path between the two rows of chips based on the areas where the plurality of buffer grooves are located;
and cutting the chip along the cutting path by using a cutting tool.
2. The method of claim 1, wherein the scribe line is located in a region where the plurality of buffer slots are located.
3. The method of claim 1, wherein the buffer slots are parallel to the direction of chip alignment in each row of chips.
4. The method of claim 1, wherein the width of the buffer slot is less than the width of the dicing lane.
5. The method of claim 1, wherein the fabricating a plurality of buffer slots in the area between two adjacent rows of the plurality of chips with metal plating comprises:
and manufacturing the plurality of buffer grooves in the area between the two adjacent rows of chips by using laser.
6. The method of claim 1, wherein the forming a scribe line between the two rows of chips based on the area where the plurality of buffer slots are located comprises:
and manufacturing the cutting channel between the two rows of chips by utilizing laser based on the areas where the plurality of buffer grooves are located.
7. The method of claim 1, wherein the plurality of buffer slots are equally spaced.
8. The method of claim 7, wherein the spacing is between 15 and 25 microns.
9. The method of claim 1, wherein the plurality of buffer bins are non-equally spaced.
10. The method of claim 9, wherein a spacing between adjacent buffer slots is smaller closer to an edge of the chip among the plurality of buffer slots.
11. The method of any one of claims 1 to 10, wherein the width of the buffer reservoir is between 60 and 100 microns.
12. The method of any one of claims 1 to 10, wherein the depth of the buffer reservoir is between 80 and 120 microns.
13. The method of any one of claims 1 to 10, wherein the number of the plurality of buffer tanks is 7.
14. The method according to any one of claims 1 to 10, wherein the chip is a computational chip, and a plurality of computational chips having the same structure are disposed on the same circuit board.
15. A chip formed based on the method of any of the preceding claims 1 to 14.
16. A chip, wherein the chip comprises:
the metal coating is positioned on the upper surface of the chip; and the number of the first and second groups,
and the buffer grooves are positioned in the edge area of the chip.
17. The chip of claim 16, wherein the buffer slot is parallel to an edge of the chip.
18. The chip of claim 16 or 17, wherein the plurality of buffer slots are equally spaced.
19. The chip of claim 18, wherein the spacing is 20 microns.
20. The chip of claim 16 or 17, wherein the plurality of buffer slots are distributed at unequal intervals.
21. The chip of claim 20, wherein the closer to the chip edge of the plurality of buffer slots, the smaller the spacing between adjacent buffer slots.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910908500.8A CN110620082A (en) | 2019-09-25 | 2019-09-25 | Method for cutting chip and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910908500.8A CN110620082A (en) | 2019-09-25 | 2019-09-25 | Method for cutting chip and chip |
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| Publication Number | Publication Date |
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| CN110620082A true CN110620082A (en) | 2019-12-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910908500.8A Pending CN110620082A (en) | 2019-09-25 | 2019-09-25 | Method for cutting chip and chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112590025A (en) * | 2020-12-10 | 2021-04-02 | 浙江美誉建设工程有限公司 | Ceramic tile cutting device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040212047A1 (en) * | 2003-04-22 | 2004-10-28 | Joshi Subhash M. | Edge arrangements for integrated circuit chips |
| CN101950743A (en) * | 2009-07-08 | 2011-01-19 | Lsi公司 | To the inhibition of breaking in the integrated circuit of cutting |
| CN105374762A (en) * | 2014-08-28 | 2016-03-02 | 中芯国际集成电路制造(上海)有限公司 | To-be-cut semiconductor chip structure and manufacturing method thereof |
| CN105470199A (en) * | 2015-12-09 | 2016-04-06 | 华天科技（西安）有限公司 | Separation method for package part with cooling fins |
-
2019
- 2019-09-25 CN CN201910908500.8A patent/CN110620082A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040212047A1 (en) * | 2003-04-22 | 2004-10-28 | Joshi Subhash M. | Edge arrangements for integrated circuit chips |
| CN101950743A (en) * | 2009-07-08 | 2011-01-19 | Lsi公司 | To the inhibition of breaking in the integrated circuit of cutting |
| CN105374762A (en) * | 2014-08-28 | 2016-03-02 | 中芯国际集成电路制造(上海)有限公司 | To-be-cut semiconductor chip structure and manufacturing method thereof |
| CN105470199A (en) * | 2015-12-09 | 2016-04-06 | 华天科技（西安）有限公司 | Separation method for package part with cooling fins |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112590025A (en) * | 2020-12-10 | 2021-04-02 | 浙江美誉建设工程有限公司 | Ceramic tile cutting device |
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Application publication date: 20191227 |